Krnl_IGL_SimplifArbiter.cl 2.6 KB
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// --------------------------------------------------------------------------
// IGL_Arbiter keeps checking whether any kernel (GA or any LSs) 
// is sending genotypes to Conform, as well as whether 
// GA sent the "turn-off" signal.
// Its name references the logic that is producing genotypes: 
// IC, GG and any LS.
// IC and GG are two logic blocks inside the GA kernel,
// while any LS logic is a kernel itself.

// It uses the valid signals to determine the "mode" value,
// used as a mux selector signal (of genotype logic-producers) in Conform.

// Initially genotypes passed through this kernel getting reordered and 
// synchronized with "mode".
// This has been later optimized, so now genotypes go directly 
// from producer logic/kernel (IC, GG, LSs) to the consumer (Conform) kernel.
// --------------------------------------------------------------------------
__kernel __attribute__ ((reqd_work_group_size(1,1,1)))
void Krnl_IGL_Arbiter(/*unsigned char DockConst_num_of_genes*/
#if !defined(SW_EMU)
		// IMPORTANT: enable this dummy global argument only for "hw" build.
		// Check ../common_xilinx/utility/boards.mk
		// https://forums.xilinx.com/t5/SDAccel/ERROR-KernelCheck-83-114-in-sdx-2017-4/td-p/818135
		__global int *dummy
#endif
) {

	char active = 0x01;

	// Only for debugging
	/*
	uint LS1_eval = 0;
	uint LS2_eval = 0;
	uint LS3_eval = 0;
	*/

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	__attribute__((xcl_pipeline_loop))
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	LOOP_WHILE_IGL_MAIN:
	while(active) {
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		nb_pipe_status Off_valid = PIPE_STATUS_FAILURE;
		nb_pipe_status IC_valid	 = PIPE_STATUS_FAILURE;
		nb_pipe_status GG_valid	 = PIPE_STATUS_FAILURE;
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		int Off_active;
		int IC_active;
		int GG_active;

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		__attribute__((xcl_pipeline_loop))
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		LOOP_WHILE_IGL_INNER:
		while (
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			(Off_valid     != PIPE_STATUS_SUCCESS) &&
			(IC_valid      != PIPE_STATUS_SUCCESS) &&  
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			(GG_valid      != PIPE_STATUS_SUCCESS)
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		){
			Off_valid     = read_pipe(chan_IGLArbiter_Off,     &Off_active);
			IC_valid      = read_pipe(chan_GA2IGL_IC_active,   &IC_active);
			GG_valid      = read_pipe(chan_GA2IGL_GG_active,   &GG_active);
		}
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		active = (Off_valid == PIPE_STATUS_SUCCESS)? 0x00 : 0x01;
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		// Send "mode" to Conform
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		const char mode_Off  = 0x00;
		const char mode_IC   = 'I';
		const char mode_GG   = 'G';
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		char mode_tmp = (Off_valid == PIPE_STATUS_SUCCESS)? mode_Off : 
				(IC_valid  == PIPE_STATUS_SUCCESS)? mode_IC : mode_GG;
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		write_pipe_block(chan_IGL2Conform_actmode, &mode_tmp);
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		//printf("IGL Simplif sent!\n");
	} // End of while (active)
}
// --------------------------------------------------------------------------
// --------------------------------------------------------------------------