drastic: all float-point + deeper block chann + expli order enforced
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Owner
Modifications
- In order to eliminate innacuracies that could be introduced by a fixed-point representation, all kernels were expressed in floating point (despite this might make design slower).
- In
Krnl_GA
, all data-passing channels were read and written in blocking calls: note that IC and GG reading of energies was re-arranged to increase speed. - In
Krnl_GA
, explicit order of channel calls, local memory operations and all computing blocks was manually/explicitly enforced usingbool
flags. - In
Krnl_Conform
andKrnl_Intra
, the local memory initialization was enforced manually to happen before main computation loop.
It seems that the explicit enforcement for operation order implemented in this commit, ensures a design free of hangs when using blocking channels in
Krnl_GA
.Results of FPGA fitting process:
Fitter Status Successful - Thu Jul 12 16:09:27 2018 Quartus Prime Version 16.0.2 Build 222 07/20/2016 Patches 2.06 SJ Pro Edition Revision Name top Top-level Entity Name top Family Arria 10 Device 10AX115H3F34I2SG Timing Models Final Logic utilization (in ALMs) 130,144 / 427,200 ( 30 % ) Total registers 267005 Total pins 169 / 618 ( 27 % ) Total virtual pins 0 Total block memory bits 33,825,787 / 55,562,240 ( 61 % ) Total RAM Blocks 1,940 / 2,713 ( 72 % ) Total DSP Blocks 224 / 1,518 ( 15 % ) Total HSSI RX channels 8 / 24 ( 33 % ) Total HSSI TX channels 8 / 24 ( 33 % ) Total PLLs 30 / 80 ( 38 % ) DC4b (FPL/FSP) - full lga This commit - only-ga Freq 187.5 MHz 175.9 MHz Best E, Best clusterSize, Time (Kcal/mol), (no units), (sec) 3ptb -5.53, 66/100, 211 -5.25, 32/100, 148 1stp -7.76, 69/100, 385 -6.05, 29/100, 339 4hmg -4.11, 25/100, 623 -1.08, no clustering, 435 3ce3 -10.88, 48/100, 1077 -9.84, 7/100, 835 3c1x -12.61, 22/100, 1487 -4.67, 3/100, 1247 Docking quality (energy/clustering) will be analyzed at this point.
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