Commit 30e7403f authored by Leonardo Solis's avatar Leonardo Solis
Browse files

added first ga-intel171

parent 1d2c5bc1
#!/bin/bash
# This is created to automate the boring
# process of setting AOC in celebdil
# DO NOT FORGET to run it using:
# >source init_aoc_esa.sh
echo "======================================="
echo ""
echo "==============================================="
echo "Setting up Altera OpenCL SDK & Compiler"
echo "======================================="
echo ""
echo "Run: $ source init_aoc171_nalla510t.sh"
echo "or if Ubuntu: $ bash init_aoc171_nalla510t.sh"
echo "==============================================="
echo ""
export LM_LICENSE_FILE=/opt/cad/keys/altera
......@@ -13,26 +19,36 @@ echo "LM_LICENSE_FILE: "
echo $LM_LICENSE_FILE
echo " "
export PATH=/opt/altera-16.0_pro/quartus/bin/:$PATH
echo "PATH: "
echo $PATH
export ALTERAROOT=/opt/altera-17.1_pro/
echo "ALTERAROOT: "
echo $ALTERAROOT
echo " "
export ALTERAOCLSDKROOT=/opt/altera-16.0_pro/hld
echo "ALTERAOCLSDKROOT: "
export ALTERAOCLSDKROOT=$ALTERAROOT/hld
echo "ALTERAOCLSDKROOT (used before v.17): "
echo $ALTERAOCLSDKROOT
echo " "
export AOCL_BOARD_PACKAGE_ROOT=/opt/altera-16.0_pro/hld/board/Proc10A_16.0.2
export INTELFPGAOCLSDKROOT=$ALTERAOCLSDKROOT
echo "INTELFPGAOCLSDKROOT (used from v.17 on): "
echo $INTELFPGAOCLSDKROOT
echo " "
export PATH=$INTELFPGAOCLSDKROOT/bin/:$PATH
echo "PATH: "
echo $PATH
echo " "
export AOCL_BOARD_PACKAGE_ROOT=$INTELFPGAOCLSDKROOT/board/nalla_pcie
echo "AOCL_BOARD_PACKAGE_ROOT: "
echo $AOCL_BOARD_PACKAGE_ROOT
echo " "
source $ALTERAOCLSDKROOT/init_opencl.sh
source $INTELFPGAOCLSDKROOT/init_opencl.sh
echo " "
echo "List of available boards "
aoc --list-boards
aoc -list-boards
echo " "
echo "Altera OpenCL SDK version: "
......@@ -40,5 +56,6 @@ aocl version
echo " "
echo "Altera OpenCL Compiler version: "
aoc --version
aoc -version
echo " "
# This is created to automate the boring
# process of setting AOC in celebdil
# DO NOT FORGET to run it using:
# >source init_aoc_esa.sh
echo "======================================="
echo "Setting up Altera OpenCL SDK & Compiler"
echo "======================================="
echo ""
export LM_LICENSE_FILE=/opt/cad/keys/altera
echo "LM_LICENSE_FILE: "
echo $LM_LICENSE_FILE
echo " "
export PATH=/opt/cad/altera/altera-16.1/quartus/bin/:$PATH
echo "PATH: "
echo $PATH
echo " "
export ALTERAOCLSDKROOT=/opt/cad/altera/altera-16.1/hld
echo "ALTERAOCLSDKROOT: "
echo $ALTERAOCLSDKROOT
echo " "
export AOCL_BOARD_PACKAGE_ROOT=$ALTERAOCLSDKROOT/board/a10_ref
echo "AOCL_BOARD_PACKAGE_ROOT: "
echo $AOCL_BOARD_PACKAGE_ROOT
echo " "
source $ALTERAOCLSDKROOT/init_opencl.sh
echo " "
echo "List of available boards "
aoc --list-boards
echo " "
echo "Altera OpenCL SDK version: "
aocl version
echo " "
echo "Altera OpenCL Compiler version: "
aoc --version
echo " "
#!/bin/bash
# This is created to automate the boring
# process of setting AOC in celebdil
# DO NOT FORGET to run it using:
# >source init_aoc_esa.sh
echo "======================================="
echo ""
echo "==============================================="
echo "Setting up Altera OpenCL SDK & Compiler"
echo "======================================="
echo ""
echo "Run: $ source init_aoc171_nalla510t.sh"
echo "or if Ubuntu: $ bash init_aoc171_nalla510t.sh"
echo "==============================================="
echo ""
export LM_LICENSE_FILE=/opt/cad/keys/altera
......@@ -13,26 +19,36 @@ echo "LM_LICENSE_FILE: "
echo $LM_LICENSE_FILE
echo " "
export PATH=/opt/cad/altera/altera-16.0/quartus/bin/:$PATH
echo "PATH: "
echo $PATH
export ALTERAROOT=/opt/cad/altera/altera-17.1.0.240
echo "ALTERAROOT: "
echo $ALTERAROOT
echo " "
export ALTERAOCLSDKROOT=/opt/cad/altera/altera-16.0/hld
echo "ALTERAOCLSDKROOT: "
export ALTERAOCLSDKROOT=$ALTERAROOT/hld
echo "ALTERAOCLSDKROOT (used before v.17): "
echo $ALTERAOCLSDKROOT
echo " "
export AOCL_BOARD_PACKAGE_ROOT=~/BSP_AOC_GIDEL/Proc10A_16.0.2/
export INTELFPGAOCLSDKROOT=$ALTERAOCLSDKROOT
echo "INTELFPGAOCLSDKROOT (used from v.17 on): "
echo $INTELFPGAOCLSDKROOT
echo " "
export PATH=$INTELFPGAOCLSDKROOT/bin/:$PATH
echo "PATH: "
echo $PATH
echo " "
#export AOCL_BOARD_PACKAGE_ROOT=~/BSP_AOC_GIDEL/Proc10A_16.0.2/
export AOCL_BOARD_PACKAGE_ROOT=~/BSP_AOC_NALLA510T/nalla_pcie
echo "AOCL_BOARD_PACKAGE_ROOT: "
echo $AOCL_BOARD_PACKAGE_ROOT
echo " "
source $ALTERAOCLSDKROOT/init_opencl.sh
source $INTELFPGAOCLSDKROOT/init_opencl.sh
echo " "
echo "List of available boards "
aoc --list-boards
aoc -list-boards
echo " "
echo "Altera OpenCL SDK version: "
......@@ -40,5 +56,6 @@ aocl version
echo " "
echo "Altera OpenCL Compiler version: "
aoc --version
aoc -version
echo " "
......@@ -76,7 +76,9 @@ TARGET_DIR_HW_PROF := bin_hw_profile
# Directories
#INC_DIRS := ../common/inc
INC_DIRS := ../common/inc wrapcl/inc host/inc ./
#INC_DIRS := ../common/inc wrapcl/inc host/inc ./
# Power Nallatech 510T (saruman server)
INC_DIRS := ../common/inc wrapcl/inc host/inc ./ $(AOCL_BOARD_PACKAGE_ROOT)/software/include/
LIB_DIRS :=
# Files
......@@ -264,18 +266,18 @@ FIPO_FLAG = $(FIPOCO_FLAG) $(FIPOIE_FLAG) $(FIPOIA_FLAG) \
# custom: 12KB = 12288 Bytes
CUSTOMSIZE_CONSTMEM = YES
# relax the order of fp operations: --fp-relaxed
# reduce fp rounding operations: --fpc
# relax the order of fp operations: -fp-relaxed
# reduce fp rounding operations: -fpc
RELAXED_REDUCED_FLOATINGPOINT = YES
ifeq ($(CUSTOMSIZE_CONSTMEM), YES)
CUSTOMSIZE_CONSTMEM_FLAG=--const-cache-bytes 12288
CUSTOMSIZE_CONSTMEM_FLAG=-const-cache-bytes=12288
else
CUSTOMSIZE_CONSTMEM_FLAG=
endif
ifeq ($(RELAXED_REDUCED_FLOATINGPOINT), YES)
RELAXED_REDUCED_FLOATINGPOINT_FLAG=--fp-relaxed --fpc
RELAXED_REDUCED_FLOATINGPOINT_FLAG=-fp-relaxed -fpc
else
RELAXED_REDUCED_FLOATINGPOINT_FLAG=
endif
......@@ -336,8 +338,8 @@ PROJECT_NAME := ofdock_taskpar_alt
DEV_DIRS := device
KRNL_NAME:= Krnl_GA
DEV_SRC := $(DEV_DIRS)/$(KRNL_NAME).cl
BOARD := Proc10A_X115
#BOARD := a10gx
#BOARD := Proc10A_X115
BOARD := p510t_sch_ax115
## Make it all: compilation (host & device) + run emulation
## Notice, it switches automatically to /bin folder
......@@ -350,7 +352,7 @@ BOARD := Proc10A_X115
# $(KRNL_NAME).aoco
# $(KRNL_NAME).aocx
keremu: $(DEV_SRC)
aoc -march=emulator -v --board $(BOARD) $(DEV_SRC) -o $(TARGET_DIR)/$(KRNL_NAME).aocx $(REP) $(FIPO_FLAG) $(AOC_FLAG) -g
aoc -march=emulator -emulator-channel-depth-model=strict -v -board=$(BOARD) $(DEV_SRC) -o $(TARGET_DIR)/$(KRNL_NAME).aocx $(REP) $(FIPO_FLAG) $(AOC_FLAG) -g
@echo $(newline)
@echo "=============================================================================="
@echo "INFO: emulation files are under: \"$(TARGET_DIR)/$(KRNL_NAME)(.aoco)(.aocx)\" "
......@@ -364,7 +366,7 @@ keremu: $(DEV_SRC)
# So .dlg file is written in $(TARGET_DIR)
emu: $(TARGET_DIR)/$(TARGET) keremu
cd $(TARGET_DIR) && \
CL_CONTEXT_EMULATOR_DEVICE_ALTERA=1 ./$(TARGET) \
CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./$(TARGET) \
-ffile ../input/$(PDB)/derived/$(PDB)_protein.maps.fld \
-lfile ../input/$(PDB)/derived/$(PDB)_ligand.pdbqt \
-psize $(PSIZE) -nrun $(NRUN) -nev $(NEV) -ngen $(NGEN) -gfpop 1
......@@ -382,7 +384,7 @@ emu: $(TARGET_DIR)/$(TARGET) keremu
# $(KRNL_NAME).aoco
# No actual hardware is built (NO .aocx)
kerrpt: $(DEV_SRC)
aoc --board $(BOARD) $(DEV_SRC) -o $(TARGET_DIR_RPT)/$(KRNL_NAME).aoco $(REP) $(FIPO_FLAG) $(AOC_FLAG) -c --report -g
aoc -board=$(BOARD) $(DEV_SRC) -o $(TARGET_DIR_RPT)/$(KRNL_NAME).aoco $(REP) $(FIPO_FLAG) $(AOC_FLAG) -c -report -g
@echo $(newline)
@echo "====================================================================================="
@echo "INFO: THIS WORKS ONLY FROM V16.1 ON: "
......@@ -401,7 +403,7 @@ kerrpt: $(DEV_SRC)
# $(KRNL_NAME).aoco
# $(KRNL_NAME).aocx
hw:
aoc --board $(BOARD) $(DEV_SRC) -o $(TARGET_DIR_HW)/$(KRNL_NAME).aocx $(FIPO_FLAG) $(AOC_FLAG)
aoc -board=$(BOARD) $(DEV_SRC) -o $(TARGET_DIR_HW)/$(KRNL_NAME).aocx $(FIPO_FLAG) $(AOC_FLAG)
@echo $(newline)
@echo "==============================================================================="
@echo "INFO: FPGA bitstream is under: \"$(TARGET_DIR_HW)/$(KRNL_NAME)(.aoco)(.aocx)\" "
......@@ -410,7 +412,7 @@ hw:
hw-he:
aoc --high-effort --board $(BOARD) $(DEV_SRC) -o $(TARGET_DIR_HW)/$(KRNL_NAME).aocx $(FIPO_FLAG) $(AOC_FLAG)
aoc --high-effort -board=$(BOARD) $(DEV_SRC) -o $(TARGET_DIR_HW)/$(KRNL_NAME).aocx $(FIPO_FLAG) $(AOC_FLAG)
@echo $(newline)
@echo "==============================================================================="
@echo "INFO: FPGA bitstream is under: \"$(TARGET_DIR_HW)/$(KRNL_NAME)(.aoco)(.aocx)\" "
......@@ -425,13 +427,24 @@ hw-he:
# $(KRNL_NAME).aoco
# $(KRNL_NAME).aocx
hw-prof:
aoc --profile --board $(BOARD) $(DEV_SRC) -o $(TARGET_DIR_HW_PROF)/$(KRNL_NAME).aocx $(FIPO_FLAG) $(AOC_FLAG)
aoc --profile -board=$(BOARD) $(DEV_SRC) -o $(TARGET_DIR_HW_PROF)/$(KRNL_NAME).aocx $(FIPO_FLAG) $(AOC_FLAG)
@echo $(newline)
@echo "================================================================================================="
@echo "INFO: instrumented FPGA bitstream is under: \"$(TARGET_DIR_HW_PROF)/$(KRNL_NAME)(.aoco)(.aocx)\" "
@echo "================================================================================================="
@echo $(newline)
# Execute on remote server
# Host-recompilation
# Copy of host to $(TARGET_DIR_HW)
# The working directory is changed
# So .dlg file is written in $(TARGET_DIR_HW)
MEASURE_POWER := NO
ifeq ($(MEASURE_POWER), YES)
POWER_FLAG=1
else
POWER_FLAG=0
endif
# Execute on remote server
# Host-recompilation
......@@ -445,7 +458,8 @@ exe: $(TARGET_DIR)/$(TARGET)
-ffile ../input/$(PDB)/derived/$(PDB)_protein.maps.fld \
-lfile ../input/$(PDB)/derived/$(PDB)_ligand.pdbqt \
-resnam docking_$(PDB)_$(NRUN) \
-nrun $(NRUN) -gfpop $(GFPOP)
-nrun $(NRUN) -gfpop $(GFPOP) \
-power $(POWER_FLAG)
@echo $(newline)
@echo "========================================================================="
@echo "INFO: log file is under: \"$(TARGET_DIR_HW)/docking_$(PDB)_$(NRUN).dlg\" "
......@@ -477,7 +491,7 @@ COPY_DIR_DOCK := $(PROJECT_NAME)
# Make sure this remote-server alias exists (in ~/.ssh/config)
SERVER_BRIDGE := erebor:/scratch/
SERVER_EXEC := sauron:~/ocladock_only-ga
SERVER_EXEC := saruman:~/ocladock-fpga/ga-intel171
# Delete an existing folder if previously created
# Create a folder $(COPY_DIR) in the parent directory
......
......@@ -82,7 +82,7 @@ while(active) {
#if 0
char2 actmode = read_channel_altera(chan_IGL2Conform_actmode);
#endif
char actmode = read_channel_altera(chan_IGL2Conform_actmode);
char actmode = read_channel_intel(chan_IGL2Conform_actmode);
mem_fence(CLK_CHANNEL_MEM_FENCE);
#if 0
......@@ -104,18 +104,18 @@ while(active) {
for (uchar i=0; i<DockConst_num_of_genes; i++) {
float fl_tmp;
switch (mode) {
case 'I': fl_tmp = read_channel_altera(chan_IC2Conf_genotype); break;
case 'G': fl_tmp = read_channel_altera(chan_GG2Conf_genotype); break;
case 'I': fl_tmp = read_channel_intel(chan_IC2Conf_genotype); break;
case 'G': fl_tmp = read_channel_intel(chan_GG2Conf_genotype); break;
/*
case 0x01: fl_tmp = read_channel_altera(chan_LS2Conf_LS1_genotype); break;
case 0x02: fl_tmp = read_channel_altera(chan_LS2Conf_LS2_genotype); break;
case 0x03: fl_tmp = read_channel_altera(chan_LS2Conf_LS3_genotype); break;
case 0x04: fl_tmp = read_channel_altera(chan_LS2Conf_LS4_genotype); break;
case 0x05: fl_tmp = read_channel_altera(chan_LS2Conf_LS5_genotype); break;
case 0x06: fl_tmp = read_channel_altera(chan_LS2Conf_LS6_genotype); break;
case 0x07: fl_tmp = read_channel_altera(chan_LS2Conf_LS7_genotype); break;
case 0x08: fl_tmp = read_channel_altera(chan_LS2Conf_LS8_genotype); break;
case 0x09: fl_tmp = read_channel_altera(chan_LS2Conf_LS9_genotype); break;
case 0x01: fl_tmp = read_channel_intel(chan_LS2Conf_LS1_genotype); break;
case 0x02: fl_tmp = read_channel_intel(chan_LS2Conf_LS2_genotype); break;
case 0x03: fl_tmp = read_channel_intel(chan_LS2Conf_LS3_genotype); break;
case 0x04: fl_tmp = read_channel_intel(chan_LS2Conf_LS4_genotype); break;
case 0x05: fl_tmp = read_channel_intel(chan_LS2Conf_LS5_genotype); break;
case 0x06: fl_tmp = read_channel_intel(chan_LS2Conf_LS6_genotype); break;
case 0x07: fl_tmp = read_channel_intel(chan_LS2Conf_LS7_genotype); break;
case 0x08: fl_tmp = read_channel_intel(chan_LS2Conf_LS8_genotype); break;
case 0x09: fl_tmp = read_channel_intel(chan_LS2Conf_LS9_genotype); break;
*/
}
......@@ -401,18 +401,18 @@ while(active) {
// Send ligand atomic coordinates to channel
// --------------------------------------------------------------
/*
write_channel_altera(chan_Conf2Intere_active, active);
write_channel_altera(chan_Conf2Intrae_active, active);
write_channel_intel(chan_Conf2Intere_active, active);
write_channel_intel(chan_Conf2Intrae_active, active);
mem_fence(CLK_CHANNEL_MEM_FENCE);
write_channel_altera(chan_Conf2Intere_mode, mode);
write_channel_altera(chan_Conf2Intrae_mode, mode);
write_channel_intel(chan_Conf2Intere_mode, mode);
write_channel_intel(chan_Conf2Intrae_mode, mode);
mem_fence(CLK_CHANNEL_MEM_FENCE);
//float3 position_xyz;
for (uchar pipe_cnt=0; pipe_cnt<DockConst_num_of_atoms; pipe_cnt++) {
write_channel_altera(chan_Conf2Intere_xyz, loc_coords[pipe_cnt]);
write_channel_altera(chan_Conf2Intrae_xyz, loc_coords[pipe_cnt]);
write_channel_intel(chan_Conf2Intere_xyz, loc_coords[pipe_cnt]);
write_channel_intel(chan_Conf2Intrae_xyz, loc_coords[pipe_cnt]);
}*/
......@@ -423,8 +423,8 @@ while(active) {
char mode_tmp = mode;
char2 actmode = {active_tmp, mode_tmp};
write_channel_altera(chan_Conf2Intere_actmode, actmode);
write_channel_altera(chan_Conf2Intrae_actmode, actmode);
write_channel_intel(chan_Conf2Intere_actmode, actmode);
write_channel_intel(chan_Conf2Intrae_actmode, actmode);
}
mem_fence(CLK_CHANNEL_MEM_FENCE);
......@@ -438,8 +438,8 @@ while(active) {
float3 tmp = loc_coords[pipe_cnt];
#endif
write_channel_altera(chan_Conf2Intere_xyz, tmp);
write_channel_altera(chan_Conf2Intrae_xyz, tmp);
write_channel_intel(chan_Conf2Intere_xyz, tmp);
write_channel_intel(chan_Conf2Intrae_xyz, tmp);
}
*/
......@@ -450,8 +450,8 @@ while(active) {
char mode_tmp = mode;
char2 actmode = {active_tmp, mode_tmp};
#endif
write_channel_altera(chan_Conf2Intere_actmode, /*actmode*/ mode);
write_channel_altera(chan_Conf2Intrae_actmode, /*actmode*/ mode);
write_channel_intel(chan_Conf2Intere_actmode, /*actmode*/ mode);
write_channel_intel(chan_Conf2Intrae_actmode, /*actmode*/ mode);
}
mem_fence(CLK_CHANNEL_MEM_FENCE);
......@@ -483,8 +483,8 @@ while(active) {
tmp.s4 = tmp_coords[1].x; tmp.s5 = tmp_coords[1].y; tmp.s6 = tmp_coords[1].z; //tmp.s7
#endif
write_channel_altera(chan_Conf2Intere_xyz, tmp);
write_channel_altera(chan_Conf2Intrae_xyz, tmp);
write_channel_intel(chan_Conf2Intere_xyz, tmp);
write_channel_intel(chan_Conf2Intrae_xyz, tmp);
}
// --------------------------------------------------------------
......
// Enable the channels extension
#pragma OPENCL EXTENSION cl_altera_channels : enable
// Enable the Intel channels extension
// Programming Guide v17.1 / 5.4.5
#pragma OPENCL EXTENSION cl_intel_channels : enable
//IC: initial calculation of energy of populations
//GG: genetic generation
......@@ -172,7 +173,7 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
// ------------------------------------------------------------------
for (ushort pop_cnt = 0; pop_cnt < DockConst_pop_size; pop_cnt++) {
// Calculate energy
write_channel_altera(chan_GA2IGL_IC_active, true);
write_channel_intel(chan_GA2IGL_IC_active, true);
mem_fence(CLK_CHANNEL_MEM_FENCE);
for (uchar pipe_cnt=0; pipe_cnt<DockConst_num_of_genes; pipe_cnt++) {
......@@ -184,7 +185,7 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
LocalPopCurr[pop_cnt][pipe_cnt & MASK_GENOTYPE] = GlobPopulationCurrent[pop_cnt*ACTUAL_GENOTYPE_LENGTH + pipe_cnt];
#endif
write_channel_altera(chan_IC2Conf_genotype, LocalPopCurr[pop_cnt][pipe_cnt & MASK_GENOTYPE]);
write_channel_intel(chan_IC2Conf_genotype, LocalPopCurr[pop_cnt][pipe_cnt & MASK_GENOTYPE]);
#endif
#if 1
......@@ -196,7 +197,7 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
#endif
LocalPopCurr[pop_cnt][pipe_cnt & MASK_GENOTYPE] = tmp_ic;
write_channel_altera(chan_IC2Conf_genotype, tmp_ic);
write_channel_intel(chan_IC2Conf_genotype, tmp_ic);
#endif
}
......@@ -212,19 +213,19 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
bool inter_valid = false;
while( (intra_valid == false) || (inter_valid == false)) {
if (intra_valid == false) {
energyIA_IC_rx = read_channel_nb_altera(chan_Intrae2StoreIC_intrae, &intra_valid);
energyIA_IC_rx = read_channel_nb_intel(chan_Intrae2StoreIC_intrae, &intra_valid);
}
else if (inter_valid == false) {
energyIE_IC_rx = read_channel_nb_altera(chan_Intere2StoreIC_intere, &inter_valid);
energyIE_IC_rx = read_channel_nb_intel(chan_Intere2StoreIC_intere, &inter_valid);
}
}
#endif
#if 0
mem_fence(CLK_CHANNEL_MEM_FENCE);
float energyIA_IC_rx = read_channel_altera(chan_Intrae2StoreIC_intrae);
float energyIA_IC_rx = read_channel_intel(chan_Intrae2StoreIC_intrae);
mem_fence(CLK_CHANNEL_MEM_FENCE);
float energyIE_IC_rx = read_channel_altera(chan_Intere2StoreIC_intere);
float energyIE_IC_rx = read_channel_intel(chan_Intere2StoreIC_intere);
#endif
LocalEneCurr[pop_cnt] = energyIA_IC_rx + energyIE_IC_rx;
......@@ -317,7 +318,7 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
// Get ushort binary_tournament selection prngs (parent index)
// Get float binary_tournament selection prngs (tournament rate)
float8 bt_tmp = read_channel_altera(chan_PRNG2GA_BT_ushort_float_prng);
float8 bt_tmp = read_channel_intel(chan_PRNG2GA_BT_ushort_float_prng);
mem_fence(CLK_CHANNEL_MEM_FENCE);
// Convert: float prng that must be still converted to short
......@@ -369,7 +370,7 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
// get uchar genetic_generation prngs (gene index)
// get float genetic_generation prngs (mutation rate)
uchar2 prng_GG_C = read_channel_altera(chan_PRNG2GA_GG_uchar_prng);
uchar2 prng_GG_C = read_channel_intel(chan_PRNG2GA_GG_uchar_prng);
mem_fence(CLK_CHANNEL_MEM_FENCE);
uchar covr_point_low;
......@@ -388,12 +389,12 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
// Reuse of bt prng float as crossover-rate
bool crossover_yes = (DockConst_crossover_rate > bt_tmp_f0);
write_channel_altera(chan_GA2IGL_GG_active, true);
write_channel_intel(chan_GA2IGL_GG_active, true);
mem_fence(CLK_CHANNEL_MEM_FENCE);
for (uchar gene_cnt=0; gene_cnt<DockConst_num_of_genes; gene_cnt++) {
float prngGG = read_channel_altera(chan_PRNG2GA_GG_float_prng);
float prngGG = read_channel_intel(chan_PRNG2GA_GG_float_prng);
mem_fence(CLK_CHANNEL_MEM_FENCE);
float tmp_offspring;
......@@ -428,7 +429,7 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
// Calculate energy
LocalPopNext [new_pop_cnt][gene_cnt & MASK_GENOTYPE] = tmp_offspring;
write_channel_altera(chan_GG2Conf_genotype, tmp_offspring);
write_channel_intel(chan_GG2Conf_genotype, tmp_offspring);
}
#if defined (DEBUG_KRNL_GG)
......@@ -443,19 +444,19 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
bool inter_valid = false;
while( (intra_valid == false) || (inter_valid == false)) {
if (intra_valid == false) {
energyIA_GG_rx = read_channel_nb_altera(chan_Intrae2StoreGG_intrae, &intra_valid);
energyIA_GG_rx = read_channel_nb_intel(chan_Intrae2StoreGG_intrae, &intra_valid);
}
else if (inter_valid == false) {
energyIE_GG_rx = read_channel_nb_altera(chan_Intere2StoreGG_intere, &inter_valid);
energyIE_GG_rx = read_channel_nb_intel(chan_Intere2StoreGG_intere, &inter_valid);
}
}
#endif
#if 0
mem_fence(CLK_CHANNEL_MEM_FENCE);
float energyIA_GG_rx = read_channel_altera(chan_Intrae2StoreGG_intrae);
float energyIA_GG_rx = read_channel_intel(chan_Intrae2StoreGG_intrae);
mem_fence(CLK_CHANNEL_MEM_FENCE);
float energyIE_GG_rx = read_channel_altera(chan_Intere2StoreGG_intere);
float energyIE_GG_rx = read_channel_intel(chan_Intere2StoreGG_intere);
#endif
LocalEneNext[new_pop_cnt] = energyIA_GG_rx + energyIE_GG_rx;
......@@ -493,13 +494,13 @@ void Krnl_GA(__global float* restrict GlobPopulationCurrent,
// ------------------------------------------------------------------
// Turn off PRNG kernels
write_channel_altera(chan_Arbiter_BT_ushort_float_off, false);
write_channel_altera(chan_Arbiter_GG_uchar_off, false);
write_channel_altera(chan_Arbiter_GG_float_off, false);
write_channel_intel(chan_Arbiter_BT_ushort_float_off, false);
write_channel_intel(chan_Arbiter_GG_uchar_off, false);
write_channel_intel(chan_Arbiter_GG_float_off, false);
mem_fence(CLK_CHANNEL_MEM_FENCE);
// Turn off IGL_Arbiter, Conform, InterE, IntraE kernerls
write_channel_altera(chan_IGLArbiter_Off, false);
write_channel_intel(chan_IGLArbiter_Off, false);
mem_fence(CLK_CHANNEL_MEM_FENCE);
// Write final pop & energies back to FPGA-board DDRs
......
......@@ -41,15 +41,15 @@ void Krnl_IGL_Arbiter(/*unsigned char DockConst_num_of_genes*/) {
(IC_valid == false) &&
(GG_valid == false)
){
Off_active = read_channel_nb_altera(chan_IGLArbiter_Off, &Off_valid);
IC_active = read_channel_nb_altera(chan_GA2IGL_IC_active, &IC_valid);
GG_active = read_channel_nb_altera(chan_GA2IGL_GG_active, &GG_valid);
Off_active = read_channel_nb_intel(chan_IGLArbiter_Off, &Off_valid);
IC_active = read_channel_nb_intel(chan_GA2IGL_IC_active, &IC_valid);
GG_active = read_channel_nb_intel(chan_GA2IGL_GG_active, &GG_valid);
}
// "active" carries mode info too
active = Off_valid ? 0x00: IC_valid? 'I': 'G';
write_channel_altera(chan_IGL2Conform_actmode, active);
write_channel_intel(chan_IGL2Conform_actmode, active);
// Only for debugging
/*
......
......@@ -68,9 +68,9 @@ while(active) {
// --------------------------------------------------------------
#if 0
char2 actmode = read_channel_altera(chan_Conf2Intere_actmode);
char2 actmode = read_channel_intel(chan_Conf2Intere_actmode);
#endif
char actmode = read_channel_altera(chan_Conf2Intere_actmode);
char actmode = read_channel_intel(chan_Conf2Intere_actmode);
mem_fence(CLK_CHANNEL_MEM_FENCE);
#if 0
......@@ -82,7 +82,7 @@ while(active) {
mode = actmode;
for (uchar pipe_cnt=0; pipe_cnt<DockConst_num_of_atoms; pipe_cnt+=2) {
float8 tmp = read_channel_altera(chan_Conf2Intere_xyz);
float8 tmp = read_channel_intel(chan_Conf2Intere_xyz);
float3 tmp1 = {tmp.s0, tmp.s1, tmp.s2};
float3 tmp2 = {tmp.s4, tmp.s5, tmp.s6};
loc_coords[pipe_cnt] = tmp1;
......@@ -465,18 +465,18 @@ while(active) {
#endif
switch (mode) {
case 'I': write_channel_altera(chan_Intere2StoreIC_intere, final_interE); break;
case 'G': write_channel_altera(chan_Intere2StoreGG_intere, final_interE); break;
case 'I': write_channel_intel(chan_Intere2StoreIC_intere, final_interE); break;
case 'G': write_channel_intel(chan_Intere2StoreGG_intere, final_interE); break;
/*
case 0x01: write_channel_altera(chan_Intere2StoreLS_LS1_intere, final_interE); break;
case 0x02: write_channel_altera(chan_Intere2StoreLS_LS2_intere, final_interE); break;
case 0x03: write_channel_altera(chan_Intere2StoreLS_LS3_intere, final_interE); break;
case 0x04: write_channel_altera(chan_Intere2StoreLS_LS4_intere, final_interE); break;
case 0x05: write_channel_altera(chan_Intere2StoreLS_LS5_intere, final_interE); break;
case 0x06: