ocladock-fpga tagshttps://git.esa.informatik.tu-darmstadt.de/docking/ocladock-fpga/-/tags2020-10-25T13:13:37Zhttps://git.esa.informatik.tu-darmstadt.de/docking/ocladock-fpga/-/tags/LGA-SDX182-ToBePortedLGA-SDX182-ToBePorted<p data-sourcepos="1:1-1:68" dir="auto">This was a version made using SDx2018.2. Contains a full LGA design.</p>2020-10-25T13:13:37ZLeonardo Solishttps://git.esa.informatik.tu-darmstadt.de/docking/ocladock-fpga/-/tags/FSP-2018FSP-2018<p data-sourcepos="1:1-1:37" dir="auto">Final version submitted to FSP-2018:</p>
<p data-sourcepos="3:1-3:120" dir="auto"><em data-sourcepos="3:1-3:119">A Case Study in Using OpenCL on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software</em>.</p>
<p data-sourcepos="5:1-5:44" dir="auto">Described as <strong data-sourcepos="5:14-5:21">DC4b</strong> in the FSP-2018 paper.</p>
<p data-sourcepos="7:1-7:110" dir="auto">Other DC4c and DC4d design configurations are obtained by setting the corresponding variables in the Makefile.</p>2018-07-27T16:33:42ZLeonardo Solissolis@esa.informatik.tu-darmstadt.dehttps://git.esa.informatik.tu-darmstadt.de/docking/ocladock-fpga/-/tags/Fourth-development-phaseFourth-development-phase<p data-sourcepos="1:1-1:44" dir="auto">Described as <strong data-sourcepos="1:14-1:21">DC4a</strong> in the FSP-2018 paper.</p>2018-07-27T16:31:18ZLeonardo Solissolis@esa.informatik.tu-darmstadt.dehttps://git.esa.informatik.tu-darmstadt.de/docking/ocladock-fpga/-/tags/Third-development-phaseThird-development-phase<p data-sourcepos="1:1-1:43" dir="auto">Described as <strong data-sourcepos="1:14-1:20">DC3</strong> in the FSP-2018 paper.</p>2018-07-27T16:31:06ZLeonardo Solissolis@esa.informatik.tu-darmstadt.dehttps://git.esa.informatik.tu-darmstadt.de/docking/ocladock-fpga/-/tags/Second-development-phaseSecond-development-phase<p data-sourcepos="1:1-1:43" dir="auto">Described as <strong data-sourcepos="1:14-1:20">DC2</strong> in the FSP-2018 paper.</p>2018-07-27T16:30:51ZLeonardo Solissolis@esa.informatik.tu-darmstadt.dehttps://git.esa.informatik.tu-darmstadt.de/docking/ocladock-fpga/-/tags/First-development-phaseFirst-development-phase<p data-sourcepos="1:1-1:44" dir="auto">Described as <strong data-sourcepos="1:14-1:20">DC1</strong> in the FSP-2018 paper.</p>2018-07-27T16:30:38ZLeonardo Solissolis@esa.informatik.tu-darmstadt.de