Commit 1d589f8a authored by Leonardo Solis's avatar Leonardo Solis

reduce width channel actmode igl2conf2ie2ia

parent ef949f63
......@@ -80,12 +80,19 @@ while(active) {
)) loc_coords [MAX_NUM_OF_ATOMS];
#endif
#if 0
char2 actmode = read_channel_altera(chan_IGL2Conform_actmode);
#endif
char actmode = read_channel_altera(chan_IGL2Conform_actmode);
mem_fence(CLK_CHANNEL_MEM_FENCE);
#if 0
active = actmode.x;
mode = actmode.y;
#endif
active = actmode;
mode = actmode;
//printf("Conform: %u\n", mode);
#if defined (FIXED_POINT_CONFORM)
......@@ -433,12 +440,16 @@ while(active) {
for (uchar pipe_cnt=0; pipe_cnt<DockConst_num_of_atoms; pipe_cnt+=2) {
if (pipe_cnt == 0) {
#if 0
char active_tmp = active;
char mode_tmp = mode;
char2 actmode = {active_tmp, mode_tmp};
write_channel_altera(chan_Conf2Intere_actmode, actmode);
write_channel_altera(chan_Conf2Intrae_actmode, actmode);
#endif
write_channel_altera(chan_Conf2Intere_actmode, mode);
write_channel_altera(chan_Conf2Intrae_actmode, mode);
}
mem_fence(CLK_CHANNEL_MEM_FENCE);
......
......@@ -30,9 +30,18 @@ channel float chan_LS2Conf_LS9_genotype __attribute__((depth(CHAN_DEPTH_G
// Send ligand-atom positions from Conform to InterE & IntraE
channel float8 chan_Conf2Intere_xyz __attribute__((depth(CHAN_DEPTH_ATOMXYZ)));
#if 0
channel char2 chan_Conf2Intere_actmode;
#endif
channel char chan_Conf2Intere_actmode;
channel float8 chan_Conf2Intrae_xyz __attribute__((depth(CHAN_DEPTH_ATOMXYZ)));
#if 0
channel char2 chan_Conf2Intrae_actmode;
#endif
channel char chan_Conf2Intrae_actmode;
// Send energy values from InterE & IntraE to genotype-senders (IC, GG, LSs)
channel float chan_Intere2StoreIC_intere __attribute__((depth(2)));
......@@ -157,7 +166,11 @@ channel bool chan_GA2LS_Off9_active;
// Send genotype-producer-channel selector and genotype
// from IGL_Arbiter to Conform
#if 0
channel char2 chan_IGL2Conform_actmode __attribute__((depth(9))); // active, mode
#endif
channel char chan_IGL2Conform_actmode __attribute__((depth(9))); // active, mode
channel float chan_IGL2Conform_genotype __attribute__((depth(9*CHAN_DEPTH_GENOTYPE)));
// Turn-off signal to IGL_Arbiter, Conform, InterE, IntraE
......
......@@ -1309,9 +1309,13 @@ while(active) {
// Send "mode" to Conform
for (uchar j=0; j<bound; j++) {
#if 0
char mode_tmp = Off_valid? 0x00: IC_valid? 'I': GG_valid? 'G': mode[j];
char2 actmode = {active, mode_tmp};
write_channel_altera(chan_IGL2Conform_actmode, actmode);
#endif
char mode_tmp = Off_valid? 0x00: IC_valid? 'I': GG_valid? 'G': mode[j];
write_channel_altera(chan_IGL2Conform_actmode, mode_tmp);
#if defined (DEBUG_KRNL_IGL_ARBITER)
printf("bound: %u, mode: %u\n", bound, mode_tmp);
......
......@@ -68,11 +68,19 @@ while(active) {
// Wait for ligand atomic coordinates in channel
// --------------------------------------------------------------
#if 0
char2 actmode = read_channel_altera(chan_Conf2Intere_actmode);
#endif
char actmode = read_channel_altera(chan_Conf2Intere_actmode);
mem_fence(CLK_CHANNEL_MEM_FENCE);
#if 0
active = actmode.x;
mode = actmode.y;
#endif
active = actmode;
mode = actmode;
for (uchar pipe_cnt=0; pipe_cnt<DockConst_num_of_atoms; pipe_cnt+=2) {
float8 tmp = read_channel_altera(chan_Conf2Intere_xyz);
......
......@@ -64,11 +64,18 @@ while(active) {
// Wait for ligand atomic coordinates in channel
// --------------------------------------------------------------
#if 0
char2 actmode = read_channel_altera(chan_Conf2Intrae_actmode);
#endif
char actmode = read_channel_altera(chan_Conf2Intrae_actmode);
mem_fence(CLK_CHANNEL_MEM_FENCE);
#if 0
active = actmode.x;
mode = actmode.y;
#endif
active = actmode;
mode = actmode;
for (uchar pipe_cnt=0; pipe_cnt<DockConst_num_of_atoms; pipe_cnt+=2) {
float8 tmp = read_channel_altera(chan_Conf2Intrae_xyz);
......
  • Results of FPGA fitting process:

    Fitter Status Successful - Fri Jun 8 17:19:49 2018
    Quartus Prime Version 16.0.2 Build 222 07/20/2016 Patches 2.06 SJ Pro Edition
    Revision Name top
    Top-level Entity Name top
    Family Arria 10
    Device 10AX115H3F34I2SG
    Timing Models Final
    Logic utilization (in ALMs) 226,812 / 427,200 ( 53 % )
    Total registers 455014
    Total pins 169 / 618 ( 27 % )
    Total virtual pins 0
    Total block memory bits 24,418,799 / 55,562,240 ( 44 % )
    Total RAM Blocks 1,940 / 2,713 ( 72 % )
    Total DSP Blocks 670 / 1,518 ( 44 % )
    Total HSSI RX channels 8 / 24 ( 33 % )
    Total HSSI TX channels 8 / 24 ( 33 % )
    Total PLLs 30 / 80 ( 38 % )
    DC4b (FPL/FSP) This commit (DC4b + smoothing + simplified chann igl2conf)
    Freq 187.5 MHz 187.5 MHz
    Best E, Best clusterSize, Time (Kcal/mol), (no units), (sec)
    3ptb -5.53, 66/100, 211 -5.54, 72/100, 218
    1stp -7.76, 69/100, 385 -7.56, 64/100, 385
    4hmg -4.11, 25/100, 623 -3.59, 41/100, 571
    3ce3 -10.88, 48/100, 1077 -11.12, 32/100, 1066
    3c1x -12.61, 22/100, 1487 -13.14, 53/100, 1493
    Edited by Leonardo Solis
  • mentioned in commit aec9fbd7

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