added smoothing
Loading
-
Results of FPGA fitting process:
Fitter Status Successful - Fri Jun 1 23:05:34 2018 Quartus Prime Version 16.0.2 Build 222 07/20/2016 Patches 2.06 SJ Pro Edition Revision Name top Top-level Entity Name top Family Arria 10 Device 10AX115H3F34I2SG Timing Models Final Logic utilization (in ALMs) 226,888 / 427,200 ( 53 % ) Total registers 455472 Total pins 169 / 618 ( 27 % ) Total virtual pins 0 Total block memory bits 24,415,503 / 55,562,240 ( 44 % ) Total RAM Blocks 1,939 / 2,713 ( 71 % ) Total DSP Blocks 670 / 1,518 ( 44 % ) Total HSSI RX channels 8 / 24 ( 33 % ) Total HSSI TX channels 8 / 24 ( 33 % ) Total PLLs 30 / 80 ( 38 % ) DC4b (FPL/FSP) This commit (DC4b + smoothing) Freq 187.5 MHz 190 MHz Best E, Best clusterSize, Time (Kcal/mol), (no units), (sec) 3ptb -5.53, 66/100, 211 -5.52, 50/100, 213 1stp -7.76, 69/100, 385 -7.75, 59/100, 377 4hmg -4.11, 25/100, 623 -3.62, 45/100, 566 3ce3 -10.88, 48/100, 1077 -10.93, 36/100, 1063 3c1x -12.61, 22/100, 1487 -13.15, 51/100, 1486 Edited by Leonardo Solis -
mentioned in commit 3e2bd71b
Please register or sign in to comment