mkMSIXIntrCtrl.v 103 KB
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//
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
//
// On Thu Jun  1 17:05:44 CEST 2017
//
//
// Ports:
// Name                         I/O  size props
// S_AXI_arready                  O     1 reg
// S_AXI_rvalid                   O     1 reg
// S_AXI_rdata                    O    32
// S_AXI_rresp                    O     2
// S_AXI_awready                  O     1
// S_AXI_wready                   O     1
// S_AXI_bvalid                   O     1 reg
// S_AXI_bresp                    O     2
// cfg_interrupt_msix_address     O    64 const
// cfg_interrupt_msix_data        O    32 const
// cfg_interrupt_msix_int         O     1 const
// M_AXI_arvalid                  O     1 reg
// M_AXI_araddr                   O    64
// M_AXI_arprot                   O     3
// M_AXI_rready                   O     1 reg
// M_AXI_awvalid                  O     1
// M_AXI_awaddr                   O    64
// M_AXI_awprot                   O     3
// M_AXI_wvalid                   O     1
// M_AXI_wdata                    O    32
// M_AXI_wstrb                    O     4
// M_AXI_bready                   O     1 reg
// S_AXI_ACLK                     I     1 clock
// S_AXI_ARESETN                  I     1 reset
// S_AXI_arvalid                  I     1
// S_AXI_araddr                   I    32 reg
// S_AXI_arprot                   I     3 reg
// S_AXI_rready                   I     1
// S_AXI_awvalid                  I     1
// S_AXI_awaddr                   I    32
// S_AXI_awprot                   I     3
// S_AXI_wvalid                   I     1
// S_AXI_wdata                    I    32
// S_AXI_wstrb                    I     4
// S_AXI_bready                   I     1
// interrupt                      I     8 reg
// cfg_interrupt_msix_sent        I     1 unused
// cfg_interrupt_msix_fail        I     1 unused
// cfg_interrupt_msix_enable      I     4
// cfg_interrupt_msix_mask        I     4
// M_AXI_arready                  I     1
// M_AXI_rvalid                   I     1
// M_AXI_rdata                    I    32 reg
// M_AXI_rresp                    I     2 reg
// M_AXI_awready                  I     1
// M_AXI_wready                   I     1
// M_AXI_bvalid                   I     1
// M_AXI_bresp                    I     2 reg
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkMSIXIntrCtrl(S_AXI_ACLK,
		      S_AXI_ARESETN,

		      S_AXI_arready,

		      S_AXI_arvalid,

		      S_AXI_araddr,

		      S_AXI_arprot,

		      S_AXI_rvalid,

		      S_AXI_rready,

		      S_AXI_rdata,

		      S_AXI_rresp,

		      S_AXI_awready,

		      S_AXI_awvalid,

		      S_AXI_awaddr,

		      S_AXI_awprot,

		      S_AXI_wready,

		      S_AXI_wvalid,

		      S_AXI_wdata,

		      S_AXI_wstrb,

		      S_AXI_bvalid,

		      S_AXI_bready,

		      S_AXI_bresp,

		      interrupt,

		      cfg_interrupt_msix_address,

		      cfg_interrupt_msix_data,

		      cfg_interrupt_msix_int,

		      cfg_interrupt_msix_sent,

		      cfg_interrupt_msix_fail,

		      cfg_interrupt_msix_enable,

		      cfg_interrupt_msix_mask,

		      M_AXI_arvalid,

		      M_AXI_arready,

		      M_AXI_araddr,

		      M_AXI_arprot,

		      M_AXI_rready,

		      M_AXI_rvalid,

		      M_AXI_rdata,

		      M_AXI_rresp,

		      M_AXI_awready,

		      M_AXI_awvalid,

		      M_AXI_awaddr,

		      M_AXI_awprot,

		      M_AXI_wready,

		      M_AXI_wvalid,

		      M_AXI_wdata,

		      M_AXI_wstrb,

		      M_AXI_bvalid,

		      M_AXI_bready,

		      M_AXI_bresp);
  input  S_AXI_ACLK;
  input  S_AXI_ARESETN;

  // value method s_rd_arready
  output S_AXI_arready;

  // action method s_rd_parvalid
  input  S_AXI_arvalid;

  // action method s_rd_paraddr
  input  [31 : 0] S_AXI_araddr;

  // action method s_rd_parprot
  input  [2 : 0] S_AXI_arprot;

  // value method s_rd_rvalid
  output S_AXI_rvalid;

  // action method s_rd_prready
  input  S_AXI_rready;

  // value method s_rd_rdata
  output [31 : 0] S_AXI_rdata;

  // value method s_rd_rresp
  output [1 : 0] S_AXI_rresp;

  // value method s_wr_awready
  output S_AXI_awready;

  // action method s_wr_pawvalid
  input  S_AXI_awvalid;

  // action method s_wr_pawaddr
  input  [31 : 0] S_AXI_awaddr;

  // action method s_wr_pawprot
  input  [2 : 0] S_AXI_awprot;

  // value method s_wr_wready
  output S_AXI_wready;

  // action method s_wr_pwvalid
  input  S_AXI_wvalid;

  // action method s_wr_pwdata
  input  [31 : 0] S_AXI_wdata;

  // action method s_wr_pwstrb
  input  [3 : 0] S_AXI_wstrb;

  // value method s_wr_bvalid
  output S_AXI_bvalid;

  // action method s_wr_pbready
  input  S_AXI_bready;

  // value method s_wr_bresp
  output [1 : 0] S_AXI_bresp;

  // action method _interrupts
  input  [7 : 0] interrupt;

  // value method intr_address
  output [63 : 0] cfg_interrupt_msix_address;

  // value method intr_data
  output [31 : 0] cfg_interrupt_msix_data;

  // value method intr_interrupt
  output cfg_interrupt_msix_int;

  // action method intr__sent
  input  cfg_interrupt_msix_sent;

  // action method intr__fail
  input  cfg_interrupt_msix_fail;

  // action method intr__enable
  input  [3 : 0] cfg_interrupt_msix_enable;

  // action method intr__mask
  input  [3 : 0] cfg_interrupt_msix_mask;

  // value method m_rd_arvalid
  output M_AXI_arvalid;

  // action method m_rd_parready
  input  M_AXI_arready;

  // value method m_rd_araddr
  output [63 : 0] M_AXI_araddr;

  // value method m_rd_arprot
  output [2 : 0] M_AXI_arprot;

  // value method m_rd_rready
  output M_AXI_rready;

  // action method m_rd_prvalid
  input  M_AXI_rvalid;

  // action method m_rd_prdata
  input  [31 : 0] M_AXI_rdata;

  // action method m_rd_prresp
  input  [1 : 0] M_AXI_rresp;

  // action method m_wr_pawready
  input  M_AXI_awready;

  // value method m_wr_awvalid
  output M_AXI_awvalid;

  // value method m_wr_awaddr
  output [63 : 0] M_AXI_awaddr;

  // value method m_wr_awprot
  output [2 : 0] M_AXI_awprot;

  // action method m_wr_pwready
  input  M_AXI_wready;

  // value method m_wr_wvalid
  output M_AXI_wvalid;

  // value method m_wr_wdata
  output [31 : 0] M_AXI_wdata;

  // value method m_wr_wstrb
  output [3 : 0] M_AXI_wstrb;

  // action method m_wr_pbvalid
  input  M_AXI_bvalid;

  // value method m_wr_bready
  output M_AXI_bready;

  // action method m_wr_pbresp
  input  [1 : 0] M_AXI_bresp;

  // signals for module outputs
  wire [63 : 0] M_AXI_araddr, M_AXI_awaddr, cfg_interrupt_msix_address;
  wire [31 : 0] M_AXI_wdata, S_AXI_rdata, cfg_interrupt_msix_data;
  wire [3 : 0] M_AXI_wstrb;
  wire [2 : 0] M_AXI_arprot, M_AXI_awprot;
  wire [1 : 0] S_AXI_bresp, S_AXI_rresp;
  wire M_AXI_arvalid,
       M_AXI_awvalid,
       M_AXI_bready,
       M_AXI_rready,
       M_AXI_wvalid,
       S_AXI_arready,
       S_AXI_awready,
       S_AXI_bvalid,
       S_AXI_rvalid,
       S_AXI_wready,
       cfg_interrupt_msix_int;

  // inlined wires
  wire [67 : 0] writeMaster_addrOut_rv$port0__write_1,
		writeMaster_addrOut_rv$port1__read,
		writeMaster_addrOut_rv$port2__read;
  wire [36 : 0] s_config_writeSlave_dataIn_rv$port0__write_1,
		s_config_writeSlave_dataIn_rv$port1__read,
		s_config_writeSlave_dataIn_rv$port2__read,
		writeMaster_dataOut_rv$port0__write_1,
		writeMaster_dataOut_rv$port1__read,
		writeMaster_dataOut_rv$port2__read;
  wire [35 : 0] s_config_writeSlave_addrIn_rv$port0__write_1,
		s_config_writeSlave_addrIn_rv$port1__read,
		s_config_writeSlave_addrIn_rv$port2__read;
  wire msix_tab_pba_0_pba$EN_port0__write,
       msix_tab_pba_0_pba$EN_port1__write,
       msix_tab_pba_0_pba$port1__read,
       msix_tab_pba_0_pba$port2__read,
       msix_tab_pba_1_pba$EN_port0__write,
       msix_tab_pba_1_pba$EN_port1__write,
       msix_tab_pba_1_pba$port1__read,
       msix_tab_pba_1_pba$port2__read,
       msix_tab_pba_2_pba$EN_port0__write,
       msix_tab_pba_2_pba$EN_port1__write,
       msix_tab_pba_2_pba$port1__read,
       msix_tab_pba_2_pba$port2__read,
       msix_tab_pba_3_pba$EN_port0__write,
       msix_tab_pba_3_pba$EN_port1__write,
       msix_tab_pba_3_pba$port1__read,
       msix_tab_pba_3_pba$port2__read,
       msix_tab_pba_4_pba$EN_port0__write,
       msix_tab_pba_4_pba$EN_port1__write,
       msix_tab_pba_4_pba$port1__read,
       msix_tab_pba_4_pba$port2__read,
       msix_tab_pba_5_pba$EN_port0__write,
       msix_tab_pba_5_pba$EN_port1__write,
       msix_tab_pba_5_pba$port1__read,
       msix_tab_pba_5_pba$port2__read,
       msix_tab_pba_6_pba$EN_port0__write,
       msix_tab_pba_6_pba$EN_port1__write,
       msix_tab_pba_6_pba$port1__read,
       msix_tab_pba_6_pba$port2__read,
       msix_tab_pba_7_pba$EN_port0__write,
       msix_tab_pba_7_pba$EN_port1__write,
       msix_tab_pba_7_pba$port1__read,
       msix_tab_pba_7_pba$port2__read,
       s_config_writeSlave_addrIn_rv$EN_port0__write,
       s_config_writeSlave_addrIn_rv$EN_port1__write,
       s_config_writeSlave_dataIn_rv$EN_port0__write,
       s_config_writeSlave_dataIn_rv$EN_port1__write,
       send_pending$EN_port0__write,
       send_pending$port1__read,
       send_pending$port2__read,
       writeMaster_addrOut_rv$EN_port0__write,
       writeMaster_addrOut_rv$EN_port1__write,
       writeMaster_dataOut_rv$EN_port0__write,
       writeMaster_dataOut_rv$EN_port1__write;

  // register active
  reg active;
  wire active$D_IN, active$EN;

  // register completionCntr
  reg [15 : 0] completionCntr;
  wire [15 : 0] completionCntr$D_IN;
  wire completionCntr$EN;

  // register completionDelay
  reg [15 : 0] completionDelay;
  wire [15 : 0] completionDelay$D_IN;
  wire completionDelay$EN;

  // register completionReg
  reg [31 : 0] completionReg;
  wire [31 : 0] completionReg$D_IN;
  wire completionReg$EN;

  // register enableAndMask
  reg [31 : 0] enableAndMask;
  wire [31 : 0] enableAndMask$D_IN;
  wire enableAndMask$EN;

  // register id
  reg [31 : 0] id;
  wire [31 : 0] id$D_IN;
  wire id$EN;

  // register interrupt_last_0
  reg interrupt_last_0;
  wire interrupt_last_0$D_IN, interrupt_last_0$EN;

  // register interrupt_last_1
  reg interrupt_last_1;
  wire interrupt_last_1$D_IN, interrupt_last_1$EN;

  // register interrupt_last_2
  reg interrupt_last_2;
  wire interrupt_last_2$D_IN, interrupt_last_2$EN;

  // register interrupt_last_3
  reg interrupt_last_3;
  wire interrupt_last_3$D_IN, interrupt_last_3$EN;

  // register interrupt_last_4
  reg interrupt_last_4;
  wire interrupt_last_4$D_IN, interrupt_last_4$EN;

  // register interrupt_last_5
  reg interrupt_last_5;
  wire interrupt_last_5$D_IN, interrupt_last_5$EN;

  // register interrupt_last_6
  reg interrupt_last_6;
  wire interrupt_last_6$D_IN, interrupt_last_6$EN;

  // register interrupt_last_7
  reg interrupt_last_7;
  wire interrupt_last_7$D_IN, interrupt_last_7$EN;

  // register interrupts_0
  reg interrupts_0;
  wire interrupts_0$D_IN, interrupts_0$EN;

  // register interrupts_1
  reg interrupts_1;
  wire interrupts_1$D_IN, interrupts_1$EN;

  // register interrupts_2
  reg interrupts_2;
  wire interrupts_2$D_IN, interrupts_2$EN;

  // register interrupts_3
  reg interrupts_3;
  wire interrupts_3$D_IN, interrupts_3$EN;

  // register interrupts_4
  reg interrupts_4;
  wire interrupts_4$D_IN, interrupts_4$EN;

  // register interrupts_5
  reg interrupts_5;
  wire interrupts_5$D_IN, interrupts_5$EN;

  // register interrupts_6
  reg interrupts_6;
  wire interrupts_6$D_IN, interrupts_6$EN;

  // register interrupts_7
  reg interrupts_7;
  wire interrupts_7$D_IN, interrupts_7$EN;

  // register msix_tab_pba_0_msg_addr_lower
  reg [31 : 0] msix_tab_pba_0_msg_addr_lower;
  wire [31 : 0] msix_tab_pba_0_msg_addr_lower$D_IN;
  wire msix_tab_pba_0_msg_addr_lower$EN;

  // register msix_tab_pba_0_msg_addr_upper
  reg [31 : 0] msix_tab_pba_0_msg_addr_upper;
  wire [31 : 0] msix_tab_pba_0_msg_addr_upper$D_IN;
  wire msix_tab_pba_0_msg_addr_upper$EN;

  // register msix_tab_pba_0_msg_data
  reg [31 : 0] msix_tab_pba_0_msg_data;
  wire [31 : 0] msix_tab_pba_0_msg_data$D_IN;
  wire msix_tab_pba_0_msg_data$EN;

  // register msix_tab_pba_0_pba
  reg msix_tab_pba_0_pba;
  wire msix_tab_pba_0_pba$D_IN, msix_tab_pba_0_pba$EN;

  // register msix_tab_pba_0_vector_control
  reg [31 : 0] msix_tab_pba_0_vector_control;
  wire [31 : 0] msix_tab_pba_0_vector_control$D_IN;
  wire msix_tab_pba_0_vector_control$EN;

  // register msix_tab_pba_1_msg_addr_lower
  reg [31 : 0] msix_tab_pba_1_msg_addr_lower;
  wire [31 : 0] msix_tab_pba_1_msg_addr_lower$D_IN;
  wire msix_tab_pba_1_msg_addr_lower$EN;

  // register msix_tab_pba_1_msg_addr_upper
  reg [31 : 0] msix_tab_pba_1_msg_addr_upper;
  wire [31 : 0] msix_tab_pba_1_msg_addr_upper$D_IN;
  wire msix_tab_pba_1_msg_addr_upper$EN;

  // register msix_tab_pba_1_msg_data
  reg [31 : 0] msix_tab_pba_1_msg_data;
  wire [31 : 0] msix_tab_pba_1_msg_data$D_IN;
  wire msix_tab_pba_1_msg_data$EN;

  // register msix_tab_pba_1_pba
  reg msix_tab_pba_1_pba;
  wire msix_tab_pba_1_pba$D_IN, msix_tab_pba_1_pba$EN;

  // register msix_tab_pba_1_vector_control
  reg [31 : 0] msix_tab_pba_1_vector_control;
  wire [31 : 0] msix_tab_pba_1_vector_control$D_IN;
  wire msix_tab_pba_1_vector_control$EN;

  // register msix_tab_pba_2_msg_addr_lower
  reg [31 : 0] msix_tab_pba_2_msg_addr_lower;
  wire [31 : 0] msix_tab_pba_2_msg_addr_lower$D_IN;
  wire msix_tab_pba_2_msg_addr_lower$EN;

  // register msix_tab_pba_2_msg_addr_upper
  reg [31 : 0] msix_tab_pba_2_msg_addr_upper;
  wire [31 : 0] msix_tab_pba_2_msg_addr_upper$D_IN;
  wire msix_tab_pba_2_msg_addr_upper$EN;

  // register msix_tab_pba_2_msg_data
  reg [31 : 0] msix_tab_pba_2_msg_data;
  wire [31 : 0] msix_tab_pba_2_msg_data$D_IN;
  wire msix_tab_pba_2_msg_data$EN;

  // register msix_tab_pba_2_pba
  reg msix_tab_pba_2_pba;
  wire msix_tab_pba_2_pba$D_IN, msix_tab_pba_2_pba$EN;

  // register msix_tab_pba_2_vector_control
  reg [31 : 0] msix_tab_pba_2_vector_control;
  wire [31 : 0] msix_tab_pba_2_vector_control$D_IN;
  wire msix_tab_pba_2_vector_control$EN;

  // register msix_tab_pba_3_msg_addr_lower
  reg [31 : 0] msix_tab_pba_3_msg_addr_lower;
  wire [31 : 0] msix_tab_pba_3_msg_addr_lower$D_IN;
  wire msix_tab_pba_3_msg_addr_lower$EN;

  // register msix_tab_pba_3_msg_addr_upper
  reg [31 : 0] msix_tab_pba_3_msg_addr_upper;
  wire [31 : 0] msix_tab_pba_3_msg_addr_upper$D_IN;
  wire msix_tab_pba_3_msg_addr_upper$EN;

  // register msix_tab_pba_3_msg_data
  reg [31 : 0] msix_tab_pba_3_msg_data;
  wire [31 : 0] msix_tab_pba_3_msg_data$D_IN;
  wire msix_tab_pba_3_msg_data$EN;

  // register msix_tab_pba_3_pba
  reg msix_tab_pba_3_pba;
  wire msix_tab_pba_3_pba$D_IN, msix_tab_pba_3_pba$EN;

  // register msix_tab_pba_3_vector_control
  reg [31 : 0] msix_tab_pba_3_vector_control;
  wire [31 : 0] msix_tab_pba_3_vector_control$D_IN;
  wire msix_tab_pba_3_vector_control$EN;

  // register msix_tab_pba_4_msg_addr_lower
  reg [31 : 0] msix_tab_pba_4_msg_addr_lower;
  wire [31 : 0] msix_tab_pba_4_msg_addr_lower$D_IN;
  wire msix_tab_pba_4_msg_addr_lower$EN;

  // register msix_tab_pba_4_msg_addr_upper
  reg [31 : 0] msix_tab_pba_4_msg_addr_upper;
  wire [31 : 0] msix_tab_pba_4_msg_addr_upper$D_IN;
  wire msix_tab_pba_4_msg_addr_upper$EN;

  // register msix_tab_pba_4_msg_data
  reg [31 : 0] msix_tab_pba_4_msg_data;
  wire [31 : 0] msix_tab_pba_4_msg_data$D_IN;
  wire msix_tab_pba_4_msg_data$EN;

  // register msix_tab_pba_4_pba
  reg msix_tab_pba_4_pba;
  wire msix_tab_pba_4_pba$D_IN, msix_tab_pba_4_pba$EN;

  // register msix_tab_pba_4_vector_control
  reg [31 : 0] msix_tab_pba_4_vector_control;
  wire [31 : 0] msix_tab_pba_4_vector_control$D_IN;
  wire msix_tab_pba_4_vector_control$EN;

  // register msix_tab_pba_5_msg_addr_lower
  reg [31 : 0] msix_tab_pba_5_msg_addr_lower;
  wire [31 : 0] msix_tab_pba_5_msg_addr_lower$D_IN;
  wire msix_tab_pba_5_msg_addr_lower$EN;

  // register msix_tab_pba_5_msg_addr_upper
  reg [31 : 0] msix_tab_pba_5_msg_addr_upper;
  wire [31 : 0] msix_tab_pba_5_msg_addr_upper$D_IN;
  wire msix_tab_pba_5_msg_addr_upper$EN;

  // register msix_tab_pba_5_msg_data
  reg [31 : 0] msix_tab_pba_5_msg_data;
  wire [31 : 0] msix_tab_pba_5_msg_data$D_IN;
  wire msix_tab_pba_5_msg_data$EN;

  // register msix_tab_pba_5_pba
  reg msix_tab_pba_5_pba;
  wire msix_tab_pba_5_pba$D_IN, msix_tab_pba_5_pba$EN;

  // register msix_tab_pba_5_vector_control
  reg [31 : 0] msix_tab_pba_5_vector_control;
  wire [31 : 0] msix_tab_pba_5_vector_control$D_IN;
  wire msix_tab_pba_5_vector_control$EN;

  // register msix_tab_pba_6_msg_addr_lower
  reg [31 : 0] msix_tab_pba_6_msg_addr_lower;
  wire [31 : 0] msix_tab_pba_6_msg_addr_lower$D_IN;
  wire msix_tab_pba_6_msg_addr_lower$EN;

  // register msix_tab_pba_6_msg_addr_upper
  reg [31 : 0] msix_tab_pba_6_msg_addr_upper;
  wire [31 : 0] msix_tab_pba_6_msg_addr_upper$D_IN;
  wire msix_tab_pba_6_msg_addr_upper$EN;

  // register msix_tab_pba_6_msg_data
  reg [31 : 0] msix_tab_pba_6_msg_data;
  wire [31 : 0] msix_tab_pba_6_msg_data$D_IN;
  wire msix_tab_pba_6_msg_data$EN;

  // register msix_tab_pba_6_pba
  reg msix_tab_pba_6_pba;
  wire msix_tab_pba_6_pba$D_IN, msix_tab_pba_6_pba$EN;

  // register msix_tab_pba_6_vector_control
  reg [31 : 0] msix_tab_pba_6_vector_control;
  wire [31 : 0] msix_tab_pba_6_vector_control$D_IN;
  wire msix_tab_pba_6_vector_control$EN;

  // register msix_tab_pba_7_msg_addr_lower
  reg [31 : 0] msix_tab_pba_7_msg_addr_lower;
  wire [31 : 0] msix_tab_pba_7_msg_addr_lower$D_IN;
  wire msix_tab_pba_7_msg_addr_lower$EN;

  // register msix_tab_pba_7_msg_addr_upper
  reg [31 : 0] msix_tab_pba_7_msg_addr_upper;
  wire [31 : 0] msix_tab_pba_7_msg_addr_upper$D_IN;
  wire msix_tab_pba_7_msg_addr_upper$EN;

  // register msix_tab_pba_7_msg_data
  reg [31 : 0] msix_tab_pba_7_msg_data;
  wire [31 : 0] msix_tab_pba_7_msg_data$D_IN;
  wire msix_tab_pba_7_msg_data$EN;

  // register msix_tab_pba_7_pba
  reg msix_tab_pba_7_pba;
  wire msix_tab_pba_7_pba$D_IN, msix_tab_pba_7_pba$EN;

  // register msix_tab_pba_7_vector_control
  reg [31 : 0] msix_tab_pba_7_vector_control;
  wire [31 : 0] msix_tab_pba_7_vector_control$D_IN;
  wire msix_tab_pba_7_vector_control$EN;

  // register num_sent
  reg [2 : 0] num_sent;
  wire [2 : 0] num_sent$D_IN;
  wire num_sent$EN;

  // register s_config_readBusy
  reg s_config_readBusy;
  wire s_config_readBusy$D_IN, s_config_readBusy$EN;

  // register s_config_writeSlave_addrIn_rv
  reg [35 : 0] s_config_writeSlave_addrIn_rv;
  wire [35 : 0] s_config_writeSlave_addrIn_rv$D_IN;
  wire s_config_writeSlave_addrIn_rv$EN;

  // register s_config_writeSlave_dataIn_rv
  reg [36 : 0] s_config_writeSlave_dataIn_rv;
  wire [36 : 0] s_config_writeSlave_dataIn_rv$D_IN;
  wire s_config_writeSlave_dataIn_rv$EN;

  // register send_pending
  reg send_pending;
  wire send_pending$D_IN, send_pending$EN;

  // register sentReg
  reg [31 : 0] sentReg;
  wire [31 : 0] sentReg$D_IN;
  wire sentReg$EN;

  // register writeMaster_addrOut_rv
  reg [67 : 0] writeMaster_addrOut_rv;
  wire [67 : 0] writeMaster_addrOut_rv$D_IN;
  wire writeMaster_addrOut_rv$EN;

  // register writeMaster_dataOut_rv
  reg [36 : 0] writeMaster_dataOut_rv;
  wire [36 : 0] writeMaster_dataOut_rv$D_IN;
  wire writeMaster_dataOut_rv$EN;

  // ports of submodule readMaster_in
  wire [66 : 0] readMaster_in$D_IN, readMaster_in$D_OUT;
  wire readMaster_in$CLR,
       readMaster_in$DEQ,
       readMaster_in$EMPTY_N,
       readMaster_in$ENQ;

  // ports of submodule readMaster_out
  wire [33 : 0] readMaster_out$D_IN;
  wire readMaster_out$CLR,
       readMaster_out$DEQ,
       readMaster_out$ENQ,
       readMaster_out$FULL_N;

  // ports of submodule s_config_readSlave_in
  wire [34 : 0] s_config_readSlave_in$D_IN, s_config_readSlave_in$D_OUT;
  wire s_config_readSlave_in$CLR,
       s_config_readSlave_in$DEQ,
       s_config_readSlave_in$EMPTY_N,
       s_config_readSlave_in$ENQ,
       s_config_readSlave_in$FULL_N;

  // ports of submodule s_config_readSlave_out
  reg [33 : 0] s_config_readSlave_out$D_IN;
  wire [33 : 0] s_config_readSlave_out$D_OUT;
  wire s_config_readSlave_out$CLR,
       s_config_readSlave_out$DEQ,
       s_config_readSlave_out$EMPTY_N,
       s_config_readSlave_out$ENQ,
       s_config_readSlave_out$FULL_N;

  // ports of submodule s_config_writeSlave_in
  wire [70 : 0] s_config_writeSlave_in$D_IN, s_config_writeSlave_in$D_OUT;
  wire s_config_writeSlave_in$CLR,
       s_config_writeSlave_in$DEQ,
       s_config_writeSlave_in$EMPTY_N,
       s_config_writeSlave_in$ENQ,
       s_config_writeSlave_in$FULL_N;

  // ports of submodule s_config_writeSlave_out
  wire [1 : 0] s_config_writeSlave_out$D_IN, s_config_writeSlave_out$D_OUT;
  wire s_config_writeSlave_out$CLR,
       s_config_writeSlave_out$DEQ,
       s_config_writeSlave_out$EMPTY_N,
       s_config_writeSlave_out$ENQ,
       s_config_writeSlave_out$FULL_N;

  // ports of submodule writeMaster_in
  wire [102 : 0] writeMaster_in$D_IN, writeMaster_in$D_OUT;
  wire writeMaster_in$CLR,
       writeMaster_in$DEQ,
       writeMaster_in$EMPTY_N,
       writeMaster_in$ENQ,
       writeMaster_in$FULL_N;

  // ports of submodule writeMaster_out
  wire [1 : 0] writeMaster_out$D_IN, writeMaster_out$D_OUT;
  wire writeMaster_out$CLR,
       writeMaster_out$DEQ,
       writeMaster_out$EMPTY_N,
       writeMaster_out$ENQ,
       writeMaster_out$FULL_N;

  // rule scheduling signals
  wire WILL_FIRE_RL_s_config_1_axiWriteFallback,
       WILL_FIRE_RL_s_config_1_axiWriteSpecialRange,
       WILL_FIRE_RL_s_config_axiReadFallback,
       WILL_FIRE_RL_s_config_axiReadSpecial,
       WILL_FIRE_RL_s_config_axiReadSpecialRange,
       WILL_FIRE_RL_s_config_axiReadSpecialRange_1,
       WILL_FIRE_RL_s_config_axiReadSpecial_1,
       WILL_FIRE_RL_s_config_axiReadSpecial_2,
       WILL_FIRE_RL_s_config_axiReadSpecial_3,
       WILL_FIRE_RL_selectInterrupt,
       WILL_FIRE_RL_waitForCompletion;

  // inputs to muxes for submodule ports
  wire [33 : 0] MUX_s_config_readSlave_out$enq_1__VAL_1,
		MUX_s_config_readSlave_out$enq_1__VAL_2,
		MUX_s_config_readSlave_out$enq_1__VAL_3,
		MUX_s_config_readSlave_out$enq_1__VAL_4,
		MUX_s_config_readSlave_out$enq_1__VAL_5,
		MUX_s_config_readSlave_out$enq_1__VAL_6;
  wire MUX_active$write_1__SEL_1;

  // remaining internal signals
  reg [31 : 0] SEL_ARR_msix_tab_pba_0_msg_addr_lower_5_msix_t_ETC___d356,
	       SEL_ARR_msix_tab_pba_0_msg_addr_upper_7_msix_t_ETC___d355,
	       r__h7838,
	       r__h8875,
	       r__h9018,
	       r__h9049,
	       v__h7794,
	       x_data__h20534;
  wire [63 : 0] x_addr__h20533;
  wire [31 : 0] addr__h9162, i__h14144, i__h9105, v__h9156;
  wire [2 : 0] IF_msix_tab_pba_0_vector_control_9_BIT_0_30_OR_ETC___d292,
	       IF_msix_tab_pba_4_vector_control_03_BIT_0_49_O_ETC___d289;
  wire NOT_msix_tab_pba_0_vector_control_9_BIT_0_30_3_ETC___d248,
       NOT_msix_tab_pba_4_vector_control_03_BIT_0_49__ETC___d267,
       _0_CONCAT_s_config_readSlave_in_first__5_BITS_1_ETC___d114,
       _0_CONCAT_s_config_readSlave_in_first__5_BITS_1_ETC___d116,
       _0_CONCAT_s_config_readSlave_in_first__5_BITS_1_ETC___d58,
       enable_wget__16_BIT_0_23_AND_NOT_mask_wget__17_ETC___d351,
       msix_tab_pba_0_vector_control_9_BIT_0_30_OR_NO_ETC___d279;

  // value method s_rd_arready
  assign S_AXI_arready = s_config_readSlave_in$FULL_N ;

  // value method s_rd_rvalid
  assign S_AXI_rvalid = s_config_readSlave_out$EMPTY_N ;

  // value method s_rd_rdata
  assign S_AXI_rdata =
	     s_config_readSlave_out$EMPTY_N ?
	       s_config_readSlave_out$D_OUT[33:2] :
	       32'd0 ;

  // value method s_rd_rresp
  assign S_AXI_rresp =
	     s_config_readSlave_out$EMPTY_N ?
	       s_config_readSlave_out$D_OUT[1:0] :
	       2'd0 ;

  // value method s_wr_awready
  assign S_AXI_awready = !s_config_writeSlave_addrIn_rv[35] ;

  // value method s_wr_wready
  assign S_AXI_wready = !s_config_writeSlave_dataIn_rv[36] ;

  // value method s_wr_bvalid
  assign S_AXI_bvalid = s_config_writeSlave_out$EMPTY_N ;

  // value method s_wr_bresp
  assign S_AXI_bresp =
	     s_config_writeSlave_out$EMPTY_N ?
	       s_config_writeSlave_out$D_OUT :
	       2'd0 ;

  // value method intr_address
  assign cfg_interrupt_msix_address = 64'd0 ;

  // value method intr_data
  assign cfg_interrupt_msix_data = 32'd0 ;

  // value method intr_interrupt
  assign cfg_interrupt_msix_int = 1'b0 ;

  // value method m_rd_arvalid
  assign M_AXI_arvalid = readMaster_in$EMPTY_N ;

  // value method m_rd_araddr
  assign M_AXI_araddr =
	     readMaster_in$EMPTY_N ? readMaster_in$D_OUT[66:3] : 64'd0 ;

  // value method m_rd_arprot
  assign M_AXI_arprot =
	     readMaster_in$EMPTY_N ? readMaster_in$D_OUT[2:0] : 3'd0 ;

  // value method m_rd_rready
  assign M_AXI_rready = readMaster_out$FULL_N ;

  // value method m_wr_awvalid
  assign M_AXI_awvalid = writeMaster_addrOut_rv$port1__read[67] ;

  // value method m_wr_awaddr
  assign M_AXI_awaddr =
	     writeMaster_addrOut_rv$port1__read[67] ?
	       writeMaster_addrOut_rv$port1__read[66:3] :
	       64'd0 ;

  // value method m_wr_awprot
  assign M_AXI_awprot =
	     writeMaster_addrOut_rv$port1__read[67] ?
	       writeMaster_addrOut_rv$port1__read[2:0] :
	       3'd0 ;

  // value method m_wr_wvalid
  assign M_AXI_wvalid = writeMaster_dataOut_rv$port1__read[36] ;

  // value method m_wr_wdata
  assign M_AXI_wdata =
	     writeMaster_dataOut_rv$port1__read[36] ?
	       writeMaster_dataOut_rv$port1__read[35:4] :
	       32'd0 ;

  // value method m_wr_wstrb
  assign M_AXI_wstrb =
	     writeMaster_dataOut_rv$port1__read[36] ?
	       writeMaster_dataOut_rv$port1__read[3:0] :
	       4'd0 ;

  // value method m_wr_bready
  assign M_AXI_bready = writeMaster_out$FULL_N ;

  // submodule readMaster_in
  FIFO1 #(.width(32'd67), .guarded(32'd1)) readMaster_in(.RST(S_AXI_ARESETN),
							 .CLK(S_AXI_ACLK),
							 .D_IN(readMaster_in$D_IN),
							 .ENQ(readMaster_in$ENQ),
							 .DEQ(readMaster_in$DEQ),
							 .CLR(readMaster_in$CLR),
							 .D_OUT(readMaster_in$D_OUT),
							 .FULL_N(),
							 .EMPTY_N(readMaster_in$EMPTY_N));

  // submodule readMaster_out
  FIFO1 #(.width(32'd34), .guarded(32'd1)) readMaster_out(.RST(S_AXI_ARESETN),
							  .CLK(S_AXI_ACLK),
							  .D_IN(readMaster_out$D_IN),
							  .ENQ(readMaster_out$ENQ),
							  .DEQ(readMaster_out$DEQ),
							  .CLR(readMaster_out$CLR),
							  .D_OUT(),
							  .FULL_N(readMaster_out$FULL_N),
							  .EMPTY_N());

  // submodule s_config_readSlave_in
  FIFO2 #(.width(32'd35),
	  .guarded(32'd1)) s_config_readSlave_in(.RST(S_AXI_ARESETN),
						 .CLK(S_AXI_ACLK),
						 .D_IN(s_config_readSlave_in$D_IN),
						 .ENQ(s_config_readSlave_in$ENQ),
						 .DEQ(s_config_readSlave_in$DEQ),
						 .CLR(s_config_readSlave_in$CLR),
						 .D_OUT(s_config_readSlave_in$D_OUT),
						 .FULL_N(s_config_readSlave_in$FULL_N),
						 .EMPTY_N(s_config_readSlave_in$EMPTY_N));

  // submodule s_config_readSlave_out
  FIFO2 #(.width(32'd34),
	  .guarded(32'd1)) s_config_readSlave_out(.RST(S_AXI_ARESETN),
						  .CLK(S_AXI_ACLK),
						  .D_IN(s_config_readSlave_out$D_IN),
						  .ENQ(s_config_readSlave_out$ENQ),
						  .DEQ(s_config_readSlave_out$DEQ),
						  .CLR(s_config_readSlave_out$CLR),
						  .D_OUT(s_config_readSlave_out$D_OUT),
						  .FULL_N(s_config_readSlave_out$FULL_N),
						  .EMPTY_N(s_config_readSlave_out$EMPTY_N));

  // submodule s_config_writeSlave_in
  FIFO2 #(.width(32'd71),
	  .guarded(32'd1)) s_config_writeSlave_in(.RST(S_AXI_ARESETN),
						  .CLK(S_AXI_ACLK),
						  .D_IN(s_config_writeSlave_in$D_IN),
						  .ENQ(s_config_writeSlave_in$ENQ),
						  .DEQ(s_config_writeSlave_in$DEQ),
						  .CLR(s_config_writeSlave_in$CLR),
						  .D_OUT(s_config_writeSlave_in$D_OUT),
						  .FULL_N(s_config_writeSlave_in$FULL_N),
						  .EMPTY_N(s_config_writeSlave_in$EMPTY_N));

  // submodule s_config_writeSlave_out
  FIFO2 #(.width(32'd2),
	  .guarded(32'd1)) s_config_writeSlave_out(.RST(S_AXI_ARESETN),
						   .CLK(S_AXI_ACLK),
						   .D_IN(s_config_writeSlave_out$D_IN),
						   .ENQ(s_config_writeSlave_out$ENQ),
						   .DEQ(s_config_writeSlave_out$DEQ),
						   .CLR(s_config_writeSlave_out$CLR),
						   .D_OUT(s_config_writeSlave_out$D_OUT),
						   .FULL_N(s_config_writeSlave_out$FULL_N),
						   .EMPTY_N(s_config_writeSlave_out$EMPTY_N));

  // submodule writeMaster_in
  FIFO1 #(.width(32'd103),
	  .guarded(32'd1)) writeMaster_in(.RST(S_AXI_ARESETN),
					  .CLK(S_AXI_ACLK),
					  .D_IN(writeMaster_in$D_IN),
					  .ENQ(writeMaster_in$ENQ),
					  .DEQ(writeMaster_in$DEQ),
					  .CLR(writeMaster_in$CLR),
					  .D_OUT(writeMaster_in$D_OUT),
					  .FULL_N(writeMaster_in$FULL_N),
					  .EMPTY_N(writeMaster_in$EMPTY_N));

  // submodule writeMaster_out
  FIFO1 #(.width(32'd2), .guarded(32'd1)) writeMaster_out(.RST(S_AXI_ARESETN),
							  .CLK(S_AXI_ACLK),
							  .D_IN(writeMaster_out$D_IN),
							  .ENQ(writeMaster_out$ENQ),
							  .DEQ(writeMaster_out$DEQ),
							  .CLR(writeMaster_out$CLR),
							  .D_OUT(writeMaster_out$D_OUT),
							  .FULL_N(writeMaster_out$FULL_N),
							  .EMPTY_N(writeMaster_out$EMPTY_N));

  // rule RL_s_config_axiReadSpecialRange
  assign WILL_FIRE_RL_s_config_axiReadSpecialRange =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
	     _0_CONCAT_s_config_readSlave_in_first__5_BITS_1_ETC___d58 &&
	     !s_config_readBusy ;
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