mkAQLQueueFetcher.v 748 KB
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//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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// On Mon May 13 18:24:49 CEST 2019
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//
//
// Ports:
// Name                         I/O  size props
// s_axi_arready                  O     1 reg
// s_axi_rvalid                   O     1 reg
// s_axi_rdata                    O    64
// s_axi_rresp                    O     2
// s_axi_awready                  O     1
// s_axi_wready                   O     1
// s_axi_bvalid                   O     1 reg
// s_axi_bresp                    O     2
// mpcie_axi_arvalid              O     1 reg
// mpcie_axi_arid                 O     1
// mpcie_axi_araddr               O    64
// mpcie_axi_arlen                O     8
// mpcie_axi_arsize               O     3
// mpcie_axi_arburst              O     2
// mpcie_axi_arlock               O     1
// mpcie_axi_arcache              O     4
// mpcie_axi_arprot               O     3
// mpcie_axi_arqos                O     4
// mpcie_axi_arregion             O     4
// mpcie_axi_rready               O     1 reg
// mpcie_axi_awvalid              O     1 reg
// mpcie_axi_awid                 O     1
// mpcie_axi_awaddr               O    64
// mpcie_axi_awlen                O     8
// mpcie_axi_awsize               O     3
// mpcie_axi_awburst              O     2
// mpcie_axi_awlock               O     1
// mpcie_axi_awcache              O     4
// mpcie_axi_awprot               O     3
// mpcie_axi_awqos                O     4
// mpcie_axi_awregion             O     4
// mpcie_axi_wvalid               O     1 reg
// mpcie_axi_wdata                O   256
// mpcie_axi_wstrb                O    32
// mpcie_axi_wlast                O     1
// mpcie_axi_bready               O     1 reg
// mddr_axi_arvalid               O     1 reg
// mddr_axi_arid                  O     1
// mddr_axi_araddr                O    64
// mddr_axi_arlen                 O     8
// mddr_axi_arsize                O     3
// mddr_axi_arburst               O     2
// mddr_axi_arlock                O     1
// mddr_axi_arcache               O     4
// mddr_axi_arprot                O     3
// mddr_axi_arqos                 O     4
// mddr_axi_arregion              O     4
// mddr_axi_rready                O     1 reg
// mddr_axi_awvalid               O     1 reg
// mddr_axi_awid                  O     1
// mddr_axi_awaddr                O    64
// mddr_axi_awlen                 O     8
// mddr_axi_awsize                O     3
// mddr_axi_awburst               O     2
// mddr_axi_awlock                O     1
// mddr_axi_awcache               O     4
// mddr_axi_awprot                O     3
// mddr_axi_awqos                 O     4
// mddr_axi_awregion              O     4
// mddr_axi_wvalid                O     1 reg
// mddr_axi_wdata                 O   512
// mddr_axi_wstrb                 O    64
// mddr_axi_wlast                 O     1
// mddr_axi_bready                O     1 reg
// new_packages                   O     1 reg
// halt_execution                 O     1
// RDY_interrupt_fetching         O     1 const
// s_axi_aclk                     I     1 clock
// s_axi_aresetn                  I     1 reset
// s_axi_arvalid                  I     1
// s_axi_araddr                   I    12 reg
// s_axi_arprot                   I     3 reg
// s_axi_rready                   I     1
// s_axi_awvalid                  I     1
// s_axi_awaddr                   I    12
// s_axi_awprot                   I     3
// s_axi_wvalid                   I     1
// s_axi_wdata                    I    64
// s_axi_wstrb                    I     8
// s_axi_bready                   I     1
// mpcie_axi_arready              I     1
// mpcie_axi_rvalid               I     1
// mpcie_axi_rid                  I     1 reg
// mpcie_axi_rdata                I   256 reg
// mpcie_axi_rresp                I     2 reg
// mpcie_axi_rlast                I     1 reg
// mpcie_axi_awready              I     1
// mpcie_axi_wready               I     1
// mpcie_axi_bvalid               I     1
// mpcie_axi_bresp                I     2 reg
// mpcie_axi_bid                  I     1 reg
// mddr_axi_arready               I     1
// mddr_axi_rvalid                I     1
// mddr_axi_rid                   I     1 reg
// mddr_axi_rdata                 I   512 reg
// mddr_axi_rresp                 I     2 reg
// mddr_axi_rlast                 I     1 reg
// mddr_axi_awready               I     1
// mddr_axi_wready                I     1
// mddr_axi_bvalid                I     1
// mddr_axi_bresp                 I     2 reg
// mddr_axi_bid                   I     1 reg
// new_packages_ack               I     1
// EN_interrupt_fetching          I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkAQLQueueFetcher(s_axi_aclk,
			 s_axi_aresetn,

			 s_axi_arready,

			 s_axi_arvalid,

			 s_axi_araddr,

			 s_axi_arprot,

			 s_axi_rvalid,

			 s_axi_rready,

			 s_axi_rdata,

			 s_axi_rresp,

			 s_axi_awready,

			 s_axi_awvalid,

			 s_axi_awaddr,

			 s_axi_awprot,

			 s_axi_wready,

			 s_axi_wvalid,

			 s_axi_wdata,

			 s_axi_wstrb,

			 s_axi_bvalid,

			 s_axi_bready,

			 s_axi_bresp,

			 mpcie_axi_arvalid,

			 mpcie_axi_arready,

			 mpcie_axi_arid,

			 mpcie_axi_araddr,

			 mpcie_axi_arlen,

			 mpcie_axi_arsize,

			 mpcie_axi_arburst,

			 mpcie_axi_arlock,

			 mpcie_axi_arcache,

			 mpcie_axi_arprot,

			 mpcie_axi_arqos,

			 mpcie_axi_arregion,

			 mpcie_axi_rready,

			 mpcie_axi_rvalid,

			 mpcie_axi_rid,
			 mpcie_axi_rdata,
			 mpcie_axi_rresp,
			 mpcie_axi_rlast,

			 mpcie_axi_awready,

			 mpcie_axi_awvalid,

			 mpcie_axi_awid,

			 mpcie_axi_awaddr,

			 mpcie_axi_awlen,

			 mpcie_axi_awsize,

			 mpcie_axi_awburst,

			 mpcie_axi_awlock,

			 mpcie_axi_awcache,

			 mpcie_axi_awprot,

			 mpcie_axi_awqos,

			 mpcie_axi_awregion,

			 mpcie_axi_wready,

			 mpcie_axi_wvalid,

			 mpcie_axi_wdata,

			 mpcie_axi_wstrb,

			 mpcie_axi_wlast,

			 mpcie_axi_bvalid,

			 mpcie_axi_bready,

			 mpcie_axi_bresp,
			 mpcie_axi_bid,

			 mddr_axi_arvalid,

			 mddr_axi_arready,

			 mddr_axi_arid,

			 mddr_axi_araddr,

			 mddr_axi_arlen,

			 mddr_axi_arsize,

			 mddr_axi_arburst,

			 mddr_axi_arlock,

			 mddr_axi_arcache,

			 mddr_axi_arprot,

			 mddr_axi_arqos,

			 mddr_axi_arregion,

			 mddr_axi_rready,

			 mddr_axi_rvalid,

			 mddr_axi_rid,
			 mddr_axi_rdata,
			 mddr_axi_rresp,
			 mddr_axi_rlast,

			 mddr_axi_awready,

			 mddr_axi_awvalid,

			 mddr_axi_awid,

			 mddr_axi_awaddr,

			 mddr_axi_awlen,

			 mddr_axi_awsize,

			 mddr_axi_awburst,

			 mddr_axi_awlock,

			 mddr_axi_awcache,

			 mddr_axi_awprot,

			 mddr_axi_awqos,

			 mddr_axi_awregion,

			 mddr_axi_wready,

			 mddr_axi_wvalid,

			 mddr_axi_wdata,

			 mddr_axi_wstrb,

			 mddr_axi_wlast,

			 mddr_axi_bvalid,

			 mddr_axi_bready,

			 mddr_axi_bresp,
			 mddr_axi_bid,

			 new_packages,

			 new_packages_ack,

			 halt_execution,

			 EN_interrupt_fetching,
			 RDY_interrupt_fetching);
  input  s_axi_aclk;
  input  s_axi_aresetn;

  // value method s_rd_arready
  output s_axi_arready;

  // action method s_rd_parvalid
  input  s_axi_arvalid;

  // action method s_rd_paraddr
  input  [11 : 0] s_axi_araddr;

  // action method s_rd_parprot
  input  [2 : 0] s_axi_arprot;

  // value method s_rd_rvalid
  output s_axi_rvalid;

  // action method s_rd_prready
  input  s_axi_rready;

  // value method s_rd_rdata
  output [63 : 0] s_axi_rdata;

  // value method s_rd_rresp
  output [1 : 0] s_axi_rresp;

  // value method s_wr_awready
  output s_axi_awready;

  // action method s_wr_pawvalid
  input  s_axi_awvalid;

  // action method s_wr_pawaddr
  input  [11 : 0] s_axi_awaddr;

  // action method s_wr_pawprot
  input  [2 : 0] s_axi_awprot;

  // value method s_wr_wready
  output s_axi_wready;

  // action method s_wr_pwvalid
  input  s_axi_wvalid;

  // action method s_wr_pwdata
  input  [63 : 0] s_axi_wdata;

  // action method s_wr_pwstrb
  input  [7 : 0] s_axi_wstrb;

  // value method s_wr_bvalid
  output s_axi_bvalid;

  // action method s_wr_pbready
  input  s_axi_bready;

  // value method s_wr_bresp
  output [1 : 0] s_axi_bresp;

  // value method pcie_rd_arvalid
  output mpcie_axi_arvalid;

  // action method pcie_rd_parready
  input  mpcie_axi_arready;

  // value method pcie_rd_arid
  output mpcie_axi_arid;

  // value method pcie_rd_araddr
  output [63 : 0] mpcie_axi_araddr;

  // value method pcie_rd_arlen
  output [7 : 0] mpcie_axi_arlen;

  // value method pcie_rd_arsize
  output [2 : 0] mpcie_axi_arsize;

  // value method pcie_rd_arburst
  output [1 : 0] mpcie_axi_arburst;

  // value method pcie_rd_arlock
  output mpcie_axi_arlock;

  // value method pcie_rd_arcache
  output [3 : 0] mpcie_axi_arcache;

  // value method pcie_rd_arprot
  output [2 : 0] mpcie_axi_arprot;

  // value method pcie_rd_arqos
  output [3 : 0] mpcie_axi_arqos;

  // value method pcie_rd_arregion
  output [3 : 0] mpcie_axi_arregion;

  // value method pcie_rd_aruser

  // value method pcie_rd_rready
  output mpcie_axi_rready;

  // action method pcie_rd_prvalid
  input  mpcie_axi_rvalid;

  // action method pcie_rd_prchannel
  input  mpcie_axi_rid;
  input  [255 : 0] mpcie_axi_rdata;
  input  [1 : 0] mpcie_axi_rresp;
  input  mpcie_axi_rlast;

  // action method pcie_wr_pawready
  input  mpcie_axi_awready;

  // value method pcie_wr_awvalid
  output mpcie_axi_awvalid;

  // value method pcie_wr_awid
  output mpcie_axi_awid;

  // value method pcie_wr_awaddr
  output [63 : 0] mpcie_axi_awaddr;

  // value method pcie_wr_awlen
  output [7 : 0] mpcie_axi_awlen;

  // value method pcie_wr_awsize
  output [2 : 0] mpcie_axi_awsize;

  // value method pcie_wr_awburst
  output [1 : 0] mpcie_axi_awburst;

  // value method pcie_wr_awlock
  output mpcie_axi_awlock;

  // value method pcie_wr_awcache
  output [3 : 0] mpcie_axi_awcache;

  // value method pcie_wr_awprot
  output [2 : 0] mpcie_axi_awprot;

  // value method pcie_wr_awqos
  output [3 : 0] mpcie_axi_awqos;

  // value method pcie_wr_awregion
  output [3 : 0] mpcie_axi_awregion;

  // value method pcie_wr_awuser

  // action method pcie_wr_pwready
  input  mpcie_axi_wready;

  // value method pcie_wr_wvalid
  output mpcie_axi_wvalid;

  // value method pcie_wr_wdata
  output [255 : 0] mpcie_axi_wdata;

  // value method pcie_wr_wstrb
  output [31 : 0] mpcie_axi_wstrb;

  // value method pcie_wr_wlast
  output mpcie_axi_wlast;

  // value method pcie_wr_wuser

  // action method pcie_wr_pbvalid
  input  mpcie_axi_bvalid;

  // value method pcie_wr_bready
  output mpcie_axi_bready;

  // action method pcie_wr_bin
  input  [1 : 0] mpcie_axi_bresp;
  input  mpcie_axi_bid;

  // value method ddr_rd_arvalid
  output mddr_axi_arvalid;

  // action method ddr_rd_parready
  input  mddr_axi_arready;

  // value method ddr_rd_arid
  output mddr_axi_arid;

  // value method ddr_rd_araddr
  output [63 : 0] mddr_axi_araddr;

  // value method ddr_rd_arlen
  output [7 : 0] mddr_axi_arlen;

  // value method ddr_rd_arsize
  output [2 : 0] mddr_axi_arsize;

  // value method ddr_rd_arburst
  output [1 : 0] mddr_axi_arburst;

  // value method ddr_rd_arlock
  output mddr_axi_arlock;

  // value method ddr_rd_arcache
  output [3 : 0] mddr_axi_arcache;

  // value method ddr_rd_arprot
  output [2 : 0] mddr_axi_arprot;

  // value method ddr_rd_arqos
  output [3 : 0] mddr_axi_arqos;

  // value method ddr_rd_arregion
  output [3 : 0] mddr_axi_arregion;

  // value method ddr_rd_aruser

  // value method ddr_rd_rready
  output mddr_axi_rready;

  // action method ddr_rd_prvalid
  input  mddr_axi_rvalid;

  // action method ddr_rd_prchannel
  input  mddr_axi_rid;
  input  [511 : 0] mddr_axi_rdata;
  input  [1 : 0] mddr_axi_rresp;
  input  mddr_axi_rlast;

  // action method ddr_wr_pawready
  input  mddr_axi_awready;

  // value method ddr_wr_awvalid
  output mddr_axi_awvalid;

  // value method ddr_wr_awid
  output mddr_axi_awid;

  // value method ddr_wr_awaddr
  output [63 : 0] mddr_axi_awaddr;

  // value method ddr_wr_awlen
  output [7 : 0] mddr_axi_awlen;

  // value method ddr_wr_awsize
  output [2 : 0] mddr_axi_awsize;

  // value method ddr_wr_awburst
  output [1 : 0] mddr_axi_awburst;

  // value method ddr_wr_awlock
  output mddr_axi_awlock;

  // value method ddr_wr_awcache
  output [3 : 0] mddr_axi_awcache;

  // value method ddr_wr_awprot
  output [2 : 0] mddr_axi_awprot;

  // value method ddr_wr_awqos
  output [3 : 0] mddr_axi_awqos;

  // value method ddr_wr_awregion
  output [3 : 0] mddr_axi_awregion;

  // value method ddr_wr_awuser

  // action method ddr_wr_pwready
  input  mddr_axi_wready;

  // value method ddr_wr_wvalid
  output mddr_axi_wvalid;

  // value method ddr_wr_wdata
  output [511 : 0] mddr_axi_wdata;

  // value method ddr_wr_wstrb
  output [63 : 0] mddr_axi_wstrb;

  // value method ddr_wr_wlast
  output mddr_axi_wlast;

  // value method ddr_wr_wuser

  // action method ddr_wr_pbvalid
  input  mddr_axi_bvalid;

  // value method ddr_wr_bready
  output mddr_axi_bready;

  // action method ddr_wr_bin
  input  [1 : 0] mddr_axi_bresp;
  input  mddr_axi_bid;

  // value method new_packages
  output new_packages;

  // action method new_packages_ack
  input  new_packages_ack;

  // value method halt_execution
  output halt_execution;

  // action method interrupt_fetching
  input  EN_interrupt_fetching;
  output RDY_interrupt_fetching;

  // signals for module outputs
  wire [511 : 0] mddr_axi_wdata;
  wire [255 : 0] mpcie_axi_wdata;
  wire [63 : 0] mddr_axi_araddr,
		mddr_axi_awaddr,
		mddr_axi_wstrb,
		mpcie_axi_araddr,
		mpcie_axi_awaddr,
		s_axi_rdata;
  wire [31 : 0] mpcie_axi_wstrb;
  wire [7 : 0] mddr_axi_arlen,
	       mddr_axi_awlen,
	       mpcie_axi_arlen,
	       mpcie_axi_awlen;
  wire [3 : 0] mddr_axi_arcache,
	       mddr_axi_arqos,
	       mddr_axi_arregion,
	       mddr_axi_awcache,
	       mddr_axi_awqos,
	       mddr_axi_awregion,
	       mpcie_axi_arcache,
	       mpcie_axi_arqos,
	       mpcie_axi_arregion,
	       mpcie_axi_awcache,
	       mpcie_axi_awqos,
	       mpcie_axi_awregion;
  wire [2 : 0] mddr_axi_arprot,
	       mddr_axi_arsize,
	       mddr_axi_awprot,
	       mddr_axi_awsize,
	       mpcie_axi_arprot,
	       mpcie_axi_arsize,
	       mpcie_axi_awprot,
	       mpcie_axi_awsize;
  wire [1 : 0] mddr_axi_arburst,
	       mddr_axi_awburst,
	       mpcie_axi_arburst,
	       mpcie_axi_awburst,
	       s_axi_bresp,
	       s_axi_rresp;
  wire RDY_interrupt_fetching,
       halt_execution,
       mddr_axi_arid,
       mddr_axi_arlock,
       mddr_axi_arvalid,
       mddr_axi_awid,
       mddr_axi_awlock,
       mddr_axi_awvalid,
       mddr_axi_bready,
       mddr_axi_rready,
       mddr_axi_wlast,
       mddr_axi_wvalid,
       mpcie_axi_arid,
       mpcie_axi_arlock,
       mpcie_axi_arvalid,
       mpcie_axi_awid,
       mpcie_axi_awlock,
       mpcie_axi_awvalid,
       mpcie_axi_bready,
       mpcie_axi_rready,
       mpcie_axi_wlast,
       mpcie_axi_wvalid,
       new_packages,
       s_axi_arready,
       s_axi_awready,
       s_axi_bvalid,
       s_axi_rvalid,
       s_axi_wready;

  // inlined wires
  reg [3 : 0] mddr_rd_warcache$wget,
	      mddr_wr_wawcache$wget,
	      mpcie_rd_master_rd_warcache$wget,
	      mpcie_wr_wawcache$wget;
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  wire [515 : 0] mddr_rd_rinpkg$wget;
  wire [259 : 0] mpcie_rd_master_rd_rinpkg$wget;
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  wire [72 : 0] s_config_writeSlave_dataIn_rv$port0__write_1,
		s_config_writeSlave_dataIn_rv$port1__read,
		s_config_writeSlave_dataIn_rv$port2__read;
  wire [15 : 0] s_config_writeSlave_addrIn_rv$port0__write_1,
		s_config_writeSlave_addrIn_rv$port1__read,
		s_config_writeSlave_addrIn_rv$port2__read;
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  wire [2 : 0] mddr_wr_rinpkg$wget, mpcie_wr_rinpkg$wget;
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  wire initializeFSM_start_wire$whas,
       initializeFSM_state_set_pw$whas,
       s_config_readIsHandled$whas,
       s_config_writeIsHandled$whas,
       s_config_writeSlave_addrIn_rv$EN_port0__write,
       s_config_writeSlave_addrIn_rv$EN_port1__write,
       s_config_writeSlave_dataIn_rv$EN_port0__write,
       s_config_writeSlave_dataIn_rv$EN_port1__write,
       updateFSM_par_blocks_1_start_wire$whas,
       updateFSM_par_blocks_1_state_set_pw$whas,
       updateFSM_par_blocks_start_wire$whas,
       updateFSM_par_running$whas,
       updateFSM_start_wire$whas,
       updateFSM_state_set_pw$whas;

  // register aql_ddr_addr
  reg [63 : 0] aql_ddr_addr;
  wire [63 : 0] aql_ddr_addr$D_IN;
  wire aql_ddr_addr$EN;

  // register aql_host_addr
  reg [63 : 0] aql_host_addr;
  wire [63 : 0] aql_host_addr$D_IN;
  wire aql_host_addr$EN;

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  // register aql_queue_mod_mask
  reg [15 : 0] aql_queue_mod_mask;
  wire [15 : 0] aql_queue_mod_mask$D_IN;
  wire aql_queue_mod_mask$EN;

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  // register aql_queue_size
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  reg [3 : 0] aql_queue_size;
  wire [3 : 0] aql_queue_size$D_IN;
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  wire aql_queue_size$EN;

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  // register aql_queue_size_calc
  reg [16 : 0] aql_queue_size_calc;
  wire [16 : 0] aql_queue_size_calc$D_IN;
  wire aql_queue_size_calc$EN;

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  // register aql_read_index_addr
  reg [63 : 0] aql_read_index_addr;
  wire [63 : 0] aql_read_index_addr$D_IN;
  wire aql_read_index_addr$EN;

  // register ddrInitAddr
  reg [63 : 0] ddrInitAddr;
  reg [63 : 0] ddrInitAddr$D_IN;
  wire ddrInitAddr$EN;

  // register id
  reg [63 : 0] id;
  wire [63 : 0] id$D_IN;
  wire id$EN;

  // register initializeFSM_start_reg
  reg initializeFSM_start_reg;
  wire initializeFSM_start_reg$D_IN, initializeFSM_start_reg$EN;

  // register initializeFSM_start_reg_1
  reg initializeFSM_start_reg_1;
  wire initializeFSM_start_reg_1$D_IN, initializeFSM_start_reg_1$EN;

  // register initializeFSM_state_can_overlap
  reg initializeFSM_state_can_overlap;
  wire initializeFSM_state_can_overlap$D_IN,
       initializeFSM_state_can_overlap$EN;

  // register initializeFSM_state_fired
  reg initializeFSM_state_fired;
  wire initializeFSM_state_fired$D_IN, initializeFSM_state_fired$EN;

  // register initializeFSM_state_mkFSMstate
  reg [3 : 0] initializeFSM_state_mkFSMstate;
  reg [3 : 0] initializeFSM_state_mkFSMstate$D_IN;
  wire initializeFSM_state_mkFSMstate$EN;

  // register mpcie_rd_task_data_output_reg
  reg [30 : 0] mpcie_rd_task_data_output_reg;
  wire [30 : 0] mpcie_rd_task_data_output_reg$D_IN;
  wire mpcie_rd_task_data_output_reg$EN;

  // register mpcie_rd_task_data_requests_reg
  reg [101 : 0] mpcie_rd_task_data_requests_reg;
  wire [101 : 0] mpcie_rd_task_data_requests_reg$D_IN;
  wire mpcie_rd_task_data_requests_reg$EN;

  // register new_packages_wire
  reg new_packages_wire;
  wire new_packages_wire$D_IN, new_packages_wire$EN;

  // register pasid_addr_host
  reg [63 : 0] pasid_addr_host;
  wire [63 : 0] pasid_addr_host$D_IN;
  wire pasid_addr_host$EN;

  // register pkgCur
  reg [511 : 0] pkgCur;
  reg [511 : 0] pkgCur$D_IN;
  wire pkgCur$EN;

  // register pkgFetchCntr
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  reg [16 : 0] pkgFetchCntr;
  wire [16 : 0] pkgFetchCntr$D_IN;
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  wire pkgFetchCntr$EN;

  // register pkgInvalidateCntr
  reg [63 : 0] pkgInvalidateCntr;
  wire [63 : 0] pkgInvalidateCntr$D_IN;
  wire pkgInvalidateCntr$EN;

  // register read_index
  reg [63 : 0] read_index;
  wire [63 : 0] read_index$D_IN;
  wire read_index$EN;

  // register read_index_old
  reg [63 : 0] read_index_old;
  wire [63 : 0] read_index_old$D_IN;
  wire read_index_old$EN;

  // register s_config_readBusy
  reg s_config_readBusy;
  wire s_config_readBusy$D_IN, s_config_readBusy$EN;

  // register s_config_writeBusy
  reg s_config_writeBusy;
  wire s_config_writeBusy$D_IN, s_config_writeBusy$EN;

  // register s_config_writeSlave_addrIn_rv
  reg [15 : 0] s_config_writeSlave_addrIn_rv;
  wire [15 : 0] s_config_writeSlave_addrIn_rv$D_IN;
  wire s_config_writeSlave_addrIn_rv$EN;

  // register s_config_writeSlave_dataIn_rv
  reg [72 : 0] s_config_writeSlave_dataIn_rv;
  wire [72 : 0] s_config_writeSlave_dataIn_rv$D_IN;
  wire s_config_writeSlave_dataIn_rv$EN;

  // register status_fetch_iterations
  reg [63 : 0] status_fetch_iterations;
  wire [63 : 0] status_fetch_iterations$D_IN;
  wire status_fetch_iterations$EN;

  // register status_idle_cycles
  reg [63 : 0] status_idle_cycles;
  wire [63 : 0] status_idle_cycles$D_IN;
  wire status_idle_cycles$EN;

  // register status_idle_cycles_t
  reg [63 : 0] status_idle_cycles_t;
  wire [63 : 0] status_idle_cycles_t$D_IN;
  wire status_idle_cycles_t$EN;

  // register status_initialized
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  reg status_initialized;
  wire status_initialized$D_IN, status_initialized$EN;
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  // register status_packages_fetched
  reg [63 : 0] status_packages_fetched;
  wire [63 : 0] status_packages_fetched$D_IN;
  wire status_packages_fetched$EN;

  // register status_packages_invalidated
  reg [63 : 0] status_packages_invalidated;
  wire [63 : 0] status_packages_invalidated$D_IN;
  wire status_packages_invalidated$EN;

  // register status_proc1
  reg [63 : 0] status_proc1;
  wire [63 : 0] status_proc1$D_IN;
  wire status_proc1$EN;

  // register status_proc2
  reg [63 : 0] status_proc2;
  wire [63 : 0] status_proc2$D_IN;
  wire status_proc2$EN;

  // register status_proc3
  reg [63 : 0] status_proc3;
  wire [63 : 0] status_proc3$D_IN;
  wire status_proc3$EN;

  // register status_proc4
  reg [63 : 0] status_proc4;
  wire [63 : 0] status_proc4$D_IN;
  wire status_proc4$EN;

  // register status_proc5
  reg [63 : 0] status_proc5;
  wire [63 : 0] status_proc5$D_IN;
  wire status_proc5$EN;

  // register status_proc6
  reg [63 : 0] status_proc6;
  wire [63 : 0] status_proc6$D_IN;
  wire status_proc6$EN;

  // register status_proc7
  reg [63 : 0] status_proc7;
  wire [63 : 0] status_proc7$D_IN;
  wire status_proc7$EN;

  // register status_proc8
  reg [63 : 0] status_proc8;
  wire [63 : 0] status_proc8$D_IN;
  wire status_proc8$EN;

  // register status_proc9
  reg [63 : 0] status_proc9;
  wire [63 : 0] status_proc9$D_IN;
  wire status_proc9$EN;

  // register updateCntr
  reg [31 : 0] updateCntr;
  wire [31 : 0] updateCntr$D_IN;
  wire updateCntr$EN;

  // register updateFSM_par_blocks_1_start_reg
  reg updateFSM_par_blocks_1_start_reg;
  wire updateFSM_par_blocks_1_start_reg$D_IN,
       updateFSM_par_blocks_1_start_reg$EN;

  // register updateFSM_par_blocks_1_state_can_overlap
  reg updateFSM_par_blocks_1_state_can_overlap;
  wire updateFSM_par_blocks_1_state_can_overlap$D_IN,
       updateFSM_par_blocks_1_state_can_overlap$EN;

  // register updateFSM_par_blocks_1_state_fired
  reg updateFSM_par_blocks_1_state_fired;
  wire updateFSM_par_blocks_1_state_fired$D_IN,
       updateFSM_par_blocks_1_state_fired$EN;

  // register updateFSM_par_blocks_1_state_mkFSMstate
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  reg [2 : 0] updateFSM_par_blocks_1_state_mkFSMstate;
  reg [2 : 0] updateFSM_par_blocks_1_state_mkFSMstate$D_IN;
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  wire updateFSM_par_blocks_1_state_mkFSMstate$EN;

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  // register updateFSM_par_blocks_fired
  reg updateFSM_par_blocks_fired;
  wire updateFSM_par_blocks_fired$D_IN, updateFSM_par_blocks_fired$EN;

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  // register updateFSM_par_blocks_start_reg
  reg updateFSM_par_blocks_start_reg;
  wire updateFSM_par_blocks_start_reg$D_IN, updateFSM_par_blocks_start_reg$EN;

  // register updateFSM_start_reg
  reg updateFSM_start_reg;
  wire updateFSM_start_reg$D_IN, updateFSM_start_reg$EN;

  // register updateFSM_start_reg_1
  reg updateFSM_start_reg_1;
  wire updateFSM_start_reg_1$D_IN, updateFSM_start_reg_1$EN;

  // register updateFSM_state_can_overlap
  reg updateFSM_state_can_overlap;
  wire updateFSM_state_can_overlap$D_IN, updateFSM_state_can_overlap$EN;

  // register updateFSM_state_fired
  reg updateFSM_state_fired;
  wire updateFSM_state_fired$D_IN, updateFSM_state_fired$EN;

  // register updateFSM_state_mkFSMstate
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  reg [4 : 0] updateFSM_state_mkFSMstate;
  reg [4 : 0] updateFSM_state_mkFSMstate$D_IN;
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  wire updateFSM_state_mkFSMstate$EN;

  // register update_rate
  reg [63 : 0] update_rate;
  wire [63 : 0] update_rate$D_IN;
  wire update_rate$EN;

  // register write_index
  reg [63 : 0] write_index;
  reg [63 : 0] write_index$D_IN;
  wire write_index$EN;

  // register write_index_addr_host
  reg [63 : 0] write_index_addr_host;
  wire [63 : 0] write_index_addr_host$D_IN;
  wire write_index_addr_host$EN;

  // register write_index_offset
  reg [4 : 0] write_index_offset;
  wire [4 : 0] write_index_offset$D_IN;
  wire write_index_offset$EN;

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