mkMSIXIntrCtrl.v 517 KB
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//
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
//
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// On Wed Jul  5 18:26:03 CEST 2017
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//
//
// Ports:
// Name                         I/O  size props
// S_AXI_arready                  O     1 reg
// S_AXI_rvalid                   O     1 reg
// S_AXI_rdata                    O    32
// S_AXI_rresp                    O     2
// S_AXI_awready                  O     1
// S_AXI_wready                   O     1
// S_AXI_bvalid                   O     1 reg
// S_AXI_bresp                    O     2
// cfg_interrupt_msix_address     O    64 const
// cfg_interrupt_msix_data        O    32 const
// cfg_interrupt_msix_int         O     1 const
// M_AXI_arvalid                  O     1 reg
// M_AXI_araddr                   O    64
// M_AXI_arprot                   O     3
// M_AXI_rready                   O     1 reg
// M_AXI_awvalid                  O     1
// M_AXI_awaddr                   O    64
// M_AXI_awprot                   O     3
// M_AXI_wvalid                   O     1
// M_AXI_wdata                    O    32
// M_AXI_wstrb                    O     4
// M_AXI_bready                   O     1 reg
// S_AXI_ACLK                     I     1 clock
// S_AXI_ARESETN                  I     1 reset
// S_AXI_arvalid                  I     1
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// S_AXI_araddr                   I    16 reg
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// S_AXI_arprot                   I     3 reg
// S_AXI_rready                   I     1
// S_AXI_awvalid                  I     1
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// S_AXI_awaddr                   I    16
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// S_AXI_awprot                   I     3
// S_AXI_wvalid                   I     1
// S_AXI_wdata                    I    32
// S_AXI_wstrb                    I     4
// S_AXI_bready                   I     1
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// interrupt                      I   132 reg
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// cfg_interrupt_msix_sent        I     1 unused
// cfg_interrupt_msix_fail        I     1 unused
// cfg_interrupt_msix_enable      I     4
// cfg_interrupt_msix_mask        I     4
// M_AXI_arready                  I     1
// M_AXI_rvalid                   I     1
// M_AXI_rdata                    I    32 reg
// M_AXI_rresp                    I     2 reg
// M_AXI_awready                  I     1
// M_AXI_wready                   I     1
// M_AXI_bvalid                   I     1
// M_AXI_bresp                    I     2 reg
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkMSIXIntrCtrl(S_AXI_ACLK,
		      S_AXI_ARESETN,

		      S_AXI_arready,

		      S_AXI_arvalid,

		      S_AXI_araddr,

		      S_AXI_arprot,

		      S_AXI_rvalid,

		      S_AXI_rready,

		      S_AXI_rdata,

		      S_AXI_rresp,

		      S_AXI_awready,

		      S_AXI_awvalid,

		      S_AXI_awaddr,

		      S_AXI_awprot,

		      S_AXI_wready,

		      S_AXI_wvalid,

		      S_AXI_wdata,

		      S_AXI_wstrb,

		      S_AXI_bvalid,

		      S_AXI_bready,

		      S_AXI_bresp,

		      interrupt,

		      cfg_interrupt_msix_address,

		      cfg_interrupt_msix_data,

		      cfg_interrupt_msix_int,

		      cfg_interrupt_msix_sent,

		      cfg_interrupt_msix_fail,

		      cfg_interrupt_msix_enable,

		      cfg_interrupt_msix_mask,

		      M_AXI_arvalid,

		      M_AXI_arready,

		      M_AXI_araddr,

		      M_AXI_arprot,

		      M_AXI_rready,

		      M_AXI_rvalid,

		      M_AXI_rdata,

		      M_AXI_rresp,

		      M_AXI_awready,

		      M_AXI_awvalid,

		      M_AXI_awaddr,

		      M_AXI_awprot,

		      M_AXI_wready,

		      M_AXI_wvalid,

		      M_AXI_wdata,

		      M_AXI_wstrb,

		      M_AXI_bvalid,

		      M_AXI_bready,

		      M_AXI_bresp);
  input  S_AXI_ACLK;
  input  S_AXI_ARESETN;

  // value method s_rd_arready
  output S_AXI_arready;

  // action method s_rd_parvalid
  input  S_AXI_arvalid;

  // action method s_rd_paraddr
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  input  [15 : 0] S_AXI_araddr;
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  // action method s_rd_parprot
  input  [2 : 0] S_AXI_arprot;

  // value method s_rd_rvalid
  output S_AXI_rvalid;

  // action method s_rd_prready
  input  S_AXI_rready;

  // value method s_rd_rdata
  output [31 : 0] S_AXI_rdata;

  // value method s_rd_rresp
  output [1 : 0] S_AXI_rresp;

  // value method s_wr_awready
  output S_AXI_awready;

  // action method s_wr_pawvalid
  input  S_AXI_awvalid;

  // action method s_wr_pawaddr
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  input  [15 : 0] S_AXI_awaddr;
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  // action method s_wr_pawprot
  input  [2 : 0] S_AXI_awprot;

  // value method s_wr_wready
  output S_AXI_wready;

  // action method s_wr_pwvalid
  input  S_AXI_wvalid;

  // action method s_wr_pwdata
  input  [31 : 0] S_AXI_wdata;

  // action method s_wr_pwstrb
  input  [3 : 0] S_AXI_wstrb;

  // value method s_wr_bvalid
  output S_AXI_bvalid;

  // action method s_wr_pbready
  input  S_AXI_bready;

  // value method s_wr_bresp
  output [1 : 0] S_AXI_bresp;

  // action method _interrupts
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  input  [131 : 0] interrupt;
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  // value method intr_address
  output [63 : 0] cfg_interrupt_msix_address;

  // value method intr_data
  output [31 : 0] cfg_interrupt_msix_data;

  // value method intr_interrupt
  output cfg_interrupt_msix_int;

  // action method intr__sent
  input  cfg_interrupt_msix_sent;

  // action method intr__fail
  input  cfg_interrupt_msix_fail;

  // action method intr__enable
  input  [3 : 0] cfg_interrupt_msix_enable;

  // action method intr__mask
  input  [3 : 0] cfg_interrupt_msix_mask;

  // value method m_rd_arvalid
  output M_AXI_arvalid;

  // action method m_rd_parready
  input  M_AXI_arready;

  // value method m_rd_araddr
  output [63 : 0] M_AXI_araddr;

  // value method m_rd_arprot
  output [2 : 0] M_AXI_arprot;

  // value method m_rd_rready
  output M_AXI_rready;

  // action method m_rd_prvalid
  input  M_AXI_rvalid;

  // action method m_rd_prdata
  input  [31 : 0] M_AXI_rdata;

  // action method m_rd_prresp
  input  [1 : 0] M_AXI_rresp;

  // action method m_wr_pawready
  input  M_AXI_awready;

  // value method m_wr_awvalid
  output M_AXI_awvalid;

  // value method m_wr_awaddr
  output [63 : 0] M_AXI_awaddr;

  // value method m_wr_awprot
  output [2 : 0] M_AXI_awprot;

  // action method m_wr_pwready
  input  M_AXI_wready;

  // value method m_wr_wvalid
  output M_AXI_wvalid;

  // value method m_wr_wdata
  output [31 : 0] M_AXI_wdata;

  // value method m_wr_wstrb
  output [3 : 0] M_AXI_wstrb;

  // action method m_wr_pbvalid
  input  M_AXI_bvalid;

  // value method m_wr_bready
  output M_AXI_bready;

  // action method m_wr_pbresp
  input  [1 : 0] M_AXI_bresp;

  // signals for module outputs
  wire [63 : 0] M_AXI_araddr, M_AXI_awaddr, cfg_interrupt_msix_address;
  wire [31 : 0] M_AXI_wdata, S_AXI_rdata, cfg_interrupt_msix_data;
  wire [3 : 0] M_AXI_wstrb;
  wire [2 : 0] M_AXI_arprot, M_AXI_awprot;
  wire [1 : 0] S_AXI_bresp, S_AXI_rresp;
  wire M_AXI_arvalid,
       M_AXI_awvalid,
       M_AXI_bready,
       M_AXI_rready,
       M_AXI_wvalid,
       S_AXI_arready,
       S_AXI_awready,
       S_AXI_bvalid,
       S_AXI_rvalid,
       S_AXI_wready,
       cfg_interrupt_msix_int;

  // inlined wires
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  wire [95 : 0] msixTable_serverAdapterA_outData_outData$wget,
		msixTable_serverAdapterB_outData_outData$wget;
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  wire [67 : 0] writeMaster_addrOut_rv$port0__write_1,
		writeMaster_addrOut_rv$port1__read,
		writeMaster_addrOut_rv$port2__read;
  wire [36 : 0] s_config_writeSlave_dataIn_rv$port0__write_1,
		s_config_writeSlave_dataIn_rv$port1__read,
		s_config_writeSlave_dataIn_rv$port2__read,
		writeMaster_dataOut_rv$port0__write_1,
		writeMaster_dataOut_rv$port1__read,
		writeMaster_dataOut_rv$port2__read;
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  wire [19 : 0] s_config_writeSlave_addrIn_rv$port0__write_1,
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		s_config_writeSlave_addrIn_rv$port1__read,
		s_config_writeSlave_addrIn_rv$port2__read;
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  wire [8 : 0] nextInterrupt_rv$port1__read,
	       nextInterrupt_rv$port1__write_1,
	       nextInterrupt_rv$port2__read;
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  wire [1 : 0] msixTable_serverAdapterB_s1_1$wget;
  wire msixTable_serverAdapterA_outData_deqCalled$whas,
       msixTable_serverAdapterA_outData_enqData$whas,
       msixTable_serverAdapterA_outData_outData$whas,
       msixTable_serverAdapterB_cnt_1$whas,
       msixTable_serverAdapterB_outData_enqData$whas,
       msixTable_serverAdapterB_outData_outData$whas,
       msixTable_serverAdapterB_writeWithResp$whas,
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       nextInterrupt_rv$EN_port1__write,
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       s_config_readIsHandled$whas,
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       s_config_writeSlave_addrIn_rv$EN_port0__write,
       s_config_writeSlave_addrIn_rv$EN_port1__write,
       s_config_writeSlave_dataIn_rv$EN_port0__write,
       s_config_writeSlave_dataIn_rv$EN_port1__write,
       send_pending$EN_port0__write,
       send_pending$port1__read,
       send_pending$port2__read,
       writeMaster_addrOut_rv$EN_port0__write,
       writeMaster_addrOut_rv$EN_port1__write,
       writeMaster_dataOut_rv$EN_port0__write,
       writeMaster_dataOut_rv$EN_port1__write;

  // register active
  reg active;
  wire active$D_IN, active$EN;

  // register completionCntr
  reg [15 : 0] completionCntr;
  wire [15 : 0] completionCntr$D_IN;
  wire completionCntr$EN;

  // register completionDelay
  reg [15 : 0] completionDelay;
  wire [15 : 0] completionDelay$D_IN;
  wire completionDelay$EN;

  // register completionReg
  reg [31 : 0] completionReg;
  wire [31 : 0] completionReg$D_IN;
  wire completionReg$EN;

  // register enableAndMask
  reg [31 : 0] enableAndMask;
  wire [31 : 0] enableAndMask$D_IN;
  wire enableAndMask$EN;

  // register id
  reg [31 : 0] id;
  wire [31 : 0] id$D_IN;
  wire id$EN;

  // register interrupt_last_0
  reg interrupt_last_0;
  wire interrupt_last_0$D_IN, interrupt_last_0$EN;

  // register interrupt_last_1
  reg interrupt_last_1;
  wire interrupt_last_1$D_IN, interrupt_last_1$EN;

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  // register interrupt_last_10
  reg interrupt_last_10;
  wire interrupt_last_10$D_IN, interrupt_last_10$EN;
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  // register interrupt_last_100
  reg interrupt_last_100;
  wire interrupt_last_100$D_IN, interrupt_last_100$EN;
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  // register interrupt_last_101
  reg interrupt_last_101;
  wire interrupt_last_101$D_IN, interrupt_last_101$EN;
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  // register interrupt_last_102
  reg interrupt_last_102;
  wire interrupt_last_102$D_IN, interrupt_last_102$EN;
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  // register interrupt_last_103
  reg interrupt_last_103;
  wire interrupt_last_103$D_IN, interrupt_last_103$EN;
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  // register interrupt_last_104
  reg interrupt_last_104;
  wire interrupt_last_104$D_IN, interrupt_last_104$EN;
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  // register interrupt_last_105
  reg interrupt_last_105;
  wire interrupt_last_105$D_IN, interrupt_last_105$EN;
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  // register interrupt_last_106
  reg interrupt_last_106;
  wire interrupt_last_106$D_IN, interrupt_last_106$EN;
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  // register interrupt_last_107
  reg interrupt_last_107;
  wire interrupt_last_107$D_IN, interrupt_last_107$EN;
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  // register interrupt_last_108
  reg interrupt_last_108;
  wire interrupt_last_108$D_IN, interrupt_last_108$EN;
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  // register interrupt_last_109
  reg interrupt_last_109;
  wire interrupt_last_109$D_IN, interrupt_last_109$EN;
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  // register interrupt_last_11
  reg interrupt_last_11;
  wire interrupt_last_11$D_IN, interrupt_last_11$EN;
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  // register interrupt_last_110
  reg interrupt_last_110;
  wire interrupt_last_110$D_IN, interrupt_last_110$EN;
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  // register interrupt_last_111
  reg interrupt_last_111;
  wire interrupt_last_111$D_IN, interrupt_last_111$EN;
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  // register interrupt_last_112
  reg interrupt_last_112;
  wire interrupt_last_112$D_IN, interrupt_last_112$EN;
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  // register interrupt_last_113
  reg interrupt_last_113;
  wire interrupt_last_113$D_IN, interrupt_last_113$EN;
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  // register interrupt_last_114
  reg interrupt_last_114;
  wire interrupt_last_114$D_IN, interrupt_last_114$EN;
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  // register interrupt_last_115
  reg interrupt_last_115;
  wire interrupt_last_115$D_IN, interrupt_last_115$EN;
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  // register interrupt_last_116
  reg interrupt_last_116;
  wire interrupt_last_116$D_IN, interrupt_last_116$EN;
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  // register interrupt_last_117
  reg interrupt_last_117;
  wire interrupt_last_117$D_IN, interrupt_last_117$EN;
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  // register interrupt_last_118
  reg interrupt_last_118;
  wire interrupt_last_118$D_IN, interrupt_last_118$EN;
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  // register interrupt_last_119
  reg interrupt_last_119;
  wire interrupt_last_119$D_IN, interrupt_last_119$EN;
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  // register interrupt_last_12
  reg interrupt_last_12;
  wire interrupt_last_12$D_IN, interrupt_last_12$EN;
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  // register interrupt_last_120
  reg interrupt_last_120;
  wire interrupt_last_120$D_IN, interrupt_last_120$EN;
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  // register interrupt_last_121
  reg interrupt_last_121;
  wire interrupt_last_121$D_IN, interrupt_last_121$EN;
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  // register interrupt_last_122
  reg interrupt_last_122;
  wire interrupt_last_122$D_IN, interrupt_last_122$EN;
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  // register interrupt_last_123
  reg interrupt_last_123;
  wire interrupt_last_123$D_IN, interrupt_last_123$EN;
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  // register interrupt_last_124
  reg interrupt_last_124;
  wire interrupt_last_124$D_IN, interrupt_last_124$EN;
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  // register interrupt_last_125
  reg interrupt_last_125;
  wire interrupt_last_125$D_IN, interrupt_last_125$EN;
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  // register interrupt_last_126
  reg interrupt_last_126;
  wire interrupt_last_126$D_IN, interrupt_last_126$EN;
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  // register interrupt_last_127
  reg interrupt_last_127;
  wire interrupt_last_127$D_IN, interrupt_last_127$EN;
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  // register interrupt_last_128
  reg interrupt_last_128;
  wire interrupt_last_128$D_IN, interrupt_last_128$EN;
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  // register interrupt_last_129
  reg interrupt_last_129;
  wire interrupt_last_129$D_IN, interrupt_last_129$EN;
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  // register interrupt_last_13
  reg interrupt_last_13;
  wire interrupt_last_13$D_IN, interrupt_last_13$EN;
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  // register interrupt_last_130
  reg interrupt_last_130;
  wire interrupt_last_130$D_IN, interrupt_last_130$EN;
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  // register interrupt_last_131
  reg interrupt_last_131;
  wire interrupt_last_131$D_IN, interrupt_last_131$EN;
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  // register interrupt_last_14
  reg interrupt_last_14;
  wire interrupt_last_14$D_IN, interrupt_last_14$EN;
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  // register interrupt_last_15
  reg interrupt_last_15;
  wire interrupt_last_15$D_IN, interrupt_last_15$EN;
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  // register interrupt_last_16
  reg interrupt_last_16;
  wire interrupt_last_16$D_IN, interrupt_last_16$EN;
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  // register interrupt_last_17
  reg interrupt_last_17;
  wire interrupt_last_17$D_IN, interrupt_last_17$EN;
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  // register interrupt_last_18
  reg interrupt_last_18;
  wire interrupt_last_18$D_IN, interrupt_last_18$EN;

  // register interrupt_last_19
  reg interrupt_last_19;
  wire interrupt_last_19$D_IN, interrupt_last_19$EN;

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  // register interrupt_last_2
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  reg interrupt_last_2;
  wire interrupt_last_2$D_IN, interrupt_last_2$EN;
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  reg interrupt_last_20;
  wire interrupt_last_20$D_IN, interrupt_last_20$EN;
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  // register interrupt_last_21
  reg interrupt_last_21;
  wire interrupt_last_21$D_IN, interrupt_last_21$EN;

  // register interrupt_last_22
  reg interrupt_last_22;
  wire interrupt_last_22$D_IN, interrupt_last_22$EN;

  // register interrupt_last_23
  reg interrupt_last_23;
  wire interrupt_last_23$D_IN, interrupt_last_23$EN;

  // register interrupt_last_24
  reg interrupt_last_24;
  wire interrupt_last_24$D_IN, interrupt_last_24$EN;

  // register interrupt_last_25
  reg interrupt_last_25;
  wire interrupt_last_25$D_IN, interrupt_last_25$EN;

  // register interrupt_last_26
  reg interrupt_last_26;
  wire interrupt_last_26$D_IN, interrupt_last_26$EN;

  // register interrupt_last_27
  reg interrupt_last_27;
  wire interrupt_last_27$D_IN, interrupt_last_27$EN;

  // register interrupt_last_28
  reg interrupt_last_28;
  wire interrupt_last_28$D_IN, interrupt_last_28$EN;

  // register interrupt_last_29
  reg interrupt_last_29;
  wire interrupt_last_29$D_IN, interrupt_last_29$EN;

  // register interrupt_last_3
  reg interrupt_last_3;
  wire interrupt_last_3$D_IN, interrupt_last_3$EN;

  // register interrupt_last_30
  reg interrupt_last_30;
  wire interrupt_last_30$D_IN, interrupt_last_30$EN;

  // register interrupt_last_31
  reg interrupt_last_31;
  wire interrupt_last_31$D_IN, interrupt_last_31$EN;

  // register interrupt_last_32
  reg interrupt_last_32;
  wire interrupt_last_32$D_IN, interrupt_last_32$EN;

  // register interrupt_last_33
  reg interrupt_last_33;
  wire interrupt_last_33$D_IN, interrupt_last_33$EN;

  // register interrupt_last_34
  reg interrupt_last_34;
  wire interrupt_last_34$D_IN, interrupt_last_34$EN;

  // register interrupt_last_35
  reg interrupt_last_35;
  wire interrupt_last_35$D_IN, interrupt_last_35$EN;

  // register interrupt_last_36
  reg interrupt_last_36;
  wire interrupt_last_36$D_IN, interrupt_last_36$EN;

  // register interrupt_last_37
  reg interrupt_last_37;
  wire interrupt_last_37$D_IN, interrupt_last_37$EN;

  // register interrupt_last_38
  reg interrupt_last_38;
  wire interrupt_last_38$D_IN, interrupt_last_38$EN;

  // register interrupt_last_39
  reg interrupt_last_39;
  wire interrupt_last_39$D_IN, interrupt_last_39$EN;

  // register interrupt_last_4
  reg interrupt_last_4;
  wire interrupt_last_4$D_IN, interrupt_last_4$EN;

  // register interrupt_last_40
  reg interrupt_last_40;
  wire interrupt_last_40$D_IN, interrupt_last_40$EN;

  // register interrupt_last_41
  reg interrupt_last_41;
  wire interrupt_last_41$D_IN, interrupt_last_41$EN;

  // register interrupt_last_42
  reg interrupt_last_42;
  wire interrupt_last_42$D_IN, interrupt_last_42$EN;

  // register interrupt_last_43
  reg interrupt_last_43;
  wire interrupt_last_43$D_IN, interrupt_last_43$EN;

  // register interrupt_last_44
  reg interrupt_last_44;
  wire interrupt_last_44$D_IN, interrupt_last_44$EN;

  // register interrupt_last_45
  reg interrupt_last_45;
  wire interrupt_last_45$D_IN, interrupt_last_45$EN;

  // register interrupt_last_46
  reg interrupt_last_46;
  wire interrupt_last_46$D_IN, interrupt_last_46$EN;

  // register interrupt_last_47
  reg interrupt_last_47;
  wire interrupt_last_47$D_IN, interrupt_last_47$EN;

  // register interrupt_last_48
  reg interrupt_last_48;
  wire interrupt_last_48$D_IN, interrupt_last_48$EN;

  // register interrupt_last_49
  reg interrupt_last_49;
  wire interrupt_last_49$D_IN, interrupt_last_49$EN;

  // register interrupt_last_5
  reg interrupt_last_5;
  wire interrupt_last_5$D_IN, interrupt_last_5$EN;

  // register interrupt_last_50
  reg interrupt_last_50;
  wire interrupt_last_50$D_IN, interrupt_last_50$EN;

  // register interrupt_last_51
  reg interrupt_last_51;
  wire interrupt_last_51$D_IN, interrupt_last_51$EN;

  // register interrupt_last_52
  reg interrupt_last_52;
  wire interrupt_last_52$D_IN, interrupt_last_52$EN;

  // register interrupt_last_53
  reg interrupt_last_53;
  wire interrupt_last_53$D_IN, interrupt_last_53$EN;

  // register interrupt_last_54
  reg interrupt_last_54;
  wire interrupt_last_54$D_IN, interrupt_last_54$EN;

  // register interrupt_last_55
  reg interrupt_last_55;
  wire interrupt_last_55$D_IN, interrupt_last_55$EN;

  // register interrupt_last_56
  reg interrupt_last_56;
  wire interrupt_last_56$D_IN, interrupt_last_56$EN;

  // register interrupt_last_57
  reg interrupt_last_57;
  wire interrupt_last_57$D_IN, interrupt_last_57$EN;

  // register interrupt_last_58
  reg interrupt_last_58;
  wire interrupt_last_58$D_IN, interrupt_last_58$EN;

  // register interrupt_last_59
  reg interrupt_last_59;
  wire interrupt_last_59$D_IN, interrupt_last_59$EN;

  // register interrupt_last_6
  reg interrupt_last_6;
  wire interrupt_last_6$D_IN, interrupt_last_6$EN;

  // register interrupt_last_60
  reg interrupt_last_60;
  wire interrupt_last_60$D_IN, interrupt_last_60$EN;

  // register interrupt_last_61
  reg interrupt_last_61;
  wire interrupt_last_61$D_IN, interrupt_last_61$EN;

  // register interrupt_last_62
  reg interrupt_last_62;
  wire interrupt_last_62$D_IN, interrupt_last_62$EN;

  // register interrupt_last_63
  reg interrupt_last_63;
  wire interrupt_last_63$D_IN, interrupt_last_63$EN;

  // register interrupt_last_64
  reg interrupt_last_64;
  wire interrupt_last_64$D_IN, interrupt_last_64$EN;

  // register interrupt_last_65
  reg interrupt_last_65;
  wire interrupt_last_65$D_IN, interrupt_last_65$EN;

  // register interrupt_last_66
  reg interrupt_last_66;
  wire interrupt_last_66$D_IN, interrupt_last_66$EN;

  // register interrupt_last_67
  reg interrupt_last_67;
  wire interrupt_last_67$D_IN, interrupt_last_67$EN;

  // register interrupt_last_68
  reg interrupt_last_68;
  wire interrupt_last_68$D_IN, interrupt_last_68$EN;

  // register interrupt_last_69
  reg interrupt_last_69;
  wire interrupt_last_69$D_IN, interrupt_last_69$EN;

  // register interrupt_last_7
  reg interrupt_last_7;
  wire interrupt_last_7$D_IN, interrupt_last_7$EN;

  // register interrupt_last_70
  reg interrupt_last_70;
  wire interrupt_last_70$D_IN, interrupt_last_70$EN;

  // register interrupt_last_71
  reg interrupt_last_71;
  wire interrupt_last_71$D_IN, interrupt_last_71$EN;

  // register interrupt_last_72
  reg interrupt_last_72;
  wire interrupt_last_72$D_IN, interrupt_last_72$EN;

  // register interrupt_last_73
  reg interrupt_last_73;
  wire interrupt_last_73$D_IN, interrupt_last_73$EN;

  // register interrupt_last_74
  reg interrupt_last_74;
  wire interrupt_last_74$D_IN, interrupt_last_74$EN;

  // register interrupt_last_75
  reg interrupt_last_75;
  wire interrupt_last_75$D_IN, interrupt_last_75$EN;

  // register interrupt_last_76
  reg interrupt_last_76;
  wire interrupt_last_76$D_IN, interrupt_last_76$EN;

  // register interrupt_last_77
  reg interrupt_last_77;
  wire interrupt_last_77$D_IN, interrupt_last_77$EN;

  // register interrupt_last_78
  reg interrupt_last_78;
  wire interrupt_last_78$D_IN, interrupt_last_78$EN;

  // register interrupt_last_79
  reg interrupt_last_79;
  wire interrupt_last_79$D_IN, interrupt_last_79$EN;

  // register interrupt_last_8
  reg interrupt_last_8;
  wire interrupt_last_8$D_IN, interrupt_last_8$EN;

  // register interrupt_last_80
  reg interrupt_last_80;
  wire interrupt_last_80$D_IN, interrupt_last_80$EN;

  // register interrupt_last_81
  reg interrupt_last_81;
  wire interrupt_last_81$D_IN, interrupt_last_81$EN;

  // register interrupt_last_82
  reg interrupt_last_82;
  wire interrupt_last_82$D_IN, interrupt_last_82$EN;

  // register interrupt_last_83
  reg interrupt_last_83;
  wire interrupt_last_83$D_IN, interrupt_last_83$EN;

  // register interrupt_last_84
  reg interrupt_last_84;
  wire interrupt_last_84$D_IN, interrupt_last_84$EN;

  // register interrupt_last_85
  reg interrupt_last_85;
  wire interrupt_last_85$D_IN, interrupt_last_85$EN;

  // register interrupt_last_86
  reg interrupt_last_86;
  wire interrupt_last_86$D_IN, interrupt_last_86$EN;

  // register interrupt_last_87
  reg interrupt_last_87;
  wire interrupt_last_87$D_IN, interrupt_last_87$EN;

  // register interrupt_last_88
  reg interrupt_last_88;
  wire interrupt_last_88$D_IN, interrupt_last_88$EN;

  // register interrupt_last_89
  reg interrupt_last_89;
  wire interrupt_last_89$D_IN, interrupt_last_89$EN;

  // register interrupt_last_9
  reg interrupt_last_9;
  wire interrupt_last_9$D_IN, interrupt_last_9$EN;

  // register interrupt_last_90
  reg interrupt_last_90;
  wire interrupt_last_90$D_IN, interrupt_last_90$EN;

  // register interrupt_last_91
  reg interrupt_last_91;
  wire interrupt_last_91$D_IN, interrupt_last_91$EN;

  // register interrupt_last_92
  reg interrupt_last_92;
  wire interrupt_last_92$D_IN, interrupt_last_92$EN;

  // register interrupt_last_93
  reg interrupt_last_93;
  wire interrupt_last_93$D_IN, interrupt_last_93$EN;

  // register interrupt_last_94
  reg interrupt_last_94;
  wire interrupt_last_94$D_IN, interrupt_last_94$EN;

  // register interrupt_last_95
  reg interrupt_last_95;
  wire interrupt_last_95$D_IN, interrupt_last_95$EN;

  // register interrupt_last_96
  reg interrupt_last_96;
  wire interrupt_last_96$D_IN, interrupt_last_96$EN;

  // register interrupt_last_97
  reg interrupt_last_97;
  wire interrupt_last_97$D_IN, interrupt_last_97$EN;

  // register interrupt_last_98
  reg interrupt_last_98;
  wire interrupt_last_98$D_IN, interrupt_last_98$EN;

  // register interrupt_last_99
  reg interrupt_last_99;
  wire interrupt_last_99$D_IN, interrupt_last_99$EN;

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  // register interrupts_inw_0
  reg interrupts_inw_0;
  wire interrupts_inw_0$D_IN, interrupts_inw_0$EN;
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  // register interrupts_inw_1
  reg interrupts_inw_1;
  wire interrupts_inw_1$D_IN, interrupts_inw_1$EN;
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  // register interrupts_inw_10
  reg interrupts_inw_10;
  wire interrupts_inw_10$D_IN, interrupts_inw_10$EN;
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  // register interrupts_inw_100
  reg interrupts_inw_100;
  wire interrupts_inw_100$D_IN, interrupts_inw_100$EN;
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  // register interrupts_inw_101
  reg interrupts_inw_101;
  wire interrupts_inw_101$D_IN, interrupts_inw_101$EN;
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  // register interrupts_inw_102
  reg interrupts_inw_102;
  wire interrupts_inw_102$D_IN, interrupts_inw_102$EN;
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  // register interrupts_inw_103
  reg interrupts_inw_103;
  wire interrupts_inw_103$D_IN, interrupts_inw_103$EN;
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  // register interrupts_inw_104
  reg interrupts_inw_104;
  wire interrupts_inw_104$D_IN, interrupts_inw_104$EN;
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  // register interrupts_inw_105
  reg interrupts_inw_105;
  wire interrupts_inw_105$D_IN, interrupts_inw_105$EN;
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  // register interrupts_inw_106
  reg interrupts_inw_106;
  wire interrupts_inw_106$D_IN, interrupts_inw_106$EN;
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  // register interrupts_inw_107
  reg interrupts_inw_107;
  wire interrupts_inw_107$D_IN, interrupts_inw_107$EN;
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  // register interrupts_inw_108
  reg interrupts_inw_108;
  wire interrupts_inw_108$D_IN, interrupts_inw_108$EN;
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  // register interrupts_inw_109
  reg interrupts_inw_109;
  wire interrupts_inw_109$D_IN, interrupts_inw_109$EN;
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  // register interrupts_inw_11
  reg interrupts_inw_11;
  wire interrupts_inw_11$D_IN, interrupts_inw_11$EN;
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  // register interrupts_inw_110
  reg interrupts_inw_110;
  wire interrupts_inw_110$D_IN, interrupts_inw_110$EN;
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  // register interrupts_inw_111
  reg interrupts_inw_111;
  wire interrupts_inw_111$D_IN, interrupts_inw_111$EN;
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  // register interrupts_inw_112
  reg interrupts_inw_112;
  wire interrupts_inw_112$D_IN, interrupts_inw_112$EN;
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  // register interrupts_inw_113
  reg interrupts_inw_113;
  wire interrupts_inw_113$D_IN, interrupts_inw_113$EN;
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  // register interrupts_inw_114
  reg interrupts_inw_114;
  wire interrupts_inw_114$D_IN, interrupts_inw_114$EN;
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