Mux.scala 3.12 KB
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package chisel.axi.axi4
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import  chisel3._
import  chisel3.util._
import  chisel.axi.Axi4._
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object AxiMux {
  /** I/O Bundle for AXI mux.
   *  @param n Number of slave interfaces.
   *  @param axi Implicit AXI interface configuration.
   **/
  class IO(n: Int)(implicit axi: Configuration) extends Bundle {
    val saxi = Vec(n, Slave(axi))
    val maxi = Master(axi)
  }
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}

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/** Connect n AXI-MM masters to one AXI-MM slave.
 *  @param n Number of slave interfaces.
 *  @param axi Implicit AXI interface configuration.
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 **/
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class AxiMux(n: Int)(implicit axi: Configuration) extends Module {
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  val io = IO(new AxiMux.IO(n))
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  // states of the FSM
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  val waiting :: in_burst :: Nil = Enum(2)
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  val r_curr  = RegInit(UInt(log2Ceil(n).W), 0.U)
  val w_curr  = RegInit(UInt(log2Ceil(n).W), 0.U)
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  val r_state = RegInit(waiting)
  val w_state = RegInit(waiting)
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  def next_r() = r_curr := Mux(r_curr === (n - 1).U, 0.U, r_curr + 1.U)
  def next_w() = w_curr := Mux(w_curr === (n - 1).U, 0.U, w_curr + 1.U)
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  /* tie-offs / wire defaults for connected slaves */
  for (s <- io.saxi) {
    /* READ ADDR */
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    s.readAddr.ready     := false.B
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    /* READ DATA */
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    s.readData.bits.defaults
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    s.readData.valid     := false.B
    s.readData.bits.data := 0.U
    s.readData.bits.id   := 0.U
    s.readData.bits.last := false.B
    s.readData.bits.resp := 0.U
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    /* WRITE ADDR */
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    s.writeAddr.ready    := false.B
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    /* WRITE DATA */
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    s.writeData.ready    := false.B
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    /* WRITE RESP */
    s.writeResp.valid    := false.B
    s.writeResp.bits.defaults
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  }

  /* wiring for currently selected slaves */
  /* READ ADDRESS */
  io.saxi(r_curr).readAddr.ready := io.maxi.readAddr.ready
  io.maxi.readAddr.valid := io.saxi(r_curr).readAddr.valid
  io.maxi.readAddr.bits := io.saxi(r_curr).readAddr.bits

  /* READ DATA */
  io.maxi.readData.ready := io.saxi(r_curr).readData.ready
  io.saxi(r_curr).readData.valid := io.maxi.readData.valid
  io.saxi(r_curr).readData.bits := io.maxi.readData.bits

  /* WRITE ADDRESS */
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  io.maxi.writeAddr.bits.defaults
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  io.saxi(w_curr).writeAddr.ready := io.maxi.writeAddr.ready
  io.maxi.writeAddr.valid         := io.saxi(w_curr).writeAddr.valid
  io.maxi.writeAddr.bits          := io.saxi(w_curr).writeAddr.bits

  /* WRITE DATA */
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  io.maxi.writeData.bits.defaults
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  io.saxi(w_curr).writeData.ready := io.maxi.writeData.ready
  io.maxi.writeData.valid         := io.saxi(w_curr).writeData.valid
  io.maxi.writeData.bits          := io.saxi(w_curr).writeData.bits

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  /* WRITE RESP */
  io.maxi.writeResp.ready := io.saxi(r_curr).writeResp.ready
  io.saxi(r_curr).writeResp.valid := io.maxi.writeResp.valid
  io.saxi(r_curr).writeResp.bits  := io.maxi.writeResp.bits

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  when (r_state === waiting) {
    when (io.saxi(r_curr).readAddr.valid) { r_state := in_burst }
    .otherwise { next_r() }
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  }
  .otherwise {
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    when (io.saxi(r_curr).readData.bits.last) {
      next_r()
      r_state := waiting
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    }
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  }
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  when (w_state === waiting) {
    when (io.saxi(w_curr).writeAddr.valid) { w_state := in_burst }
    .otherwise { next_w() }
  }
  .otherwise {
    when (io.saxi(w_curr).writeData.bits.last) {
      next_w()
      w_state := waiting
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    }
  }
}