mkMSIXIntrCtrl.v 517 KB
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  // register vector_control_48
  reg vector_control_48;
  wire vector_control_48$D_IN, vector_control_48$EN;

  // register vector_control_49
  reg vector_control_49;
  wire vector_control_49$D_IN, vector_control_49$EN;

  // register vector_control_5
  reg vector_control_5;
  wire vector_control_5$D_IN, vector_control_5$EN;

  // register vector_control_50
  reg vector_control_50;
  wire vector_control_50$D_IN, vector_control_50$EN;

  // register vector_control_51
  reg vector_control_51;
  wire vector_control_51$D_IN, vector_control_51$EN;

  // register vector_control_52
  reg vector_control_52;
  wire vector_control_52$D_IN, vector_control_52$EN;

  // register vector_control_53
  reg vector_control_53;
  wire vector_control_53$D_IN, vector_control_53$EN;

  // register vector_control_54
  reg vector_control_54;
  wire vector_control_54$D_IN, vector_control_54$EN;

  // register vector_control_55
  reg vector_control_55;
  wire vector_control_55$D_IN, vector_control_55$EN;

  // register vector_control_56
  reg vector_control_56;
  wire vector_control_56$D_IN, vector_control_56$EN;

  // register vector_control_57
  reg vector_control_57;
  wire vector_control_57$D_IN, vector_control_57$EN;

  // register vector_control_58
  reg vector_control_58;
  wire vector_control_58$D_IN, vector_control_58$EN;

  // register vector_control_59
  reg vector_control_59;
  wire vector_control_59$D_IN, vector_control_59$EN;

  // register vector_control_6
  reg vector_control_6;
  wire vector_control_6$D_IN, vector_control_6$EN;

  // register vector_control_60
  reg vector_control_60;
  wire vector_control_60$D_IN, vector_control_60$EN;

  // register vector_control_61
  reg vector_control_61;
  wire vector_control_61$D_IN, vector_control_61$EN;

  // register vector_control_62
  reg vector_control_62;
  wire vector_control_62$D_IN, vector_control_62$EN;

  // register vector_control_63
  reg vector_control_63;
  wire vector_control_63$D_IN, vector_control_63$EN;

  // register vector_control_64
  reg vector_control_64;
  wire vector_control_64$D_IN, vector_control_64$EN;

  // register vector_control_65
  reg vector_control_65;
  wire vector_control_65$D_IN, vector_control_65$EN;

  // register vector_control_66
  reg vector_control_66;
  wire vector_control_66$D_IN, vector_control_66$EN;

  // register vector_control_67
  reg vector_control_67;
  wire vector_control_67$D_IN, vector_control_67$EN;

  // register vector_control_68
  reg vector_control_68;
  wire vector_control_68$D_IN, vector_control_68$EN;

  // register vector_control_69
  reg vector_control_69;
  wire vector_control_69$D_IN, vector_control_69$EN;

  // register vector_control_7
  reg vector_control_7;
  wire vector_control_7$D_IN, vector_control_7$EN;

  // register vector_control_70
  reg vector_control_70;
  wire vector_control_70$D_IN, vector_control_70$EN;

  // register vector_control_71
  reg vector_control_71;
  wire vector_control_71$D_IN, vector_control_71$EN;

  // register vector_control_72
  reg vector_control_72;
  wire vector_control_72$D_IN, vector_control_72$EN;

  // register vector_control_73
  reg vector_control_73;
  wire vector_control_73$D_IN, vector_control_73$EN;

  // register vector_control_74
  reg vector_control_74;
  wire vector_control_74$D_IN, vector_control_74$EN;

  // register vector_control_75
  reg vector_control_75;
  wire vector_control_75$D_IN, vector_control_75$EN;

  // register vector_control_76
  reg vector_control_76;
  wire vector_control_76$D_IN, vector_control_76$EN;

  // register vector_control_77
  reg vector_control_77;
  wire vector_control_77$D_IN, vector_control_77$EN;

  // register vector_control_78
  reg vector_control_78;
  wire vector_control_78$D_IN, vector_control_78$EN;

  // register vector_control_79
  reg vector_control_79;
  wire vector_control_79$D_IN, vector_control_79$EN;

  // register vector_control_8
  reg vector_control_8;
  wire vector_control_8$D_IN, vector_control_8$EN;

  // register vector_control_80
  reg vector_control_80;
  wire vector_control_80$D_IN, vector_control_80$EN;

  // register vector_control_81
  reg vector_control_81;
  wire vector_control_81$D_IN, vector_control_81$EN;

  // register vector_control_82
  reg vector_control_82;
  wire vector_control_82$D_IN, vector_control_82$EN;

  // register vector_control_83
  reg vector_control_83;
  wire vector_control_83$D_IN, vector_control_83$EN;

  // register vector_control_84
  reg vector_control_84;
  wire vector_control_84$D_IN, vector_control_84$EN;

  // register vector_control_85
  reg vector_control_85;
  wire vector_control_85$D_IN, vector_control_85$EN;

  // register vector_control_86
  reg vector_control_86;
  wire vector_control_86$D_IN, vector_control_86$EN;

  // register vector_control_87
  reg vector_control_87;
  wire vector_control_87$D_IN, vector_control_87$EN;

  // register vector_control_88
  reg vector_control_88;
  wire vector_control_88$D_IN, vector_control_88$EN;

  // register vector_control_89
  reg vector_control_89;
  wire vector_control_89$D_IN, vector_control_89$EN;

  // register vector_control_9
  reg vector_control_9;
  wire vector_control_9$D_IN, vector_control_9$EN;

  // register vector_control_90
  reg vector_control_90;
  wire vector_control_90$D_IN, vector_control_90$EN;

  // register vector_control_91
  reg vector_control_91;
  wire vector_control_91$D_IN, vector_control_91$EN;

  // register vector_control_92
  reg vector_control_92;
  wire vector_control_92$D_IN, vector_control_92$EN;

  // register vector_control_93
  reg vector_control_93;
  wire vector_control_93$D_IN, vector_control_93$EN;

  // register vector_control_94
  reg vector_control_94;
  wire vector_control_94$D_IN, vector_control_94$EN;

  // register vector_control_95
  reg vector_control_95;
  wire vector_control_95$D_IN, vector_control_95$EN;

  // register vector_control_96
  reg vector_control_96;
  wire vector_control_96$D_IN, vector_control_96$EN;

  // register vector_control_97
  reg vector_control_97;
  wire vector_control_97$D_IN, vector_control_97$EN;

  // register vector_control_98
  reg vector_control_98;
  wire vector_control_98$D_IN, vector_control_98$EN;

  // register vector_control_99
  reg vector_control_99;
  wire vector_control_99$D_IN, vector_control_99$EN;

  // register writeMaster_addrOut_rv
  reg [67 : 0] writeMaster_addrOut_rv;
  wire [67 : 0] writeMaster_addrOut_rv$D_IN;
  wire writeMaster_addrOut_rv$EN;

  // register writeMaster_dataOut_rv
  reg [36 : 0] writeMaster_dataOut_rv;
  wire [36 : 0] writeMaster_dataOut_rv$D_IN;
  wire writeMaster_dataOut_rv$EN;

  // ports of submodule msixTable_memory
  wire [95 : 0] msixTable_memory$DIA,
		msixTable_memory$DIB,
		msixTable_memory$DOA,
		msixTable_memory$DOB;
  wire [11 : 0] msixTable_memory$WEA, msixTable_memory$WEB;
  wire [7 : 0] msixTable_memory$ADDRA, msixTable_memory$ADDRB;
  wire msixTable_memory$ENA, msixTable_memory$ENB;

  // ports of submodule msixTable_serverAdapterA_outDataCore
  wire [95 : 0] msixTable_serverAdapterA_outDataCore$D_IN,
		msixTable_serverAdapterA_outDataCore$D_OUT;
  wire msixTable_serverAdapterA_outDataCore$CLR,
       msixTable_serverAdapterA_outDataCore$DEQ,
       msixTable_serverAdapterA_outDataCore$EMPTY_N,
       msixTable_serverAdapterA_outDataCore$ENQ,
       msixTable_serverAdapterA_outDataCore$FULL_N;

  // ports of submodule msixTable_serverAdapterB_outDataCore
  wire [95 : 0] msixTable_serverAdapterB_outDataCore$D_IN,
		msixTable_serverAdapterB_outDataCore$D_OUT;
  wire msixTable_serverAdapterB_outDataCore$CLR,
       msixTable_serverAdapterB_outDataCore$DEQ,
       msixTable_serverAdapterB_outDataCore$EMPTY_N,
       msixTable_serverAdapterB_outDataCore$ENQ,
       msixTable_serverAdapterB_outDataCore$FULL_N;

  // ports of submodule pbaRet
  reg [31 : 0] pbaRet$D_IN;
  wire [31 : 0] pbaRet$D_OUT;
  wire pbaRet$CLR, pbaRet$DEQ, pbaRet$EMPTY_N, pbaRet$ENQ, pbaRet$FULL_N;

  // ports of submodule readMaster_in
  wire [66 : 0] readMaster_in$D_IN, readMaster_in$D_OUT;
  wire readMaster_in$CLR,
       readMaster_in$DEQ,
       readMaster_in$EMPTY_N,
       readMaster_in$ENQ;

  // ports of submodule readMaster_out
  wire [33 : 0] readMaster_out$D_IN;
  wire readMaster_out$CLR,
       readMaster_out$DEQ,
       readMaster_out$ENQ,
       readMaster_out$FULL_N;

  // ports of submodule s_config_readSlave_in
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  wire [18 : 0] s_config_readSlave_in$D_IN, s_config_readSlave_in$D_OUT;
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  wire s_config_readSlave_in$CLR,
       s_config_readSlave_in$DEQ,
       s_config_readSlave_in$EMPTY_N,
       s_config_readSlave_in$ENQ,
       s_config_readSlave_in$FULL_N;

  // ports of submodule s_config_readSlave_out
  reg [33 : 0] s_config_readSlave_out$D_IN;
  wire [33 : 0] s_config_readSlave_out$D_OUT;
  wire s_config_readSlave_out$CLR,
       s_config_readSlave_out$DEQ,
       s_config_readSlave_out$EMPTY_N,
       s_config_readSlave_out$ENQ,
       s_config_readSlave_out$FULL_N;

  // ports of submodule s_config_writeSlave_in
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  wire [54 : 0] s_config_writeSlave_in$D_IN, s_config_writeSlave_in$D_OUT;
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  wire s_config_writeSlave_in$CLR,
       s_config_writeSlave_in$DEQ,
       s_config_writeSlave_in$EMPTY_N,
       s_config_writeSlave_in$ENQ,
       s_config_writeSlave_in$FULL_N;

  // ports of submodule s_config_writeSlave_out
  wire [1 : 0] s_config_writeSlave_out$D_IN, s_config_writeSlave_out$D_OUT;
  wire s_config_writeSlave_out$CLR,
       s_config_writeSlave_out$DEQ,
       s_config_writeSlave_out$EMPTY_N,
       s_config_writeSlave_out$ENQ,
       s_config_writeSlave_out$FULL_N;

  // ports of submodule typeRequest
  reg [2 : 0] typeRequest$D_IN;
  wire [2 : 0] typeRequest$D_OUT;
  wire typeRequest$CLR,
       typeRequest$DEQ,
       typeRequest$EMPTY_N,
       typeRequest$ENQ,
       typeRequest$FULL_N;

  // ports of submodule writeMaster_in
  wire [102 : 0] writeMaster_in$D_IN, writeMaster_in$D_OUT;
  wire writeMaster_in$CLR,
       writeMaster_in$DEQ,
       writeMaster_in$EMPTY_N,
       writeMaster_in$ENQ,
       writeMaster_in$FULL_N;

  // ports of submodule writeMaster_out
  wire [1 : 0] writeMaster_out$D_IN, writeMaster_out$D_OUT;
  wire writeMaster_out$CLR,
       writeMaster_out$DEQ,
       writeMaster_out$EMPTY_N,
       writeMaster_out$ENQ,
       writeMaster_out$FULL_N;

  // rule scheduling signals
Jaco Hofmann's avatar
Jaco Hofmann committed
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  wire WILL_FIRE_RL_catchInterrupt,
       WILL_FIRE_RL_catchInterrupt_1,
       WILL_FIRE_RL_catchInterrupt_10,
       WILL_FIRE_RL_catchInterrupt_100,
       WILL_FIRE_RL_catchInterrupt_101,
       WILL_FIRE_RL_catchInterrupt_102,
       WILL_FIRE_RL_catchInterrupt_103,
       WILL_FIRE_RL_catchInterrupt_104,
       WILL_FIRE_RL_catchInterrupt_105,
       WILL_FIRE_RL_catchInterrupt_106,
       WILL_FIRE_RL_catchInterrupt_107,
       WILL_FIRE_RL_catchInterrupt_108,
       WILL_FIRE_RL_catchInterrupt_109,
       WILL_FIRE_RL_catchInterrupt_11,
       WILL_FIRE_RL_catchInterrupt_110,
       WILL_FIRE_RL_catchInterrupt_111,
       WILL_FIRE_RL_catchInterrupt_112,
       WILL_FIRE_RL_catchInterrupt_113,
       WILL_FIRE_RL_catchInterrupt_114,
       WILL_FIRE_RL_catchInterrupt_115,
       WILL_FIRE_RL_catchInterrupt_116,
       WILL_FIRE_RL_catchInterrupt_117,
       WILL_FIRE_RL_catchInterrupt_118,
       WILL_FIRE_RL_catchInterrupt_119,
       WILL_FIRE_RL_catchInterrupt_12,
       WILL_FIRE_RL_catchInterrupt_120,
       WILL_FIRE_RL_catchInterrupt_121,
       WILL_FIRE_RL_catchInterrupt_122,
       WILL_FIRE_RL_catchInterrupt_123,
       WILL_FIRE_RL_catchInterrupt_124,
       WILL_FIRE_RL_catchInterrupt_125,
       WILL_FIRE_RL_catchInterrupt_126,
       WILL_FIRE_RL_catchInterrupt_127,
       WILL_FIRE_RL_catchInterrupt_128,
       WILL_FIRE_RL_catchInterrupt_129,
       WILL_FIRE_RL_catchInterrupt_13,
       WILL_FIRE_RL_catchInterrupt_130,
       WILL_FIRE_RL_catchInterrupt_131,
       WILL_FIRE_RL_catchInterrupt_14,
       WILL_FIRE_RL_catchInterrupt_15,
       WILL_FIRE_RL_catchInterrupt_16,
       WILL_FIRE_RL_catchInterrupt_17,
       WILL_FIRE_RL_catchInterrupt_18,
       WILL_FIRE_RL_catchInterrupt_19,
       WILL_FIRE_RL_catchInterrupt_2,
       WILL_FIRE_RL_catchInterrupt_20,
       WILL_FIRE_RL_catchInterrupt_21,
       WILL_FIRE_RL_catchInterrupt_22,
       WILL_FIRE_RL_catchInterrupt_23,
       WILL_FIRE_RL_catchInterrupt_24,
       WILL_FIRE_RL_catchInterrupt_25,
       WILL_FIRE_RL_catchInterrupt_26,
       WILL_FIRE_RL_catchInterrupt_27,
       WILL_FIRE_RL_catchInterrupt_28,
       WILL_FIRE_RL_catchInterrupt_29,
       WILL_FIRE_RL_catchInterrupt_3,
       WILL_FIRE_RL_catchInterrupt_30,
       WILL_FIRE_RL_catchInterrupt_31,
       WILL_FIRE_RL_catchInterrupt_32,
       WILL_FIRE_RL_catchInterrupt_33,
       WILL_FIRE_RL_catchInterrupt_34,
       WILL_FIRE_RL_catchInterrupt_35,
       WILL_FIRE_RL_catchInterrupt_36,
       WILL_FIRE_RL_catchInterrupt_37,
       WILL_FIRE_RL_catchInterrupt_38,
       WILL_FIRE_RL_catchInterrupt_39,
       WILL_FIRE_RL_catchInterrupt_4,
       WILL_FIRE_RL_catchInterrupt_40,
       WILL_FIRE_RL_catchInterrupt_41,
       WILL_FIRE_RL_catchInterrupt_42,
       WILL_FIRE_RL_catchInterrupt_43,
       WILL_FIRE_RL_catchInterrupt_44,
       WILL_FIRE_RL_catchInterrupt_45,
       WILL_FIRE_RL_catchInterrupt_46,
       WILL_FIRE_RL_catchInterrupt_47,
       WILL_FIRE_RL_catchInterrupt_48,
       WILL_FIRE_RL_catchInterrupt_49,
       WILL_FIRE_RL_catchInterrupt_5,
       WILL_FIRE_RL_catchInterrupt_50,
       WILL_FIRE_RL_catchInterrupt_51,
       WILL_FIRE_RL_catchInterrupt_52,
       WILL_FIRE_RL_catchInterrupt_53,
       WILL_FIRE_RL_catchInterrupt_54,
       WILL_FIRE_RL_catchInterrupt_55,
       WILL_FIRE_RL_catchInterrupt_56,
       WILL_FIRE_RL_catchInterrupt_57,
       WILL_FIRE_RL_catchInterrupt_58,
       WILL_FIRE_RL_catchInterrupt_59,
       WILL_FIRE_RL_catchInterrupt_6,
       WILL_FIRE_RL_catchInterrupt_60,
       WILL_FIRE_RL_catchInterrupt_61,
       WILL_FIRE_RL_catchInterrupt_62,
       WILL_FIRE_RL_catchInterrupt_63,
       WILL_FIRE_RL_catchInterrupt_64,
       WILL_FIRE_RL_catchInterrupt_65,
       WILL_FIRE_RL_catchInterrupt_66,
       WILL_FIRE_RL_catchInterrupt_67,
       WILL_FIRE_RL_catchInterrupt_68,
       WILL_FIRE_RL_catchInterrupt_69,
       WILL_FIRE_RL_catchInterrupt_7,
       WILL_FIRE_RL_catchInterrupt_70,
       WILL_FIRE_RL_catchInterrupt_71,
       WILL_FIRE_RL_catchInterrupt_72,
       WILL_FIRE_RL_catchInterrupt_73,
       WILL_FIRE_RL_catchInterrupt_74,
       WILL_FIRE_RL_catchInterrupt_75,
       WILL_FIRE_RL_catchInterrupt_76,
       WILL_FIRE_RL_catchInterrupt_77,
       WILL_FIRE_RL_catchInterrupt_78,
       WILL_FIRE_RL_catchInterrupt_79,
       WILL_FIRE_RL_catchInterrupt_8,
       WILL_FIRE_RL_catchInterrupt_80,
       WILL_FIRE_RL_catchInterrupt_81,
       WILL_FIRE_RL_catchInterrupt_82,
       WILL_FIRE_RL_catchInterrupt_83,
       WILL_FIRE_RL_catchInterrupt_84,
       WILL_FIRE_RL_catchInterrupt_85,
       WILL_FIRE_RL_catchInterrupt_86,
       WILL_FIRE_RL_catchInterrupt_87,
       WILL_FIRE_RL_catchInterrupt_88,
       WILL_FIRE_RL_catchInterrupt_89,
       WILL_FIRE_RL_catchInterrupt_9,
       WILL_FIRE_RL_catchInterrupt_90,
       WILL_FIRE_RL_catchInterrupt_91,
       WILL_FIRE_RL_catchInterrupt_92,
       WILL_FIRE_RL_catchInterrupt_93,
       WILL_FIRE_RL_catchInterrupt_94,
       WILL_FIRE_RL_catchInterrupt_95,
       WILL_FIRE_RL_catchInterrupt_96,
       WILL_FIRE_RL_catchInterrupt_97,
       WILL_FIRE_RL_catchInterrupt_98,
       WILL_FIRE_RL_catchInterrupt_99,
       WILL_FIRE_RL_msixTable_serverAdapterA_outData_enqAndDeq,
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       WILL_FIRE_RL_msixTable_serverAdapterA_outData_setFirstEnq,
       WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways,
       WILL_FIRE_RL_msixTable_serverAdapterB_outData_enqAndDeq,
       WILL_FIRE_RL_msixTable_serverAdapterB_outData_setFirstEnq,
       WILL_FIRE_RL_s_config_1_axiWriteFallback,
       WILL_FIRE_RL_s_config_1_axiWriteSpecialRange,
       WILL_FIRE_RL_s_config_axiReadFallback,
       WILL_FIRE_RL_s_config_axiReadSpecial,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3,
       WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed,
       WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled,
       WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled_1,
       WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn,
       WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn_1,
       WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed_1,
       WILL_FIRE_RL_s_config_axiReadSpecial_1,
       WILL_FIRE_RL_s_config_axiReadSpecial_2,
       WILL_FIRE_RL_s_config_axiReadSpecial_3,
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       WILL_FIRE_RL_selectInterrupt,
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       WILL_FIRE_RL_waitForCompletion;

  // inputs to muxes for submodule ports
  reg [11 : 0] MUX_msixTable_memory$b_put_1__VAL_1;
  wire [95 : 0] MUX_msixTable_memory$b_put_3__VAL_1;
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  wire [33 : 0] MUX_s_config_readSlave_out$enq_1__VAL_1,
		MUX_s_config_readSlave_out$enq_1__VAL_2,
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		MUX_s_config_readSlave_out$enq_1__VAL_3,
		MUX_s_config_readSlave_out$enq_1__VAL_4,
		MUX_s_config_readSlave_out$enq_1__VAL_5,
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		MUX_s_config_readSlave_out$enq_1__VAL_6;
  wire MUX_msixTable_memory$b_put_1__SEL_1,
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       MUX_pba_vector_0$write_1__SEL_1,
       MUX_pba_vector_1$write_1__SEL_1,
       MUX_pba_vector_10$write_1__SEL_1,
       MUX_pba_vector_100$write_1__SEL_1,
       MUX_pba_vector_101$write_1__SEL_1,
       MUX_pba_vector_102$write_1__SEL_1,
       MUX_pba_vector_103$write_1__SEL_1,
       MUX_pba_vector_104$write_1__SEL_1,
       MUX_pba_vector_105$write_1__SEL_1,
       MUX_pba_vector_106$write_1__SEL_1,
       MUX_pba_vector_107$write_1__SEL_1,
       MUX_pba_vector_108$write_1__SEL_1,
       MUX_pba_vector_109$write_1__SEL_1,
       MUX_pba_vector_11$write_1__SEL_1,
       MUX_pba_vector_110$write_1__SEL_1,
       MUX_pba_vector_111$write_1__SEL_1,
       MUX_pba_vector_112$write_1__SEL_1,
       MUX_pba_vector_113$write_1__SEL_1,
       MUX_pba_vector_114$write_1__SEL_1,
       MUX_pba_vector_115$write_1__SEL_1,
       MUX_pba_vector_116$write_1__SEL_1,
       MUX_pba_vector_117$write_1__SEL_1,
       MUX_pba_vector_118$write_1__SEL_1,
       MUX_pba_vector_119$write_1__SEL_1,
       MUX_pba_vector_12$write_1__SEL_1,
       MUX_pba_vector_120$write_1__SEL_1,
       MUX_pba_vector_121$write_1__SEL_1,
       MUX_pba_vector_122$write_1__SEL_1,
       MUX_pba_vector_123$write_1__SEL_1,
       MUX_pba_vector_124$write_1__SEL_1,
       MUX_pba_vector_125$write_1__SEL_1,
       MUX_pba_vector_126$write_1__SEL_1,
       MUX_pba_vector_127$write_1__SEL_1,
       MUX_pba_vector_128$write_1__SEL_1,
       MUX_pba_vector_129$write_1__SEL_1,
       MUX_pba_vector_13$write_1__SEL_1,
       MUX_pba_vector_130$write_1__SEL_1,
       MUX_pba_vector_131$write_1__SEL_1,
       MUX_pba_vector_14$write_1__SEL_1,
       MUX_pba_vector_15$write_1__SEL_1,
       MUX_pba_vector_16$write_1__SEL_1,
       MUX_pba_vector_17$write_1__SEL_1,
       MUX_pba_vector_18$write_1__SEL_1,
       MUX_pba_vector_19$write_1__SEL_1,
       MUX_pba_vector_2$write_1__SEL_1,
       MUX_pba_vector_20$write_1__SEL_1,
       MUX_pba_vector_21$write_1__SEL_1,
       MUX_pba_vector_22$write_1__SEL_1,
       MUX_pba_vector_23$write_1__SEL_1,
       MUX_pba_vector_24$write_1__SEL_1,
       MUX_pba_vector_25$write_1__SEL_1,
       MUX_pba_vector_26$write_1__SEL_1,
       MUX_pba_vector_27$write_1__SEL_1,
       MUX_pba_vector_28$write_1__SEL_1,
       MUX_pba_vector_29$write_1__SEL_1,
       MUX_pba_vector_3$write_1__SEL_1,
       MUX_pba_vector_30$write_1__SEL_1,
       MUX_pba_vector_31$write_1__SEL_1,
       MUX_pba_vector_32$write_1__SEL_1,
       MUX_pba_vector_33$write_1__SEL_1,
       MUX_pba_vector_34$write_1__SEL_1,
       MUX_pba_vector_35$write_1__SEL_1,
       MUX_pba_vector_36$write_1__SEL_1,
       MUX_pba_vector_37$write_1__SEL_1,
       MUX_pba_vector_38$write_1__SEL_1,
       MUX_pba_vector_39$write_1__SEL_1,
       MUX_pba_vector_4$write_1__SEL_1,
       MUX_pba_vector_40$write_1__SEL_1,
       MUX_pba_vector_41$write_1__SEL_1,
       MUX_pba_vector_42$write_1__SEL_1,
       MUX_pba_vector_43$write_1__SEL_1,
       MUX_pba_vector_44$write_1__SEL_1,
       MUX_pba_vector_45$write_1__SEL_1,
       MUX_pba_vector_46$write_1__SEL_1,
       MUX_pba_vector_47$write_1__SEL_1,
       MUX_pba_vector_48$write_1__SEL_1,
       MUX_pba_vector_49$write_1__SEL_1,
       MUX_pba_vector_5$write_1__SEL_1,
       MUX_pba_vector_50$write_1__SEL_1,
       MUX_pba_vector_51$write_1__SEL_1,
       MUX_pba_vector_52$write_1__SEL_1,
       MUX_pba_vector_53$write_1__SEL_1,
       MUX_pba_vector_54$write_1__SEL_1,
       MUX_pba_vector_55$write_1__SEL_1,
       MUX_pba_vector_56$write_1__SEL_1,
       MUX_pba_vector_57$write_1__SEL_1,
       MUX_pba_vector_58$write_1__SEL_1,
       MUX_pba_vector_59$write_1__SEL_1,
       MUX_pba_vector_6$write_1__SEL_1,
       MUX_pba_vector_60$write_1__SEL_1,
       MUX_pba_vector_61$write_1__SEL_1,
       MUX_pba_vector_62$write_1__SEL_1,
       MUX_pba_vector_63$write_1__SEL_1,
       MUX_pba_vector_64$write_1__SEL_1,
       MUX_pba_vector_65$write_1__SEL_1,
       MUX_pba_vector_66$write_1__SEL_1,
       MUX_pba_vector_67$write_1__SEL_1,
       MUX_pba_vector_68$write_1__SEL_1,
       MUX_pba_vector_69$write_1__SEL_1,
       MUX_pba_vector_7$write_1__SEL_1,
       MUX_pba_vector_70$write_1__SEL_1,
       MUX_pba_vector_71$write_1__SEL_1,
       MUX_pba_vector_72$write_1__SEL_1,
       MUX_pba_vector_73$write_1__SEL_1,
       MUX_pba_vector_74$write_1__SEL_1,
       MUX_pba_vector_75$write_1__SEL_1,
       MUX_pba_vector_76$write_1__SEL_1,
       MUX_pba_vector_77$write_1__SEL_1,
       MUX_pba_vector_78$write_1__SEL_1,
       MUX_pba_vector_79$write_1__SEL_1,
       MUX_pba_vector_8$write_1__SEL_1,
       MUX_pba_vector_80$write_1__SEL_1,
       MUX_pba_vector_81$write_1__SEL_1,
       MUX_pba_vector_82$write_1__SEL_1,
       MUX_pba_vector_83$write_1__SEL_1,
       MUX_pba_vector_84$write_1__SEL_1,
       MUX_pba_vector_85$write_1__SEL_1,
       MUX_pba_vector_86$write_1__SEL_1,
       MUX_pba_vector_87$write_1__SEL_1,
       MUX_pba_vector_88$write_1__SEL_1,
       MUX_pba_vector_89$write_1__SEL_1,
       MUX_pba_vector_9$write_1__SEL_1,
       MUX_pba_vector_90$write_1__SEL_1,
       MUX_pba_vector_91$write_1__SEL_1,
       MUX_pba_vector_92$write_1__SEL_1,
       MUX_pba_vector_93$write_1__SEL_1,
       MUX_pba_vector_94$write_1__SEL_1,
       MUX_pba_vector_95$write_1__SEL_1,
       MUX_pba_vector_96$write_1__SEL_1,
       MUX_pba_vector_97$write_1__SEL_1,
       MUX_pba_vector_98$write_1__SEL_1,
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       MUX_pba_vector_99$write_1__SEL_1,
       MUX_s_config_readBusy$write_1__SEL_1;
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  // remaining internal signals
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  reg [31 : 0] v__h28374;
  reg SEL_ARR_vector_control_0_81_vector_control_1_8_ETC___d315;
  wire [63 : 0] x_addr__h93628;
  wire [31 : 0] r__h28539;
  wire [15 : 0] addr__h28722, i__h28619, i__h54995;
  wire [7 : 0] IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1830,
	       IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1832,
	       IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1833,
	       IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1835,
	       IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1836,
	       IF_vector_control_100_81_OR_NOT_pba_vector_100_ETC___d1733,
	       IF_vector_control_104_85_OR_NOT_pba_vector_104_ETC___d1729,
	       IF_vector_control_108_89_OR_NOT_pba_vector_108_ETC___d1726,
	       IF_vector_control_112_93_OR_NOT_pba_vector_112_ETC___d1721,
	       IF_vector_control_112_93_OR_NOT_pba_vector_112_ETC___d1723,
	       IF_vector_control_116_97_OR_NOT_pba_vector_116_ETC___d1718,
	       IF_vector_control_120_01_OR_NOT_pba_vector_120_ETC___d1714,
	       IF_vector_control_124_05_OR_NOT_pba_vector_124_ETC___d1711,
	       IF_vector_control_128_09_OR_NOT_pba_vector_128_ETC___d1708,
	       IF_vector_control_12_93_OR_NOT_pba_vector_12_9_ETC___d1820,
	       IF_vector_control_16_97_OR_NOT_pba_vector_16_8_ETC___d1815,
	       IF_vector_control_16_97_OR_NOT_pba_vector_16_8_ETC___d1817,
	       IF_vector_control_20_01_OR_NOT_pba_vector_20_8_ETC___d1812,
	       IF_vector_control_24_05_OR_NOT_pba_vector_24_7_ETC___d1808,
	       IF_vector_control_28_09_OR_NOT_pba_vector_28_7_ETC___d1805,
	       IF_vector_control_32_13_OR_NOT_pba_vector_32_6_ETC___d1799,
	       IF_vector_control_32_13_OR_NOT_pba_vector_32_6_ETC___d1801,
	       IF_vector_control_32_13_OR_NOT_pba_vector_32_6_ETC___d1802,
	       IF_vector_control_36_17_OR_NOT_pba_vector_36_5_ETC___d1796,
	       IF_vector_control_40_21_OR_NOT_pba_vector_40_4_ETC___d1792,
	       IF_vector_control_44_25_OR_NOT_pba_vector_44_4_ETC___d1789,
	       IF_vector_control_48_29_OR_NOT_pba_vector_48_3_ETC___d1784,
	       IF_vector_control_48_29_OR_NOT_pba_vector_48_3_ETC___d1786,
	       IF_vector_control_4_85_OR_NOT_pba_vector_4_06__ETC___d1827,
	       IF_vector_control_52_33_OR_NOT_pba_vector_52_3_ETC___d1781,
	       IF_vector_control_56_37_OR_NOT_pba_vector_56_2_ETC___d1777,
	       IF_vector_control_60_41_OR_NOT_pba_vector_60_1_ETC___d1774,
	       IF_vector_control_64_45_OR_NOT_pba_vector_64_0_ETC___d1767,
	       IF_vector_control_64_45_OR_NOT_pba_vector_64_0_ETC___d1769,
	       IF_vector_control_64_45_OR_NOT_pba_vector_64_0_ETC___d1770,
	       IF_vector_control_68_49_OR_NOT_pba_vector_68_0_ETC___d1764,
	       IF_vector_control_72_53_OR_NOT_pba_vector_72_9_ETC___d1760,
	       IF_vector_control_76_57_OR_NOT_pba_vector_76_9_ETC___d1757,
	       IF_vector_control_80_61_OR_NOT_pba_vector_80_8_ETC___d1752,
	       IF_vector_control_80_61_OR_NOT_pba_vector_80_8_ETC___d1754,
	       IF_vector_control_84_65_OR_NOT_pba_vector_84_7_ETC___d1749,
	       IF_vector_control_88_69_OR_NOT_pba_vector_88_7_ETC___d1745,
	       IF_vector_control_8_89_OR_NOT_pba_vector_8_00__ETC___d1823,
	       IF_vector_control_92_73_OR_NOT_pba_vector_92_6_ETC___d1742,
	       IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1736,
	       IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1738,
	       IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1739;
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  wire [2 : 0] msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32,
	       msixTable_serverAdapterB_cnt_3_PLUS_IF_msixTab_ETC___d89;
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  wire [1 : 0] ab__h18814;
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  wire NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1015,
       NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1315,
       NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d931,
       NOT_vector_control_100_81_218_AND_pba_vector_1_ETC___d1228,
       NOT_vector_control_104_85_230_AND_pba_vector_1_ETC___d1240,
       NOT_vector_control_108_89_241_AND_pba_vector_1_ETC___d1251,
       NOT_vector_control_112_93_254_AND_pba_vector_1_ETC___d1264,
       NOT_vector_control_116_97_265_AND_pba_vector_1_ETC___d1275,
       NOT_vector_control_120_01_277_AND_pba_vector_1_ETC___d1287,
       NOT_vector_control_124_05_288_AND_pba_vector_1_ETC___d1298,
       NOT_vector_control_128_09_304_AND_pba_vector_1_ETC___d1314,
       NOT_vector_control_12_93_55_AND_pba_vector_12__ETC___d965,
       NOT_vector_control_16_97_68_AND_pba_vector_16__ETC___d978,
       NOT_vector_control_20_01_79_AND_pba_vector_20__ETC___d989,
       NOT_vector_control_24_05_91_AND_pba_vector_24__ETC___d1001,
       NOT_vector_control_28_09_002_AND_pba_vector_28_ETC___d1012,
       NOT_vector_control_32_13_016_AND_pba_vector_32_ETC___d1026,
       NOT_vector_control_32_13_016_AND_pba_vector_32_ETC___d1110,
       NOT_vector_control_36_17_027_AND_pba_vector_36_ETC___d1037,
       NOT_vector_control_40_21_039_AND_pba_vector_40_ETC___d1049,
       NOT_vector_control_44_25_050_AND_pba_vector_44_ETC___d1060,
       NOT_vector_control_48_29_063_AND_pba_vector_48_ETC___d1073,
       NOT_vector_control_4_85_32_AND_pba_vector_4_06_ETC___d942,
       NOT_vector_control_52_33_074_AND_pba_vector_52_ETC___d1084,
       NOT_vector_control_56_37_086_AND_pba_vector_56_ETC___d1096,
       NOT_vector_control_60_41_097_AND_pba_vector_60_ETC___d1107,
       NOT_vector_control_64_45_112_AND_pba_vector_64_ETC___d1122,
       NOT_vector_control_64_45_112_AND_pba_vector_64_ETC___d1206,
       NOT_vector_control_68_49_123_AND_pba_vector_68_ETC___d1133,
       NOT_vector_control_72_53_135_AND_pba_vector_72_ETC___d1145,
       NOT_vector_control_76_57_146_AND_pba_vector_76_ETC___d1156,
       NOT_vector_control_80_61_159_AND_pba_vector_80_ETC___d1169,
       NOT_vector_control_84_65_170_AND_pba_vector_84_ETC___d1180,
       NOT_vector_control_88_69_182_AND_pba_vector_88_ETC___d1192,
       NOT_vector_control_8_89_44_AND_pba_vector_8_00_ETC___d954,
       NOT_vector_control_92_73_193_AND_pba_vector_92_ETC___d1203,
       NOT_vector_control_96_77_207_AND_pba_vector_96_ETC___d1217,
       NOT_vector_control_96_77_207_AND_pba_vector_96_ETC___d1301,
       enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907,
       msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902,
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       msixTable_serverAdapterB_cnt_3_SLT_3___d168,
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       s_config_readSlave_in_first__71_BITS_18_TO_5_7_ETC___d174,
       typeRequest_i_notEmpty__27_AND_msixTable_serve_ETC___d333,
       vector_control_0_81_OR_NOT_pba_vector_0_12_316_ETC___d1326,
       vector_control_0_81_OR_NOT_pba_vector_0_12_316_ETC___d1410,
       vector_control_100_81_OR_NOT_pba_vector_100_50_ETC___d1623,
       vector_control_104_85_OR_NOT_pba_vector_104_44_ETC___d1635,
       vector_control_108_89_OR_NOT_pba_vector_108_38_ETC___d1646,
       vector_control_112_93_OR_NOT_pba_vector_112_32_ETC___d1659,
       vector_control_116_97_OR_NOT_pba_vector_116_26_ETC___d1670,
       vector_control_120_01_OR_NOT_pba_vector_120_20_ETC___d1682,
       vector_control_124_05_OR_NOT_pba_vector_124_14_ETC___d1693,
       vector_control_12_93_OR_NOT_pba_vector_12_94_3_ETC___d1360,
       vector_control_16_97_OR_NOT_pba_vector_16_88_3_ETC___d1373,
       vector_control_20_01_OR_NOT_pba_vector_20_82_3_ETC___d1384,
       vector_control_24_05_OR_NOT_pba_vector_24_76_3_ETC___d1396,
       vector_control_28_09_OR_NOT_pba_vector_28_70_3_ETC___d1407,
       vector_control_32_13_OR_NOT_pba_vector_32_60_4_ETC___d1421,
       vector_control_32_13_OR_NOT_pba_vector_32_60_4_ETC___d1505,
       vector_control_36_17_OR_NOT_pba_vector_36_54_4_ETC___d1432,
       vector_control_40_21_OR_NOT_pba_vector_40_48_4_ETC___d1444,
       vector_control_44_25_OR_NOT_pba_vector_44_42_4_ETC___d1455,
       vector_control_48_29_OR_NOT_pba_vector_48_36_4_ETC___d1468,
       vector_control_4_85_OR_NOT_pba_vector_4_06_327_ETC___d1337,
       vector_control_52_33_OR_NOT_pba_vector_52_30_4_ETC___d1479,
       vector_control_56_37_OR_NOT_pba_vector_56_24_4_ETC___d1491,
       vector_control_60_41_OR_NOT_pba_vector_60_18_4_ETC___d1502,
       vector_control_64_45_OR_NOT_pba_vector_64_08_5_ETC___d1517,
       vector_control_64_45_OR_NOT_pba_vector_64_08_5_ETC___d1601,
       vector_control_68_49_OR_NOT_pba_vector_68_02_5_ETC___d1528,
       vector_control_72_53_OR_NOT_pba_vector_72_96_5_ETC___d1540,
       vector_control_76_57_OR_NOT_pba_vector_76_90_5_ETC___d1551,
       vector_control_80_61_OR_NOT_pba_vector_80_84_5_ETC___d1564,
       vector_control_84_65_OR_NOT_pba_vector_84_78_5_ETC___d1575,
       vector_control_88_69_OR_NOT_pba_vector_88_72_5_ETC___d1587,
       vector_control_8_89_OR_NOT_pba_vector_8_00_339_ETC___d1349,
       vector_control_92_73_OR_NOT_pba_vector_92_66_5_ETC___d1598,
       vector_control_96_77_OR_NOT_pba_vector_96_56_6_ETC___d1612,
       vector_control_96_77_OR_NOT_pba_vector_96_56_6_ETC___d1696;
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  // value method s_rd_arready
  assign S_AXI_arready = s_config_readSlave_in$FULL_N ;

  // value method s_rd_rvalid
  assign S_AXI_rvalid = s_config_readSlave_out$EMPTY_N ;

  // value method s_rd_rdata
  assign S_AXI_rdata =
	     s_config_readSlave_out$EMPTY_N ?
	       s_config_readSlave_out$D_OUT[33:2] :
	       32'd0 ;

  // value method s_rd_rresp
  assign S_AXI_rresp =
	     s_config_readSlave_out$EMPTY_N ?
	       s_config_readSlave_out$D_OUT[1:0] :
	       2'd0 ;

  // value method s_wr_awready
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  assign S_AXI_awready = !s_config_writeSlave_addrIn_rv[19] ;
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  // value method s_wr_wready
  assign S_AXI_wready = !s_config_writeSlave_dataIn_rv[36] ;

  // value method s_wr_bvalid
  assign S_AXI_bvalid = s_config_writeSlave_out$EMPTY_N ;

  // value method s_wr_bresp
  assign S_AXI_bresp =
	     s_config_writeSlave_out$EMPTY_N ?
	       s_config_writeSlave_out$D_OUT :
	       2'd0 ;

  // value method intr_address
  assign cfg_interrupt_msix_address = 64'd0 ;

  // value method intr_data
  assign cfg_interrupt_msix_data = 32'd0 ;

  // value method intr_interrupt
  assign cfg_interrupt_msix_int = 1'b0 ;

  // value method m_rd_arvalid
  assign M_AXI_arvalid = readMaster_in$EMPTY_N ;

  // value method m_rd_araddr
  assign M_AXI_araddr =
	     readMaster_in$EMPTY_N ? readMaster_in$D_OUT[66:3] : 64'd0 ;

  // value method m_rd_arprot
  assign M_AXI_arprot =
	     readMaster_in$EMPTY_N ? readMaster_in$D_OUT[2:0] : 3'd0 ;

  // value method m_rd_rready
  assign M_AXI_rready = readMaster_out$FULL_N ;

  // value method m_wr_awvalid
  assign M_AXI_awvalid = writeMaster_addrOut_rv$port1__read[67] ;

  // value method m_wr_awaddr
  assign M_AXI_awaddr =
	     writeMaster_addrOut_rv$port1__read[67] ?
	       writeMaster_addrOut_rv$port1__read[66:3] :
	       64'd0 ;

  // value method m_wr_awprot
  assign M_AXI_awprot =
	     writeMaster_addrOut_rv$port1__read[67] ?
	       writeMaster_addrOut_rv$port1__read[2:0] :
	       3'd0 ;

  // value method m_wr_wvalid
  assign M_AXI_wvalid = writeMaster_dataOut_rv$port1__read[36] ;

  // value method m_wr_wdata
  assign M_AXI_wdata =
	     writeMaster_dataOut_rv$port1__read[36] ?
	       writeMaster_dataOut_rv$port1__read[35:4] :
	       32'd0 ;

  // value method m_wr_wstrb
  assign M_AXI_wstrb =
	     writeMaster_dataOut_rv$port1__read[36] ?
	       writeMaster_dataOut_rv$port1__read[3:0] :
	       4'd0 ;

  // value method m_wr_bready
  assign M_AXI_bready = writeMaster_out$FULL_N ;

  // submodule msixTable_memory
  BRAM2BE #(.PIPELINED(1'd0),
	    .ADDR_WIDTH(32'd8),
	    .DATA_WIDTH(32'd96),
	    .CHUNKSIZE(32'd8),
	    .WE_WIDTH(32'd12),
	    .MEMSIZE(9'd256)) msixTable_memory(.CLKA(S_AXI_ACLK),
					       .CLKB(S_AXI_ACLK),
					       .ADDRA(msixTable_memory$ADDRA),
					       .ADDRB(msixTable_memory$ADDRB),
					       .DIA(msixTable_memory$DIA),
					       .DIB(msixTable_memory$DIB),
					       .WEA(msixTable_memory$WEA),
					       .WEB(msixTable_memory$WEB),
					       .ENA(msixTable_memory$ENA),
					       .ENB(msixTable_memory$ENB),
					       .DOA(msixTable_memory$DOA),
					       .DOB(msixTable_memory$DOB));

  // submodule msixTable_serverAdapterA_outDataCore
  SizedFIFO #(.p1width(32'd96),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) msixTable_serverAdapterA_outDataCore(.RST(S_AXI_ARESETN),
								    .CLK(S_AXI_ACLK),
								    .D_IN(msixTable_serverAdapterA_outDataCore$D_IN),
								    .ENQ(msixTable_serverAdapterA_outDataCore$ENQ),
								    .DEQ(msixTable_serverAdapterA_outDataCore$DEQ),
								    .CLR(msixTable_serverAdapterA_outDataCore$CLR),
								    .D_OUT(msixTable_serverAdapterA_outDataCore$D_OUT),
								    .FULL_N(msixTable_serverAdapterA_outDataCore$FULL_N),
								    .EMPTY_N(msixTable_serverAdapterA_outDataCore$EMPTY_N));

  // submodule msixTable_serverAdapterB_outDataCore
  SizedFIFO #(.p1width(32'd96),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) msixTable_serverAdapterB_outDataCore(.RST(S_AXI_ARESETN),
								    .CLK(S_AXI_ACLK),
								    .D_IN(msixTable_serverAdapterB_outDataCore$D_IN),
								    .ENQ(msixTable_serverAdapterB_outDataCore$ENQ),
								    .DEQ(msixTable_serverAdapterB_outDataCore$DEQ),
								    .CLR(msixTable_serverAdapterB_outDataCore$CLR),
								    .D_OUT(msixTable_serverAdapterB_outDataCore$D_OUT),
								    .FULL_N(msixTable_serverAdapterB_outDataCore$FULL_N),
								    .EMPTY_N(msixTable_serverAdapterB_outDataCore$EMPTY_N));

  // submodule pbaRet
  FIFO2 #(.width(32'd32), .guarded(32'd1)) pbaRet(.RST(S_AXI_ARESETN),
						  .CLK(S_AXI_ACLK),
						  .D_IN(pbaRet$D_IN),
						  .ENQ(pbaRet$ENQ),
						  .DEQ(pbaRet$DEQ),
						  .CLR(pbaRet$CLR),
						  .D_OUT(pbaRet$D_OUT),
						  .FULL_N(pbaRet$FULL_N),
						  .EMPTY_N(pbaRet$EMPTY_N));

  // submodule readMaster_in
  FIFO1 #(.width(32'd67), .guarded(32'd1)) readMaster_in(.RST(S_AXI_ARESETN),
							 .CLK(S_AXI_ACLK),
							 .D_IN(readMaster_in$D_IN),
							 .ENQ(readMaster_in$ENQ),
							 .DEQ(readMaster_in$DEQ),
							 .CLR(readMaster_in$CLR),
							 .D_OUT(readMaster_in$D_OUT),
							 .FULL_N(),
							 .EMPTY_N(readMaster_in$EMPTY_N));

  // submodule readMaster_out
  FIFO1 #(.width(32'd34), .guarded(32'd1)) readMaster_out(.RST(S_AXI_ARESETN),
							  .CLK(S_AXI_ACLK),
							  .D_IN(readMaster_out$D_IN),
							  .ENQ(readMaster_out$ENQ),
							  .DEQ(readMaster_out$DEQ),
							  .CLR(readMaster_out$CLR),
							  .D_OUT(),
							  .FULL_N(readMaster_out$FULL_N),
							  .EMPTY_N());

  // submodule s_config_readSlave_in
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  FIFO2 #(.width(32'd19),
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	  .guarded(32'd1)) s_config_readSlave_in(.RST(S_AXI_ARESETN),
						 .CLK(S_AXI_ACLK),
						 .D_IN(s_config_readSlave_in$D_IN),
						 .ENQ(s_config_readSlave_in$ENQ),
						 .DEQ(s_config_readSlave_in$DEQ),
						 .CLR(s_config_readSlave_in$CLR),
						 .D_OUT(s_config_readSlave_in$D_OUT),
						 .FULL_N(s_config_readSlave_in$FULL_N),
						 .EMPTY_N(s_config_readSlave_in$EMPTY_N));

  // submodule s_config_readSlave_out
  FIFO2 #(.width(32'd34),
	  .guarded(32'd1)) s_config_readSlave_out(.RST(S_AXI_ARESETN),
						  .CLK(S_AXI_ACLK),
						  .D_IN(s_config_readSlave_out$D_IN),
						  .ENQ(s_config_readSlave_out$ENQ),
						  .DEQ(s_config_readSlave_out$DEQ),
						  .CLR(s_config_readSlave_out$CLR),
						  .D_OUT(s_config_readSlave_out$D_OUT),
						  .FULL_N(s_config_readSlave_out$FULL_N),
						  .EMPTY_N(s_config_readSlave_out$EMPTY_N));

  // submodule s_config_writeSlave_in
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  FIFO2 #(.width(32'd55),
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	  .guarded(32'd1)) s_config_writeSlave_in(.RST(S_AXI_ARESETN),
						  .CLK(S_AXI_ACLK),
						  .D_IN(s_config_writeSlave_in$D_IN),
						  .ENQ(s_config_writeSlave_in$ENQ),
						  .DEQ(s_config_writeSlave_in$DEQ),
						  .CLR(s_config_writeSlave_in$CLR),
						  .D_OUT(s_config_writeSlave_in$D_OUT),
						  .FULL_N(s_config_writeSlave_in$FULL_N),
						  .EMPTY_N(s_config_writeSlave_in$EMPTY_N));

  // submodule s_config_writeSlave_out
  FIFO2 #(.width(32'd2),
	  .guarded(32'd1)) s_config_writeSlave_out(.RST(S_AXI_ARESETN),
						   .CLK(S_AXI_ACLK),
						   .D_IN(s_config_writeSlave_out$D_IN),
						   .ENQ(s_config_writeSlave_out$ENQ),
						   .DEQ(s_config_writeSlave_out$DEQ),
						   .CLR(s_config_writeSlave_out$CLR),
						   .D_OUT(s_config_writeSlave_out$D_OUT),
						   .FULL_N(s_config_writeSlave_out$FULL_N),
						   .EMPTY_N(s_config_writeSlave_out$EMPTY_N));

  // submodule typeRequest
  FIFO2 #(.width(32'd3), .guarded(32'd1)) typeRequest(.RST(S_AXI_ARESETN),
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