mkBlueDMA.v 264 KB
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  reg [31 : 0] m_pcie_wr_clkCntr;
  wire [31 : 0] m_pcie_wr_clkCntr$D_IN;
  wire m_pcie_wr_clkCntr$EN;

  // register m_pcie_wr_lastPut
  reg [31 : 0] m_pcie_wr_lastPut;
  wire [31 : 0] m_pcie_wr_lastPut$D_IN;
  wire m_pcie_wr_lastPut$EN;

  // register m_pcie_wr_putDelay
  reg [31 : 0] m_pcie_wr_putDelay;
  wire [31 : 0] m_pcie_wr_putDelay$D_IN;
  wire m_pcie_wr_putDelay$EN;

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  // register m_pcie_wr_task_data_output_reg
  reg [74 : 0] m_pcie_wr_task_data_output_reg;
  wire [74 : 0] m_pcie_wr_task_data_output_reg$D_IN;
  wire m_pcie_wr_task_data_output_reg$EN;

  // register m_pcie_wr_task_data_requests_reg
  reg [134 : 0] m_pcie_wr_task_data_requests_reg;
  wire [134 : 0] m_pcie_wr_task_data_requests_reg$D_IN;
  wire m_pcie_wr_task_data_requests_reg$EN;
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  // register m_pcie_wr_totalPuts
  reg [31 : 0] m_pcie_wr_totalPuts;
  wire [31 : 0] m_pcie_wr_totalPuts$D_IN;
  wire m_pcie_wr_totalPuts$EN;

  // register opInProgress
  reg opInProgress;
  wire opInProgress$D_IN, opInProgress$EN;

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  // register pc_betweenStart
  reg [31 : 0] pc_betweenStart;
  wire [31 : 0] pc_betweenStart$D_IN;
  wire pc_betweenStart$EN;

  // register pc_reqCntr
  reg [11 : 0] pc_reqCntr;
  wire [11 : 0] pc_reqCntr$D_IN;
  wire pc_reqCntr$EN;

  // register pc_start
  reg [31 : 0] pc_start;
  wire [31 : 0] pc_start$D_IN;
  wire pc_start$EN;

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  // register pcieLastCycle
  reg pcieLastCycle;
  wire pcieLastCycle$D_IN, pcieLastCycle$EN;

  // register readConverter_buffer
  reg [511 : 0] readConverter_buffer;
  wire [511 : 0] readConverter_buffer$D_IN;
  wire readConverter_buffer$EN;

  // register readConverter_bufferEmpty
  reg readConverter_bufferEmpty;
  wire readConverter_bufferEmpty$D_IN, readConverter_bufferEmpty$EN;

  // register readConverter_byteCntr
  reg [63 : 0] readConverter_byteCntr;
  wire [63 : 0] readConverter_byteCntr$D_IN;
  wire readConverter_byteCntr$EN;

  // register readConverter_wordInCntr
  reg readConverter_wordInCntr;
  wire readConverter_wordInCntr$D_IN, readConverter_wordInCntr$EN;

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  // register readIn_rv
  reg [192 : 0] readIn_rv;
  wire [192 : 0] readIn_rv$D_IN;
  wire readIn_rv$EN;

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  // register read_requests
  reg [63 : 0] read_requests;
  wire [63 : 0] read_requests$D_IN;
  wire read_requests$EN;

  // register s_config_readBusy
  reg s_config_readBusy;
  wire s_config_readBusy$D_IN, s_config_readBusy$EN;

  // register s_config_writeSlave_addrIn_rv
  reg [67 : 0] s_config_writeSlave_addrIn_rv;
  wire [67 : 0] s_config_writeSlave_addrIn_rv$D_IN;
  wire s_config_writeSlave_addrIn_rv$EN;

  // register s_config_writeSlave_dataIn_rv
  reg [72 : 0] s_config_writeSlave_dataIn_rv;
  wire [72 : 0] s_config_writeSlave_dataIn_rv$D_IN;
  wire s_config_writeSlave_dataIn_rv$EN;

  // register transfer_length
  reg [63 : 0] transfer_length;
  wire [63 : 0] transfer_length$D_IN;
  wire transfer_length$EN;

  // register writeConverter_buffer_0
  reg [255 : 0] writeConverter_buffer_0;
  wire [255 : 0] writeConverter_buffer_0$D_IN;
  wire writeConverter_buffer_0$EN;

  // register writeConverter_byteCntr
  reg [63 : 0] writeConverter_byteCntr;
  wire [63 : 0] writeConverter_byteCntr$D_IN;
  wire writeConverter_byteCntr$EN;

  // register writeConverter_wordInCntr
  reg [1 : 0] writeConverter_wordInCntr;
  wire [1 : 0] writeConverter_wordInCntr$D_IN;
  wire writeConverter_wordInCntr$EN;

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  // register writeIn_rv
  reg [192 : 0] writeIn_rv;
  wire [192 : 0] writeIn_rv$D_IN;
  wire writeIn_rv$EN;

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  // register write_requests
  reg [63 : 0] write_requests;
  wire [63 : 0] write_requests$D_IN;
  wire write_requests$EN;

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  // ports of submodule byteAlignerReader_addr_ff
  wire [191 : 0] byteAlignerReader_addr_ff$dD_OUT,
		 byteAlignerReader_addr_ff$sD_IN;
  wire byteAlignerReader_addr_ff$dDEQ,
       byteAlignerReader_addr_ff$dEMPTY_N,
       byteAlignerReader_addr_ff$sENQ;

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  // ports of submodule byteAlignerReader_incoming
  wire [255 : 0] byteAlignerReader_incoming$D_IN,
		 byteAlignerReader_incoming$D_OUT;
  wire byteAlignerReader_incoming$CLR,
       byteAlignerReader_incoming$DEQ,
       byteAlignerReader_incoming$EMPTY_N,
       byteAlignerReader_incoming$ENQ;

  // ports of submodule byteAlignerReader_outgoing
  wire [255 : 0] byteAlignerReader_outgoing$D_IN;
  wire byteAlignerReader_outgoing$CLR,
       byteAlignerReader_outgoing$DEQ,
       byteAlignerReader_outgoing$ENQ,
       byteAlignerReader_outgoing$FULL_N;

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  // ports of submodule byteAlignerWriter_addr_ff
  wire [191 : 0] byteAlignerWriter_addr_ff$dD_OUT,
		 byteAlignerWriter_addr_ff$sD_IN;
  wire byteAlignerWriter_addr_ff$dDEQ,
       byteAlignerWriter_addr_ff$dEMPTY_N,
       byteAlignerWriter_addr_ff$sENQ;

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  // ports of submodule byteAlignerWriter_incoming
  wire [255 : 0] byteAlignerWriter_incoming$D_IN,
		 byteAlignerWriter_incoming$D_OUT;
  wire byteAlignerWriter_incoming$CLR,
       byteAlignerWriter_incoming$DEQ,
       byteAlignerWriter_incoming$EMPTY_N,
       byteAlignerWriter_incoming$ENQ;

  // ports of submodule byteAlignerWriter_outgoing
  wire [255 : 0] byteAlignerWriter_outgoing$D_IN;
  wire byteAlignerWriter_outgoing$CLR,
       byteAlignerWriter_outgoing$DEQ,
       byteAlignerWriter_outgoing$ENQ,
       byteAlignerWriter_outgoing$FULL_N;

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  // ports of submodule cmdsIn
  wire cmdsIn$CLR,
       cmdsIn$DEQ,
       cmdsIn$D_IN,
       cmdsIn$D_OUT,
       cmdsIn$EMPTY_N,
       cmdsIn$ENQ,
       cmdsIn$FULL_N;

  // ports of submodule fpgaDone
  wire fpgaDone$dDEQ,
       fpgaDone$dEMPTY_N,
       fpgaDone$sD_IN,
       fpgaDone$sENQ,
       fpgaDone$sFULL_N;

  // ports of submodule fpga_request_converter
  wire [511 : 0] fpga_request_converter$dD_OUT, fpga_request_converter$sD_IN;
  wire fpga_request_converter$dDEQ,
       fpga_request_converter$dEMPTY_N,
       fpga_request_converter$sENQ,
       fpga_request_converter$sFULL_N;

  // ports of submodule fpga_response_converter
  wire [511 : 0] fpga_response_converter$dD_OUT,
		 fpga_response_converter$sD_IN;
  wire fpga_response_converter$dDEQ,
       fpga_response_converter$dEMPTY_N,
       fpga_response_converter$sENQ,
       fpga_response_converter$sFULL_N;

  // ports of submodule m_fpga_rd_master_rd_in
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  wire [94 : 0] m_fpga_rd_master_rd_in$D_IN, m_fpga_rd_master_rd_in$D_OUT;
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  wire m_fpga_rd_master_rd_in$CLR,
       m_fpga_rd_master_rd_in$DEQ,
       m_fpga_rd_master_rd_in$EMPTY_N,
       m_fpga_rd_master_rd_in$ENQ,
       m_fpga_rd_master_rd_in$FULL_N;

  // ports of submodule m_fpga_rd_master_rd_out
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  wire [516 : 0] m_fpga_rd_master_rd_out$D_IN, m_fpga_rd_master_rd_out$D_OUT;
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  wire m_fpga_rd_master_rd_out$CLR,
       m_fpga_rd_master_rd_out$DEQ,
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       m_fpga_rd_master_rd_out$EMPTY_N,
       m_fpga_rd_master_rd_out$ENQ,
       m_fpga_rd_master_rd_out$FULL_N;

  // ports of submodule m_fpga_rd_outgoingBuffer
  wire [511 : 0] m_fpga_rd_outgoingBuffer$D_IN,
		 m_fpga_rd_outgoingBuffer$D_OUT;
  wire m_fpga_rd_outgoingBuffer$CLR,
       m_fpga_rd_outgoingBuffer$DEQ,
       m_fpga_rd_outgoingBuffer$EMPTY_N,
       m_fpga_rd_outgoingBuffer$ENQ,
       m_fpga_rd_outgoingBuffer$FULL_N;
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  // ports of submodule m_fpga_rd_reqGen_incomingBuffer
  wire [131 : 0] m_fpga_rd_reqGen_incomingBuffer$D_IN,
		 m_fpga_rd_reqGen_incomingBuffer$D_OUT;
  wire m_fpga_rd_reqGen_incomingBuffer$CLR,
       m_fpga_rd_reqGen_incomingBuffer$DEQ,
       m_fpga_rd_reqGen_incomingBuffer$EMPTY_N,
       m_fpga_rd_reqGen_incomingBuffer$ENQ,
       m_fpga_rd_reqGen_incomingBuffer$FULL_N;

  // ports of submodule m_fpga_rd_reqGen_intermediateBuffer
  wire [143 : 0] m_fpga_rd_reqGen_intermediateBuffer$D_IN,
		 m_fpga_rd_reqGen_intermediateBuffer$D_OUT;
  wire m_fpga_rd_reqGen_intermediateBuffer$CLR,
       m_fpga_rd_reqGen_intermediateBuffer$DEQ,
       m_fpga_rd_reqGen_intermediateBuffer$EMPTY_N,
       m_fpga_rd_reqGen_intermediateBuffer$ENQ,
       m_fpga_rd_reqGen_intermediateBuffer$FULL_N;

  // ports of submodule m_fpga_rd_reqGen_intermediateBuffer2
  wire [201 : 0] m_fpga_rd_reqGen_intermediateBuffer2$D_IN,
		 m_fpga_rd_reqGen_intermediateBuffer2$D_OUT;
  wire m_fpga_rd_reqGen_intermediateBuffer2$CLR,
       m_fpga_rd_reqGen_intermediateBuffer2$DEQ,
       m_fpga_rd_reqGen_intermediateBuffer2$EMPTY_N,
       m_fpga_rd_reqGen_intermediateBuffer2$ENQ,
       m_fpga_rd_reqGen_intermediateBuffer2$FULL_N;

  // ports of submodule m_fpga_rd_reqGen_outgoingBuffer
  wire [210 : 0] m_fpga_rd_reqGen_outgoingBuffer$D_IN,
		 m_fpga_rd_reqGen_outgoingBuffer$D_OUT;
  wire m_fpga_rd_reqGen_outgoingBuffer$CLR,
       m_fpga_rd_reqGen_outgoingBuffer$DEQ,
       m_fpga_rd_reqGen_outgoingBuffer$EMPTY_N,
       m_fpga_rd_reqGen_outgoingBuffer$ENQ,
       m_fpga_rd_reqGen_outgoingBuffer$FULL_N;

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  // ports of submodule m_fpga_wr_beatsPerRequestFIFO
  wire [7 : 0] m_fpga_wr_beatsPerRequestFIFO$D_IN,
	       m_fpga_wr_beatsPerRequestFIFO$D_OUT;
  wire m_fpga_wr_beatsPerRequestFIFO$CLR,
       m_fpga_wr_beatsPerRequestFIFO$DEQ,
       m_fpga_wr_beatsPerRequestFIFO$EMPTY_N,
       m_fpga_wr_beatsPerRequestFIFO$ENQ,
       m_fpga_wr_beatsPerRequestFIFO$FULL_N;
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  // ports of submodule m_fpga_wr_incomingBuffer
  wire [511 : 0] m_fpga_wr_incomingBuffer$D_IN,
		 m_fpga_wr_incomingBuffer$D_OUT;
  wire m_fpga_wr_incomingBuffer$CLR,
       m_fpga_wr_incomingBuffer$DEQ,
       m_fpga_wr_incomingBuffer$EMPTY_N,
       m_fpga_wr_incomingBuffer$ENQ,
       m_fpga_wr_incomingBuffer$FULL_N;

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  // ports of submodule m_fpga_wr_master_wr_in_addr
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  wire [94 : 0] m_fpga_wr_master_wr_in_addr$D_IN,
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		m_fpga_wr_master_wr_in_addr$D_OUT;
  wire m_fpga_wr_master_wr_in_addr$CLR,
       m_fpga_wr_master_wr_in_addr$DEQ,
       m_fpga_wr_master_wr_in_addr$EMPTY_N,
       m_fpga_wr_master_wr_in_addr$ENQ,
       m_fpga_wr_master_wr_in_addr$FULL_N;

  // ports of submodule m_fpga_wr_master_wr_in_data
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  wire [577 : 0] m_fpga_wr_master_wr_in_data$D_IN,
		 m_fpga_wr_master_wr_in_data$D_OUT;
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  wire m_fpga_wr_master_wr_in_data$CLR,
       m_fpga_wr_master_wr_in_data$DEQ,
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       m_fpga_wr_master_wr_in_data$EMPTY_N,
       m_fpga_wr_master_wr_in_data$ENQ,
       m_fpga_wr_master_wr_in_data$FULL_N;
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  // ports of submodule m_fpga_wr_master_wr_out
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  wire [3 : 0] m_fpga_wr_master_wr_out$D_IN;
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  wire m_fpga_wr_master_wr_out$CLR,
       m_fpga_wr_master_wr_out$DEQ,
       m_fpga_wr_master_wr_out$EMPTY_N,
       m_fpga_wr_master_wr_out$ENQ,
       m_fpga_wr_master_wr_out$FULL_N;

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  // ports of submodule m_fpga_wr_reqGen_incomingBuffer
  wire [131 : 0] m_fpga_wr_reqGen_incomingBuffer$D_IN,
		 m_fpga_wr_reqGen_incomingBuffer$D_OUT;
  wire m_fpga_wr_reqGen_incomingBuffer$CLR,
       m_fpga_wr_reqGen_incomingBuffer$DEQ,
       m_fpga_wr_reqGen_incomingBuffer$EMPTY_N,
       m_fpga_wr_reqGen_incomingBuffer$ENQ,
       m_fpga_wr_reqGen_incomingBuffer$FULL_N;

  // ports of submodule m_fpga_wr_reqGen_intermediateBuffer
  wire [143 : 0] m_fpga_wr_reqGen_intermediateBuffer$D_IN,
		 m_fpga_wr_reqGen_intermediateBuffer$D_OUT;
  wire m_fpga_wr_reqGen_intermediateBuffer$CLR,
       m_fpga_wr_reqGen_intermediateBuffer$DEQ,
       m_fpga_wr_reqGen_intermediateBuffer$EMPTY_N,
       m_fpga_wr_reqGen_intermediateBuffer$ENQ,
       m_fpga_wr_reqGen_intermediateBuffer$FULL_N;

  // ports of submodule m_fpga_wr_reqGen_intermediateBuffer2
  wire [201 : 0] m_fpga_wr_reqGen_intermediateBuffer2$D_IN,
		 m_fpga_wr_reqGen_intermediateBuffer2$D_OUT;
  wire m_fpga_wr_reqGen_intermediateBuffer2$CLR,
       m_fpga_wr_reqGen_intermediateBuffer2$DEQ,
       m_fpga_wr_reqGen_intermediateBuffer2$EMPTY_N,
       m_fpga_wr_reqGen_intermediateBuffer2$ENQ,
       m_fpga_wr_reqGen_intermediateBuffer2$FULL_N;

  // ports of submodule m_fpga_wr_reqGen_outgoingBuffer
  wire [210 : 0] m_fpga_wr_reqGen_outgoingBuffer$D_IN,
		 m_fpga_wr_reqGen_outgoingBuffer$D_OUT;
  wire m_fpga_wr_reqGen_outgoingBuffer$CLR,
       m_fpga_wr_reqGen_outgoingBuffer$DEQ,
       m_fpga_wr_reqGen_outgoingBuffer$EMPTY_N,
       m_fpga_wr_reqGen_outgoingBuffer$ENQ,
       m_fpga_wr_reqGen_outgoingBuffer$FULL_N;

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  // ports of submodule m_pcie_rd_master_rd_in
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  wire [94 : 0] m_pcie_rd_master_rd_in$D_IN, m_pcie_rd_master_rd_in$D_OUT;
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  wire m_pcie_rd_master_rd_in$CLR,
       m_pcie_rd_master_rd_in$DEQ,
       m_pcie_rd_master_rd_in$EMPTY_N,
       m_pcie_rd_master_rd_in$ENQ,
       m_pcie_rd_master_rd_in$FULL_N;

  // ports of submodule m_pcie_rd_master_rd_out
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  wire [260 : 0] m_pcie_rd_master_rd_out$D_IN, m_pcie_rd_master_rd_out$D_OUT;
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  wire m_pcie_rd_master_rd_out$CLR,
       m_pcie_rd_master_rd_out$DEQ,
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       m_pcie_rd_master_rd_out$EMPTY_N,
       m_pcie_rd_master_rd_out$ENQ,
       m_pcie_rd_master_rd_out$FULL_N;

  // ports of submodule m_pcie_rd_outgoingBuffer
  wire [255 : 0] m_pcie_rd_outgoingBuffer$D_IN,
		 m_pcie_rd_outgoingBuffer$D_OUT;
  wire m_pcie_rd_outgoingBuffer$CLR,
       m_pcie_rd_outgoingBuffer$DEQ,
       m_pcie_rd_outgoingBuffer$EMPTY_N,
       m_pcie_rd_outgoingBuffer$ENQ,
       m_pcie_rd_outgoingBuffer$FULL_N;
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  // ports of submodule m_pcie_rd_reqGen_incomingBuffer
  wire [131 : 0] m_pcie_rd_reqGen_incomingBuffer$D_IN,
		 m_pcie_rd_reqGen_incomingBuffer$D_OUT;
  wire m_pcie_rd_reqGen_incomingBuffer$CLR,
       m_pcie_rd_reqGen_incomingBuffer$DEQ,
       m_pcie_rd_reqGen_incomingBuffer$EMPTY_N,
       m_pcie_rd_reqGen_incomingBuffer$ENQ,
       m_pcie_rd_reqGen_incomingBuffer$FULL_N;

  // ports of submodule m_pcie_rd_reqGen_intermediateBuffer
  wire [141 : 0] m_pcie_rd_reqGen_intermediateBuffer$D_IN,
		 m_pcie_rd_reqGen_intermediateBuffer$D_OUT;
  wire m_pcie_rd_reqGen_intermediateBuffer$CLR,
       m_pcie_rd_reqGen_intermediateBuffer$DEQ,
       m_pcie_rd_reqGen_intermediateBuffer$EMPTY_N,
       m_pcie_rd_reqGen_intermediateBuffer$ENQ,
       m_pcie_rd_reqGen_intermediateBuffer$FULL_N;

  // ports of submodule m_pcie_rd_reqGen_intermediateBuffer2
  wire [200 : 0] m_pcie_rd_reqGen_intermediateBuffer2$D_IN,
		 m_pcie_rd_reqGen_intermediateBuffer2$D_OUT;
  wire m_pcie_rd_reqGen_intermediateBuffer2$CLR,
       m_pcie_rd_reqGen_intermediateBuffer2$DEQ,
       m_pcie_rd_reqGen_intermediateBuffer2$EMPTY_N,
       m_pcie_rd_reqGen_intermediateBuffer2$ENQ,
       m_pcie_rd_reqGen_intermediateBuffer2$FULL_N;

  // ports of submodule m_pcie_rd_reqGen_outgoingBuffer
  wire [209 : 0] m_pcie_rd_reqGen_outgoingBuffer$D_IN,
		 m_pcie_rd_reqGen_outgoingBuffer$D_OUT;
  wire m_pcie_rd_reqGen_outgoingBuffer$CLR,
       m_pcie_rd_reqGen_outgoingBuffer$DEQ,
       m_pcie_rd_reqGen_outgoingBuffer$EMPTY_N,
       m_pcie_rd_reqGen_outgoingBuffer$ENQ,
       m_pcie_rd_reqGen_outgoingBuffer$FULL_N;

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  // ports of submodule m_pcie_wr_beatsPerRequestFIFO
  wire [7 : 0] m_pcie_wr_beatsPerRequestFIFO$D_IN,
	       m_pcie_wr_beatsPerRequestFIFO$D_OUT;
  wire m_pcie_wr_beatsPerRequestFIFO$CLR,
       m_pcie_wr_beatsPerRequestFIFO$DEQ,
       m_pcie_wr_beatsPerRequestFIFO$EMPTY_N,
       m_pcie_wr_beatsPerRequestFIFO$ENQ,
       m_pcie_wr_beatsPerRequestFIFO$FULL_N;
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  // ports of submodule m_pcie_wr_incomingBuffer
  reg [255 : 0] m_pcie_wr_incomingBuffer$D_IN;
  wire [255 : 0] m_pcie_wr_incomingBuffer$D_OUT;
  wire m_pcie_wr_incomingBuffer$CLR,
       m_pcie_wr_incomingBuffer$DEQ,
       m_pcie_wr_incomingBuffer$EMPTY_N,
       m_pcie_wr_incomingBuffer$ENQ,
       m_pcie_wr_incomingBuffer$FULL_N;

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  // ports of submodule m_pcie_wr_master_wr_in_addr
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  wire [94 : 0] m_pcie_wr_master_wr_in_addr$D_IN,
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		m_pcie_wr_master_wr_in_addr$D_OUT;
  wire m_pcie_wr_master_wr_in_addr$CLR,
       m_pcie_wr_master_wr_in_addr$DEQ,
       m_pcie_wr_master_wr_in_addr$EMPTY_N,
       m_pcie_wr_master_wr_in_addr$ENQ,
       m_pcie_wr_master_wr_in_addr$FULL_N;

  // ports of submodule m_pcie_wr_master_wr_in_data
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  wire [289 : 0] m_pcie_wr_master_wr_in_data$D_IN,
		 m_pcie_wr_master_wr_in_data$D_OUT;
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  wire m_pcie_wr_master_wr_in_data$CLR,
       m_pcie_wr_master_wr_in_data$DEQ,
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       m_pcie_wr_master_wr_in_data$EMPTY_N,
       m_pcie_wr_master_wr_in_data$ENQ,
       m_pcie_wr_master_wr_in_data$FULL_N;
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  // ports of submodule m_pcie_wr_master_wr_out
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  wire [3 : 0] m_pcie_wr_master_wr_out$D_IN;
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  wire m_pcie_wr_master_wr_out$CLR,
       m_pcie_wr_master_wr_out$DEQ,
       m_pcie_wr_master_wr_out$EMPTY_N,
       m_pcie_wr_master_wr_out$ENQ,
       m_pcie_wr_master_wr_out$FULL_N;

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  // ports of submodule m_pcie_wr_reqGen_incomingBuffer
  wire [131 : 0] m_pcie_wr_reqGen_incomingBuffer$D_IN,
		 m_pcie_wr_reqGen_incomingBuffer$D_OUT;
  wire m_pcie_wr_reqGen_incomingBuffer$CLR,
       m_pcie_wr_reqGen_incomingBuffer$DEQ,
       m_pcie_wr_reqGen_incomingBuffer$EMPTY_N,
       m_pcie_wr_reqGen_incomingBuffer$ENQ,
       m_pcie_wr_reqGen_incomingBuffer$FULL_N;

  // ports of submodule m_pcie_wr_reqGen_intermediateBuffer
  wire [141 : 0] m_pcie_wr_reqGen_intermediateBuffer$D_IN,
		 m_pcie_wr_reqGen_intermediateBuffer$D_OUT;
  wire m_pcie_wr_reqGen_intermediateBuffer$CLR,
       m_pcie_wr_reqGen_intermediateBuffer$DEQ,
       m_pcie_wr_reqGen_intermediateBuffer$EMPTY_N,
       m_pcie_wr_reqGen_intermediateBuffer$ENQ,
       m_pcie_wr_reqGen_intermediateBuffer$FULL_N;

  // ports of submodule m_pcie_wr_reqGen_intermediateBuffer2
  wire [200 : 0] m_pcie_wr_reqGen_intermediateBuffer2$D_IN,
		 m_pcie_wr_reqGen_intermediateBuffer2$D_OUT;
  wire m_pcie_wr_reqGen_intermediateBuffer2$CLR,
       m_pcie_wr_reqGen_intermediateBuffer2$DEQ,
       m_pcie_wr_reqGen_intermediateBuffer2$EMPTY_N,
       m_pcie_wr_reqGen_intermediateBuffer2$ENQ,
       m_pcie_wr_reqGen_intermediateBuffer2$FULL_N;

  // ports of submodule m_pcie_wr_reqGen_outgoingBuffer
  wire [209 : 0] m_pcie_wr_reqGen_outgoingBuffer$D_IN,
		 m_pcie_wr_reqGen_outgoingBuffer$D_OUT;
  wire m_pcie_wr_reqGen_outgoingBuffer$CLR,
       m_pcie_wr_reqGen_outgoingBuffer$DEQ,
       m_pcie_wr_reqGen_outgoingBuffer$EMPTY_N,
       m_pcie_wr_reqGen_outgoingBuffer$ENQ,
       m_pcie_wr_reqGen_outgoingBuffer$FULL_N;

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  // ports of submodule mclk_m_fpga_put_req_rd_ff
  wire [131 : 0] mclk_m_fpga_put_req_rd_ff$dD_OUT,
		 mclk_m_fpga_put_req_rd_ff$sD_IN;
  wire mclk_m_fpga_put_req_rd_ff$dDEQ,
       mclk_m_fpga_put_req_rd_ff$dEMPTY_N,
       mclk_m_fpga_put_req_rd_ff$sENQ,
       mclk_m_fpga_put_req_rd_ff$sFULL_N;

  // ports of submodule mclk_m_fpga_put_req_wr_ff
  wire [131 : 0] mclk_m_fpga_put_req_wr_ff$dD_OUT,
		 mclk_m_fpga_put_req_wr_ff$sD_IN;
  wire mclk_m_fpga_put_req_wr_ff$dDEQ,
       mclk_m_fpga_put_req_wr_ff$dEMPTY_N,
       mclk_m_fpga_put_req_wr_ff$sENQ,
       mclk_m_fpga_put_req_wr_ff$sFULL_N;

  // ports of submodule mclk_m_pcie_put_req_rd_ff
  wire [131 : 0] mclk_m_pcie_put_req_rd_ff$dD_OUT,
		 mclk_m_pcie_put_req_rd_ff$sD_IN;
  wire mclk_m_pcie_put_req_rd_ff$dDEQ,
       mclk_m_pcie_put_req_rd_ff$dEMPTY_N,
       mclk_m_pcie_put_req_rd_ff$sENQ,
       mclk_m_pcie_put_req_rd_ff$sFULL_N;

  // ports of submodule mclk_m_pcie_put_req_wr_ff
  wire [131 : 0] mclk_m_pcie_put_req_wr_ff$dD_OUT,
		 mclk_m_pcie_put_req_wr_ff$sD_IN;
  wire mclk_m_pcie_put_req_wr_ff$dDEQ,
       mclk_m_pcie_put_req_wr_ff$dEMPTY_N,
       mclk_m_pcie_put_req_wr_ff$sENQ,
       mclk_m_pcie_put_req_wr_ff$sFULL_N;

  // ports of submodule pcieDone
  wire pcieDone$dDEQ,
       pcieDone$dEMPTY_N,
       pcieDone$sD_IN,
       pcieDone$sENQ,
       pcieDone$sFULL_N;

  // ports of submodule readConvBTT_ff
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  wire [64 : 0] readConvBTT_ff$dD_OUT, readConvBTT_ff$sD_IN;
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  wire readConvBTT_ff$dDEQ,
       readConvBTT_ff$dEMPTY_N,
       readConvBTT_ff$sENQ,
       readConvBTT_ff$sFULL_N;

  // ports of submodule s_config_readSlave_in
  wire [66 : 0] s_config_readSlave_in$D_IN, s_config_readSlave_in$D_OUT;
  wire s_config_readSlave_in$CLR,
       s_config_readSlave_in$DEQ,
       s_config_readSlave_in$EMPTY_N,
       s_config_readSlave_in$ENQ,
       s_config_readSlave_in$FULL_N;

  // ports of submodule s_config_readSlave_out
  reg [65 : 0] s_config_readSlave_out$D_IN;
  wire [65 : 0] s_config_readSlave_out$D_OUT;
  wire s_config_readSlave_out$CLR,
       s_config_readSlave_out$DEQ,
       s_config_readSlave_out$EMPTY_N,
       s_config_readSlave_out$ENQ,
       s_config_readSlave_out$FULL_N;

  // ports of submodule s_config_writeSlave_in
  wire [138 : 0] s_config_writeSlave_in$D_IN, s_config_writeSlave_in$D_OUT;
  wire s_config_writeSlave_in$CLR,
       s_config_writeSlave_in$DEQ,
       s_config_writeSlave_in$EMPTY_N,
       s_config_writeSlave_in$ENQ,
       s_config_writeSlave_in$FULL_N;

  // ports of submodule s_config_writeSlave_out
  wire [1 : 0] s_config_writeSlave_out$D_IN, s_config_writeSlave_out$D_OUT;
  wire s_config_writeSlave_out$CLR,
       s_config_writeSlave_out$DEQ,
       s_config_writeSlave_out$EMPTY_N,
       s_config_writeSlave_out$ENQ,
       s_config_writeSlave_out$FULL_N;

  // ports of submodule writeConvBTT_ff
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  wire [64 : 0] writeConvBTT_ff$dD_OUT, writeConvBTT_ff$sD_IN;
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  wire writeConvBTT_ff$dDEQ,
       writeConvBTT_ff$dEMPTY_N,
       writeConvBTT_ff$sENQ,
       writeConvBTT_ff$sFULL_N;

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  // ports of submodule writeConverter_dataSync
  wire [511 : 0] writeConverter_dataSync$D_IN, writeConverter_dataSync$D_OUT;
  wire writeConverter_dataSync$CLR,
       writeConverter_dataSync$DEQ,
       writeConverter_dataSync$EMPTY_N,
       writeConverter_dataSync$ENQ,
       writeConverter_dataSync$FULL_N;

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  // rule scheduling signals
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  wire CAN_FIRE_RL_byteAlignerReader_forwardOutputLast,
       CAN_FIRE_RL_byteAlignerWriter_forwardOutputLast,
       CAN_FIRE_RL_handleRead,
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       WILL_FIRE_RL_byteAlignerReader_fetchNewData,
       WILL_FIRE_RL_byteAlignerReader_forwardOutput,
       WILL_FIRE_RL_byteAlignerReader_forwardOutputLast,
       WILL_FIRE_RL_byteAlignerWriter_fetchNewData,
       WILL_FIRE_RL_byteAlignerWriter_forwardOutput,
       WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast,
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       WILL_FIRE_RL_handleRead,
       WILL_FIRE_RL_handleWrite,
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       WILL_FIRE_RL_m_fpga_rd_fillBuffer,
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       WILL_FIRE_RL_m_fpga_rd_forwardData,
       WILL_FIRE_RL_m_fpga_rd_placeRequest,
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       WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest,
       WILL_FIRE_RL_m_fpga_wr_fillBuffer,
       WILL_FIRE_RL_m_fpga_wr_forwardData,
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       WILL_FIRE_RL_m_fpga_wr_placeRequest,
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       WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest,
       WILL_FIRE_RL_m_pcie_rd_fillBuffer,
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       WILL_FIRE_RL_m_pcie_rd_forwardData,
       WILL_FIRE_RL_m_pcie_rd_placeRequest,
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       WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest,
       WILL_FIRE_RL_m_pcie_wr_fillBuffer,
       WILL_FIRE_RL_m_pcie_wr_forwardData,
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       WILL_FIRE_RL_m_pcie_wr_placeRequest,
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       WILL_FIRE_RL_m_pcie_wr_reqGen_finishRequest,
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       WILL_FIRE_RL_mkConnectionGetPut_1,
       WILL_FIRE_RL_mkConnectionGetPut_2,
       WILL_FIRE_RL_mkConnectionGetPut_3,
       WILL_FIRE_RL_s_config_1_axiWriteFallback,
       WILL_FIRE_RL_s_config_1_axiWriteSpecial,
       WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled,
       WILL_FIRE_RL_s_config_1_axiWriteSpecial_1,
       WILL_FIRE_RL_s_config_1_axiWriteSpecial_2,
       WILL_FIRE_RL_s_config_1_axiWriteSpecial_3,
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       WILL_FIRE_RL_s_config_1_axiWriteSpecial_4,
       WILL_FIRE_RL_s_config_1_axiWriteSpecial_5,
       WILL_FIRE_RL_s_config_1_axiWriteSpecial_6,
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       WILL_FIRE_RL_s_config_axiReadFallback,
       WILL_FIRE_RL_s_config_axiReadSpecial,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_5,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7,
       WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8,
       WILL_FIRE_RL_s_config_axiReadSpecial_1,
       WILL_FIRE_RL_s_config_axiReadSpecial_2,
       WILL_FIRE_RL_s_config_axiReadSpecial_3,
       WILL_FIRE_RL_s_config_axiReadSpecial_4,
       WILL_FIRE_RL_s_config_axiReadSpecial_5,
       WILL_FIRE_RL_s_config_axiReadSpecial_6,
       WILL_FIRE_RL_s_config_axiReadSpecial_7,
       WILL_FIRE_RL_s_config_axiReadSpecial_8,
       WILL_FIRE_RL_setInterrupt;

  // inputs to muxes for submodule ports
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  wire [511 : 0] MUX_byteAlignerReader_buffer$port0__write_1__VAL_1,
		 MUX_byteAlignerWriter_buffer$port0__write_1__VAL_1;
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  wire [134 : 0] MUX_m_pcie_rd_task_data_requests_reg$write_1__VAL_1,
		 MUX_m_pcie_wr_task_data_requests_reg$write_1__VAL_1;
  wire [133 : 0] MUX_m_fpga_rd_task_data_requests_reg$write_1__VAL_1,
		 MUX_m_fpga_wr_task_data_requests_reg$write_1__VAL_1;
  wire [76 : 0] MUX_m_fpga_rd_task_data_output_reg$write_1__VAL_1,
		MUX_m_fpga_wr_task_data_output_reg$write_1__VAL_1;
  wire [74 : 0] MUX_m_pcie_rd_task_data_output_reg$write_1__VAL_1,
		MUX_m_pcie_wr_task_data_output_reg$write_1__VAL_1;
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  wire [65 : 0] MUX_s_config_readSlave_out$enq_1__VAL_1,
		MUX_s_config_readSlave_out$enq_1__VAL_2,
		MUX_s_config_readSlave_out$enq_1__VAL_3,
		MUX_s_config_readSlave_out$enq_1__VAL_4,
		MUX_s_config_readSlave_out$enq_1__VAL_5,
		MUX_s_config_readSlave_out$enq_1__VAL_6,
		MUX_s_config_readSlave_out$enq_1__VAL_7,
		MUX_s_config_readSlave_out$enq_1__VAL_8,
		MUX_s_config_readSlave_out$enq_1__VAL_9;
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  wire [63 : 0] MUX_byteAlignerReader_bytes_in$write_1__VAL_1,
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		MUX_byteAlignerReader_bytes_out$write_1__VAL_1,
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		MUX_byteAlignerReader_bytes_out$write_1__VAL_2,
		MUX_byteAlignerWriter_bytes_in$write_1__VAL_1,
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		MUX_byteAlignerWriter_bytes_out$write_1__VAL_1,
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		MUX_byteAlignerWriter_bytes_out$write_1__VAL_2,
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		MUX_cycles_between$write_1__VAL_1,
		MUX_cycles_between$write_1__VAL_2,
		MUX_cycles_last_request$write_1__VAL_1,
		MUX_cycles_last_request$write_1__VAL_2,
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		MUX_readConverter_byteCntr$write_1__VAL_2,
		MUX_writeConverter_byteCntr$write_1__VAL_2;
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  wire [7 : 0] MUX_m_fpga_wr_beatsThisRequestCntr$write_1__VAL_1,
	       MUX_m_pcie_wr_beatsThisRequestCntr$write_1__VAL_1;
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  wire [5 : 0] MUX_byteAlignerReader_bytes_left_in_buffer$port0__write_1__VAL_1,
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	       MUX_byteAlignerReader_bytes_out_needed$write_1__VAL_1,
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	       MUX_byteAlignerWriter_bytes_left_in_buffer$port0__write_1__VAL_1,
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	       MUX_byteAlignerWriter_bytes_out_needed$write_1__VAL_1;
  wire [1 : 0] MUX_writeConverter_wordInCntr$write_1__VAL_1,
	       MUX_writeConverter_wordInCntr$write_1__VAL_2;
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  wire MUX_cycles_between$write_1__SEL_1, MUX_opInProgress$write_1__SEL_2;
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  // remaining internal signals
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  reg [3 : 0] CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q5,
	      CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q4,
	      CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q3,
	      CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q2;
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  wire [63 : 0] _theResult____h26331,
		_theResult____h26515,
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		_theResult____h36285,
		_theResult____h36469,
		_theResult____h40174,
		_theResult____h40358,
		_theResult____h55521,
		_theResult____h55705,
		btt__h102089,
		btt__h145195,
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		bytes_first___1__h26366,
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		bytes_first___1__h36320,
		bytes_first___1__h40209,
		bytes_first___1__h55556,
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		bytes_first__h26330,
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		bytes_first__h36284,
		bytes_first__h40173,
		bytes_first__h55520,
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		m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6,
		m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7,
		m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8,
		m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9,
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		request_data_address__h26655,
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		request_data_address__h36609,
		request_data_address__h40498,
		request_data_address__h55845,
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		transfers_total___1__h26523,
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		transfers_total___1__h36477,
		transfers_total___1__h40366,
		transfers_total___1__h55713,
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		transfers_total__h26514,
		transfers_total__h26520,
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		transfers_total__h36468,
		transfers_total__h36474,
		transfers_total__h40357,
		transfers_total__h40363,
		transfers_total__h55704,
		transfers_total__h55710,
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		x__h26336,
		x__h26517,
		x__h26543,
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		x__h36290,
		x__h36471,
		x__h36497,
		x__h40179,
		x__h40360,
		x__h40386,
		x__h55526,
		x__h55707,
		x__h55733,
		x_address__h29577,
		x_address__h38734,
		x_address__h43405,
		x_address__h57967,
		x_strb__h43921,
		y__h102126,
		y__h145223,
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		y__h26410,
		y__h26544,
		y__h26546,
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		y__h36364,
		y__h36498,
		y__h36500,
		y__h40253,
		y__h40387,
		y__h40389,
		y__h55600,
		y__h55734,
		y__h55736;
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  wire [58 : 0] request_data_requests_total__h26654,
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		request_data_requests_total__h36608,
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		requests_total___1__h26680,
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		requests_total___1__h36634,
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		requests_total__h26618,
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		requests_total__h36572,
		x_requests_total__h29576,
		x_requests_total__h38733,
		x_transfers_total__h35603,
		x_transfers_total__h39183;
  wire [57 : 0] request_data_requests_total__h40497,
		request_data_requests_total__h55844,
		requests_total___1__h40523,
		requests_total___1__h55870,
		requests_total__h40461,
		requests_total__h55808,
		x_requests_total__h43404,
		x_requests_total__h57966,
		x_transfers_total__h54839,
		x_transfers_total__h58416;
  wire [31 : 0] x_strb__h30093;
  wire [7 : 0] _theResult____h29471,
	       _theResult____h43299,
	       beatsThisRequestCntrT__h29979,
	       beatsThisRequestCntrT__h43807,
	       beatsThisRequest___1__h29519,
	       beatsThisRequest___1__h38705,
	       beatsThisRequest___1__h43347,
	       beatsThisRequest___1__h57938,
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	       requests_last__h26617,
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	       requests_last__h36571;
  wire [6 : 0] IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950,
	       endByte___1__h46830,
	       endByte___1__h46856,
	       startByte___1__h46829,
	       x__h46816;
  wire [5 : 0] IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465,
	       b__h115475,
	       b__h72292,
	       endByte___1__h31594,
	       endByte___1__h31620,
	       startByte___1__h31593,
	       x__h31580;
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  wire [1 : 0] IF_0_CONCAT_readConverter_wordInCntr_EQ_1_OR_r_ETC__q1;
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  wire byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440,
       byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455,
       byteAlignerWriter_bytes_in_560_ULT_byteAligner_ETC___d1562,
       byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1577,
       fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672,
       m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929,
       m_pcie_wr_beatsThisRequestCntr_42_EQ_m_pcie_wr_ETC___d444,
       pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681,
       pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665;
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  // value method s_rd_arready
  assign S_AXI_arready = s_config_readSlave_in$FULL_N ;

  // value method s_rd_rvalid
  assign S_AXI_rvalid = s_config_readSlave_out$EMPTY_N ;

  // value method s_rd_rdata
  assign S_AXI_rdata =
	     s_config_readSlave_out$EMPTY_N ?
	       s_config_readSlave_out$D_OUT[65:2] :
	       64'd0 ;

  // value method s_rd_rresp
  assign S_AXI_rresp =
	     s_config_readSlave_out$EMPTY_N ?
	       s_config_readSlave_out$D_OUT[1:0] :
	       2'd0 ;

  // value method s_wr_awready
  assign S_AXI_awready = !s_config_writeSlave_addrIn_rv[67] ;

  // value method s_wr_wready
  assign S_AXI_wready = !s_config_writeSlave_dataIn_rv[72] ;

  // value method s_wr_bvalid
  assign S_AXI_bvalid = s_config_writeSlave_out$EMPTY_N ;

  // value method s_wr_bresp
  assign S_AXI_bresp =
	     s_config_writeSlave_out$EMPTY_N ?
	       s_config_writeSlave_out$D_OUT :
	       2'd0 ;

  // value method pcie_rd_arvalid
  assign pcie_rd_arvalid = m_pcie_rd_master_rd_in$EMPTY_N ;

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  // value method pcie_rd_arid
  assign pcie_rd_arid =
	     m_pcie_rd_master_rd_in$EMPTY_N &&
	     m_pcie_rd_master_rd_in$D_OUT[94] ;

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  // value method pcie_rd_araddr
  assign pcie_rd_araddr =
	     m_pcie_rd_master_rd_in$EMPTY_N ?
	       m_pcie_rd_master_rd_in$D_OUT[93:30] :
	       64'd0 ;

  // value method pcie_rd_arlen
  assign pcie_rd_arlen =
	     m_pcie_rd_master_rd_in$EMPTY_N ?
	       m_pcie_rd_master_rd_in$D_OUT[29:22] :
	       8'd0 ;

  // value method pcie_rd_arsize
  assign pcie_rd_arsize =
	     m_pcie_rd_master_rd_in$EMPTY_N ?
	       m_pcie_rd_master_rd_in$D_OUT[21:19] :
	       3'd0 ;

  // value method pcie_rd_arburst
  assign pcie_rd_arburst =
	     m_pcie_rd_master_rd_in$EMPTY_N ?
	       m_pcie_rd_master_rd_in$D_OUT[18:17] :
	       2'd0 ;

  // value method pcie_rd_arlock
  assign pcie_rd_arlock =
	     m_pcie_rd_master_rd_in$EMPTY_N &&
	     m_pcie_rd_master_rd_in$D_OUT[16] ;

  // value method pcie_rd_arcache
  assign pcie_rd_arcache =
	     (!m_pcie_rd_master_rd_in$EMPTY_N ||
	      m_pcie_rd_master_rd_warcache$wget == 4'd0) ?
	       4'd0 :
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	       CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q3 ;
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  // value method pcie_rd_arprot
  assign pcie_rd_arprot =
	     m_pcie_rd_master_rd_in$EMPTY_N ?
	       m_pcie_rd_master_rd_in$D_OUT[11:9] :
	       3'd0 ;

  // value method pcie_rd_arqos
  assign pcie_rd_arqos =
	     m_pcie_rd_master_rd_in$EMPTY_N ?
	       m_pcie_rd_master_rd_in$D_OUT[8:5] :
	       4'd0 ;

  // value method pcie_rd_arregion
  assign pcie_rd_arregion =
	     m_pcie_rd_master_rd_in$EMPTY_N ?
	       m_pcie_rd_master_rd_in$D_OUT[4:1] :
	       4'd0 ;

  // value method pcie_rd_aruser
  assign pcie_rd_aruser =
	     m_pcie_rd_master_rd_in$EMPTY_N &&
	     m_pcie_rd_master_rd_in$D_OUT[0] ;

  // value method pcie_rd_rready
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  assign pcie_rd_rready = m_pcie_rd_master_rd_out$FULL_N ;
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  // value method pcie_wr_awvalid
  assign pcie_wr_awvalid = m_pcie_wr_master_wr_in_addr$EMPTY_N ;

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  // value method pcie_wr_awid
  assign pcie_wr_awid =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N &&
	     m_pcie_wr_master_wr_in_addr$D_OUT[94] ;

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  // value method pcie_wr_awaddr
  assign pcie_wr_awaddr =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N ?
	       m_pcie_wr_master_wr_in_addr$D_OUT[93:30] :
	       64'd0 ;

  // value method pcie_wr_awlen
  assign pcie_wr_awlen =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N ?
	       m_pcie_wr_master_wr_in_addr$D_OUT[29:22] :
	       8'd0 ;

  // value method pcie_wr_awsize
  assign pcie_wr_awsize =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N ?
	       m_pcie_wr_master_wr_in_addr$D_OUT[21:19] :
	       3'd0 ;

  // value method pcie_wr_awburst
  assign pcie_wr_awburst =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N ?
	       m_pcie_wr_master_wr_in_addr$D_OUT[18:17] :
	       2'd0 ;

  // value method pcie_wr_awlock
  assign pcie_wr_awlock =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N &&
	     m_pcie_wr_master_wr_in_addr$D_OUT[16] ;

  // value method pcie_wr_awcache
  assign pcie_wr_awcache =
	     (!m_pcie_wr_master_wr_in_addr$EMPTY_N ||
	      m_pcie_wr_master_wr_wawcache$wget == 4'd0) ?
	       4'd0 :
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	       CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q2 ;
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  // value method pcie_wr_awprot
  assign pcie_wr_awprot =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N ?
	       m_pcie_wr_master_wr_in_addr$D_OUT[11:9] :
	       3'd0 ;

  // value method pcie_wr_awqos
  assign pcie_wr_awqos =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N ?
	       m_pcie_wr_master_wr_in_addr$D_OUT[8:5] :
	       4'd0 ;

  // value method pcie_wr_awregion
  assign pcie_wr_awregion =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N ?
	       m_pcie_wr_master_wr_in_addr$D_OUT[4:1] :
	       4'd0 ;

  // value method pcie_wr_awuser
  assign pcie_wr_awuser =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N &&
	     m_pcie_wr_master_wr_in_addr$D_OUT[0] ;

  // value method pcie_wr_wvalid
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  assign pcie_wr_wvalid = m_pcie_wr_master_wr_in_data$EMPTY_N ;
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  // value method pcie_wr_wdata
  assign pcie_wr_wdata =
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	     m_pcie_wr_master_wr_in_data$EMPTY_N ?
	       m_pcie_wr_master_wr_in_data$D_OUT[289:34] :
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	       256'd0 ;

  // value method pcie_wr_wstrb
  assign pcie_wr_wstrb =
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	     m_pcie_wr_master_wr_in_data$EMPTY_N ?
	       m_pcie_wr_master_wr_in_data$D_OUT[33:2] :
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	       32'd0 ;

  // value method pcie_wr_wlast
  assign pcie_wr_wlast =
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	     m_pcie_wr_master_wr_in_data$EMPTY_N &&
	     m_pcie_wr_master_wr_in_data$D_OUT[1] ;
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  // value method pcie_wr_wuser
  assign pcie_wr_wuser =
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	     m_pcie_wr_master_wr_in_data$EMPTY_N &&
	     m_pcie_wr_master_wr_in_data$D_OUT[0] ;
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