mkBlueDMA.v 264 KB
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  // value method pcie_wr_bready
  assign pcie_wr_bready = m_pcie_wr_master_wr_out$FULL_N ;

  // value method fpga_rd_arvalid
  assign fpga_rd_arvalid = m_fpga_rd_master_rd_in$EMPTY_N ;

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  // value method fpga_rd_arid
  assign fpga_rd_arid =
	     m_fpga_rd_master_rd_in$EMPTY_N &&
	     m_fpga_rd_master_rd_in$D_OUT[94] ;

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  // value method fpga_rd_araddr
  assign fpga_rd_araddr =
	     m_fpga_rd_master_rd_in$EMPTY_N ?
	       m_fpga_rd_master_rd_in$D_OUT[93:30] :
	       64'd0 ;

  // value method fpga_rd_arlen
  assign fpga_rd_arlen =
	     m_fpga_rd_master_rd_in$EMPTY_N ?
	       m_fpga_rd_master_rd_in$D_OUT[29:22] :
	       8'd0 ;

  // value method fpga_rd_arsize
  assign fpga_rd_arsize =
	     m_fpga_rd_master_rd_in$EMPTY_N ?
	       m_fpga_rd_master_rd_in$D_OUT[21:19] :
	       3'd0 ;

  // value method fpga_rd_arburst
  assign fpga_rd_arburst =
	     m_fpga_rd_master_rd_in$EMPTY_N ?
	       m_fpga_rd_master_rd_in$D_OUT[18:17] :
	       2'd0 ;

  // value method fpga_rd_arlock
  assign fpga_rd_arlock =
	     m_fpga_rd_master_rd_in$EMPTY_N &&
	     m_fpga_rd_master_rd_in$D_OUT[16] ;

  // value method fpga_rd_arcache
  assign fpga_rd_arcache =
	     (!m_fpga_rd_master_rd_in$EMPTY_N ||
	      m_fpga_rd_master_rd_warcache$wget == 4'd0) ?
	       4'd0 :
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	       CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q5 ;
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  // value method fpga_rd_arprot
  assign fpga_rd_arprot =
	     m_fpga_rd_master_rd_in$EMPTY_N ?
	       m_fpga_rd_master_rd_in$D_OUT[11:9] :
	       3'd0 ;

  // value method fpga_rd_arqos
  assign fpga_rd_arqos =
	     m_fpga_rd_master_rd_in$EMPTY_N ?
	       m_fpga_rd_master_rd_in$D_OUT[8:5] :
	       4'd0 ;

  // value method fpga_rd_arregion
  assign fpga_rd_arregion =
	     m_fpga_rd_master_rd_in$EMPTY_N ?
	       m_fpga_rd_master_rd_in$D_OUT[4:1] :
	       4'd0 ;

  // value method fpga_rd_aruser
  assign fpga_rd_aruser =
	     m_fpga_rd_master_rd_in$EMPTY_N &&
	     m_fpga_rd_master_rd_in$D_OUT[0] ;

  // value method fpga_rd_rready
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  assign fpga_rd_rready = m_fpga_rd_master_rd_out$FULL_N ;
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  // value method fpga_wr_awvalid
  assign fpga_wr_awvalid = m_fpga_wr_master_wr_in_addr$EMPTY_N ;

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  // value method fpga_wr_awid
  assign fpga_wr_awid =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N &&
	     m_fpga_wr_master_wr_in_addr$D_OUT[94] ;

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  // value method fpga_wr_awaddr
  assign fpga_wr_awaddr =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N ?
	       m_fpga_wr_master_wr_in_addr$D_OUT[93:30] :
	       64'd0 ;

  // value method fpga_wr_awlen
  assign fpga_wr_awlen =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N ?
	       m_fpga_wr_master_wr_in_addr$D_OUT[29:22] :
	       8'd0 ;

  // value method fpga_wr_awsize
  assign fpga_wr_awsize =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N ?
	       m_fpga_wr_master_wr_in_addr$D_OUT[21:19] :
	       3'd0 ;

  // value method fpga_wr_awburst
  assign fpga_wr_awburst =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N ?
	       m_fpga_wr_master_wr_in_addr$D_OUT[18:17] :
	       2'd0 ;

  // value method fpga_wr_awlock
  assign fpga_wr_awlock =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N &&
	     m_fpga_wr_master_wr_in_addr$D_OUT[16] ;

  // value method fpga_wr_awcache
  assign fpga_wr_awcache =
	     (!m_fpga_wr_master_wr_in_addr$EMPTY_N ||
	      m_fpga_wr_master_wr_wawcache$wget == 4'd0) ?
	       4'd0 :
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	       CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q4 ;
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  // value method fpga_wr_awprot
  assign fpga_wr_awprot =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N ?
	       m_fpga_wr_master_wr_in_addr$D_OUT[11:9] :
	       3'd0 ;

  // value method fpga_wr_awqos
  assign fpga_wr_awqos =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N ?
	       m_fpga_wr_master_wr_in_addr$D_OUT[8:5] :
	       4'd0 ;

  // value method fpga_wr_awregion
  assign fpga_wr_awregion =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N ?
	       m_fpga_wr_master_wr_in_addr$D_OUT[4:1] :
	       4'd0 ;

  // value method fpga_wr_awuser
  assign fpga_wr_awuser =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N &&
	     m_fpga_wr_master_wr_in_addr$D_OUT[0] ;

  // value method fpga_wr_wvalid
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  assign fpga_wr_wvalid = m_fpga_wr_master_wr_in_data$EMPTY_N ;
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  // value method fpga_wr_wdata
  assign fpga_wr_wdata =
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	     m_fpga_wr_master_wr_in_data$EMPTY_N ?
	       m_fpga_wr_master_wr_in_data$D_OUT[577:66] :
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	       512'd0 ;

  // value method fpga_wr_wstrb
  assign fpga_wr_wstrb =
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	     m_fpga_wr_master_wr_in_data$EMPTY_N ?
	       m_fpga_wr_master_wr_in_data$D_OUT[65:2] :
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	       64'd0 ;

  // value method fpga_wr_wlast
  assign fpga_wr_wlast =
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	     m_fpga_wr_master_wr_in_data$EMPTY_N &&
	     m_fpga_wr_master_wr_in_data$D_OUT[1] ;
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  // value method fpga_wr_wuser
  assign fpga_wr_wuser =
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	     m_fpga_wr_master_wr_in_data$EMPTY_N &&
	     m_fpga_wr_master_wr_in_data$D_OUT[0] ;
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  // value method fpga_wr_bready
  assign fpga_wr_bready = m_fpga_wr_master_wr_out$FULL_N ;

  // value method interrupt
  assign interrupt = doneInterruptReg ;

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  // submodule byteAlignerReader_addr_ff
  SyncFIFO1 #(.dataWidth(32'd192)) byteAlignerReader_addr_ff(.sCLK(CLK),
							     .dCLK(CLK_m64_axi_aclk),
							     .sRST(RST_N),
							     .sD_IN(byteAlignerReader_addr_ff$sD_IN),
							     .sENQ(byteAlignerReader_addr_ff$sENQ),
							     .dDEQ(byteAlignerReader_addr_ff$dDEQ),
							     .sFULL_N(),
							     .dEMPTY_N(byteAlignerReader_addr_ff$dEMPTY_N),
							     .dD_OUT(byteAlignerReader_addr_ff$dD_OUT));

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  // submodule byteAlignerReader_incoming
  FIFO2 #(.width(32'd256),
	  .guarded(32'd1)) byteAlignerReader_incoming(.RST(RST_N_m64_axi_arestn),
						      .CLK(CLK_m64_axi_aclk),
						      .D_IN(byteAlignerReader_incoming$D_IN),
						      .ENQ(byteAlignerReader_incoming$ENQ),
						      .DEQ(byteAlignerReader_incoming$DEQ),
						      .CLR(byteAlignerReader_incoming$CLR),
						      .D_OUT(byteAlignerReader_incoming$D_OUT),
						      .FULL_N(),
						      .EMPTY_N(byteAlignerReader_incoming$EMPTY_N));

  // submodule byteAlignerReader_outgoing
  FIFO2 #(.width(32'd256),
	  .guarded(32'd1)) byteAlignerReader_outgoing(.RST(RST_N_m64_axi_arestn),
						      .CLK(CLK_m64_axi_aclk),
						      .D_IN(byteAlignerReader_outgoing$D_IN),
						      .ENQ(byteAlignerReader_outgoing$ENQ),
						      .DEQ(byteAlignerReader_outgoing$DEQ),
						      .CLR(byteAlignerReader_outgoing$CLR),
						      .D_OUT(),
						      .FULL_N(byteAlignerReader_outgoing$FULL_N),
						      .EMPTY_N());

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  // submodule byteAlignerWriter_addr_ff
  SyncFIFO1 #(.dataWidth(32'd192)) byteAlignerWriter_addr_ff(.sCLK(CLK),
							     .dCLK(CLK_m64_axi_aclk),
							     .sRST(RST_N),
							     .sD_IN(byteAlignerWriter_addr_ff$sD_IN),
							     .sENQ(byteAlignerWriter_addr_ff$sENQ),
							     .dDEQ(byteAlignerWriter_addr_ff$dDEQ),
							     .sFULL_N(),
							     .dEMPTY_N(byteAlignerWriter_addr_ff$dEMPTY_N),
							     .dD_OUT(byteAlignerWriter_addr_ff$dD_OUT));

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  // submodule byteAlignerWriter_incoming
  FIFO2 #(.width(32'd256),
	  .guarded(32'd1)) byteAlignerWriter_incoming(.RST(RST_N_m64_axi_arestn),
						      .CLK(CLK_m64_axi_aclk),
						      .D_IN(byteAlignerWriter_incoming$D_IN),
						      .ENQ(byteAlignerWriter_incoming$ENQ),
						      .DEQ(byteAlignerWriter_incoming$DEQ),
						      .CLR(byteAlignerWriter_incoming$CLR),
						      .D_OUT(byteAlignerWriter_incoming$D_OUT),
						      .FULL_N(),
						      .EMPTY_N(byteAlignerWriter_incoming$EMPTY_N));

  // submodule byteAlignerWriter_outgoing
  FIFO2 #(.width(32'd256),
	  .guarded(32'd1)) byteAlignerWriter_outgoing(.RST(RST_N_m64_axi_arestn),
						      .CLK(CLK_m64_axi_aclk),
						      .D_IN(byteAlignerWriter_outgoing$D_IN),
						      .ENQ(byteAlignerWriter_outgoing$ENQ),
						      .DEQ(byteAlignerWriter_outgoing$DEQ),
						      .CLR(byteAlignerWriter_outgoing$CLR),
						      .D_OUT(),
						      .FULL_N(byteAlignerWriter_outgoing$FULL_N),
						      .EMPTY_N());

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  // submodule cmdsIn
  FIFO2 #(.width(32'd1), .guarded(32'd1)) cmdsIn(.RST(RST_N),
						 .CLK(CLK),
						 .D_IN(cmdsIn$D_IN),
						 .ENQ(cmdsIn$ENQ),
						 .DEQ(cmdsIn$DEQ),
						 .CLR(cmdsIn$CLR),
						 .D_OUT(cmdsIn$D_OUT),
						 .FULL_N(cmdsIn$FULL_N),
						 .EMPTY_N(cmdsIn$EMPTY_N));

  // submodule fpgaDone
  SyncFIFO1 #(.dataWidth(32'd1)) fpgaDone(.sCLK(CLK_m32_axi_aclk),
					  .dCLK(CLK),
					  .sRST(RST_N_m32_axi_arestn),
					  .sD_IN(fpgaDone$sD_IN),
					  .sENQ(fpgaDone$sENQ),
					  .dDEQ(fpgaDone$dDEQ),
					  .sFULL_N(fpgaDone$sFULL_N),
					  .dEMPTY_N(fpgaDone$dEMPTY_N),
					  .dD_OUT());

  // submodule fpga_request_converter
  SyncFIFO #(.dataWidth(32'd512),
	     .depth(32'd512),
	     .indxWidth(32'd9)) fpga_request_converter(.sCLK(CLK_m64_axi_aclk),
						       .dCLK(CLK_m32_axi_aclk),
						       .sRST(RST_N_m64_axi_arestn),
						       .sD_IN(fpga_request_converter$sD_IN),
						       .sENQ(fpga_request_converter$sENQ),
						       .dDEQ(fpga_request_converter$dDEQ),
						       .sFULL_N(fpga_request_converter$sFULL_N),
						       .dEMPTY_N(fpga_request_converter$dEMPTY_N),
						       .dD_OUT(fpga_request_converter$dD_OUT));

  // submodule fpga_response_converter
  SyncFIFO #(.dataWidth(32'd512),
	     .depth(32'd512),
	     .indxWidth(32'd9)) fpga_response_converter(.sCLK(CLK_m32_axi_aclk),
							.dCLK(CLK_m64_axi_aclk),
							.sRST(RST_N_m32_axi_arestn),
							.sD_IN(fpga_response_converter$sD_IN),
							.sENQ(fpga_response_converter$sENQ),
							.dDEQ(fpga_response_converter$dDEQ),
							.sFULL_N(fpga_response_converter$sFULL_N),
							.dEMPTY_N(fpga_response_converter$dEMPTY_N),
							.dD_OUT(fpga_response_converter$dD_OUT));

  // submodule m_fpga_rd_master_rd_in
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  SizedFIFO #(.p1width(32'd95),
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	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
	      .guarded(32'd1)) m_fpga_rd_master_rd_in(.RST(RST_N_m32_axi_arestn),
						      .CLK(CLK_m32_axi_aclk),
						      .D_IN(m_fpga_rd_master_rd_in$D_IN),
						      .ENQ(m_fpga_rd_master_rd_in$ENQ),
						      .DEQ(m_fpga_rd_master_rd_in$DEQ),
						      .CLR(m_fpga_rd_master_rd_in$CLR),
						      .D_OUT(m_fpga_rd_master_rd_in$D_OUT),
						      .FULL_N(m_fpga_rd_master_rd_in$FULL_N),
						      .EMPTY_N(m_fpga_rd_master_rd_in$EMPTY_N));

  // submodule m_fpga_rd_master_rd_out
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  FIFO2 #(.width(32'd517),
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	  .guarded(32'd1)) m_fpga_rd_master_rd_out(.RST(RST_N_m32_axi_arestn),
						   .CLK(CLK_m32_axi_aclk),
						   .D_IN(m_fpga_rd_master_rd_out$D_IN),
						   .ENQ(m_fpga_rd_master_rd_out$ENQ),
						   .DEQ(m_fpga_rd_master_rd_out$DEQ),
						   .CLR(m_fpga_rd_master_rd_out$CLR),
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						   .D_OUT(m_fpga_rd_master_rd_out$D_OUT),
						   .FULL_N(m_fpga_rd_master_rd_out$FULL_N),
						   .EMPTY_N(m_fpga_rd_master_rd_out$EMPTY_N));

  // submodule m_fpga_rd_outgoingBuffer
  FIFO2 #(.width(32'd512),
	  .guarded(32'd1)) m_fpga_rd_outgoingBuffer(.RST(RST_N_m32_axi_arestn),
						    .CLK(CLK_m32_axi_aclk),
						    .D_IN(m_fpga_rd_outgoingBuffer$D_IN),
						    .ENQ(m_fpga_rd_outgoingBuffer$ENQ),
						    .DEQ(m_fpga_rd_outgoingBuffer$DEQ),
						    .CLR(m_fpga_rd_outgoingBuffer$CLR),
						    .D_OUT(m_fpga_rd_outgoingBuffer$D_OUT),
						    .FULL_N(m_fpga_rd_outgoingBuffer$FULL_N),
						    .EMPTY_N(m_fpga_rd_outgoingBuffer$EMPTY_N));
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  // submodule m_fpga_rd_reqGen_incomingBuffer
  FIFO2 #(.width(32'd132),
	  .guarded(32'd1)) m_fpga_rd_reqGen_incomingBuffer(.RST(RST_N_m32_axi_arestn),
							   .CLK(CLK_m32_axi_aclk),
							   .D_IN(m_fpga_rd_reqGen_incomingBuffer$D_IN),
							   .ENQ(m_fpga_rd_reqGen_incomingBuffer$ENQ),
							   .DEQ(m_fpga_rd_reqGen_incomingBuffer$DEQ),
							   .CLR(m_fpga_rd_reqGen_incomingBuffer$CLR),
							   .D_OUT(m_fpga_rd_reqGen_incomingBuffer$D_OUT),
							   .FULL_N(m_fpga_rd_reqGen_incomingBuffer$FULL_N),
							   .EMPTY_N(m_fpga_rd_reqGen_incomingBuffer$EMPTY_N));

  // submodule m_fpga_rd_reqGen_intermediateBuffer
  FIFO2 #(.width(32'd144),
	  .guarded(32'd1)) m_fpga_rd_reqGen_intermediateBuffer(.RST(RST_N_m32_axi_arestn),
							       .CLK(CLK_m32_axi_aclk),
							       .D_IN(m_fpga_rd_reqGen_intermediateBuffer$D_IN),
							       .ENQ(m_fpga_rd_reqGen_intermediateBuffer$ENQ),
							       .DEQ(m_fpga_rd_reqGen_intermediateBuffer$DEQ),
							       .CLR(m_fpga_rd_reqGen_intermediateBuffer$CLR),
							       .D_OUT(m_fpga_rd_reqGen_intermediateBuffer$D_OUT),
							       .FULL_N(m_fpga_rd_reqGen_intermediateBuffer$FULL_N),
							       .EMPTY_N(m_fpga_rd_reqGen_intermediateBuffer$EMPTY_N));

  // submodule m_fpga_rd_reqGen_intermediateBuffer2
  FIFO2 #(.width(32'd202),
	  .guarded(32'd1)) m_fpga_rd_reqGen_intermediateBuffer2(.RST(RST_N_m32_axi_arestn),
								.CLK(CLK_m32_axi_aclk),
								.D_IN(m_fpga_rd_reqGen_intermediateBuffer2$D_IN),
								.ENQ(m_fpga_rd_reqGen_intermediateBuffer2$ENQ),
								.DEQ(m_fpga_rd_reqGen_intermediateBuffer2$DEQ),
								.CLR(m_fpga_rd_reqGen_intermediateBuffer2$CLR),
								.D_OUT(m_fpga_rd_reqGen_intermediateBuffer2$D_OUT),
								.FULL_N(m_fpga_rd_reqGen_intermediateBuffer2$FULL_N),
								.EMPTY_N(m_fpga_rd_reqGen_intermediateBuffer2$EMPTY_N));

  // submodule m_fpga_rd_reqGen_outgoingBuffer
  FIFO2 #(.width(32'd211),
	  .guarded(32'd1)) m_fpga_rd_reqGen_outgoingBuffer(.RST(RST_N_m32_axi_arestn),
							   .CLK(CLK_m32_axi_aclk),
							   .D_IN(m_fpga_rd_reqGen_outgoingBuffer$D_IN),
							   .ENQ(m_fpga_rd_reqGen_outgoingBuffer$ENQ),
							   .DEQ(m_fpga_rd_reqGen_outgoingBuffer$DEQ),
							   .CLR(m_fpga_rd_reqGen_outgoingBuffer$CLR),
							   .D_OUT(m_fpga_rd_reqGen_outgoingBuffer$D_OUT),
							   .FULL_N(m_fpga_rd_reqGen_outgoingBuffer$FULL_N),
							   .EMPTY_N(m_fpga_rd_reqGen_outgoingBuffer$EMPTY_N));

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  // submodule m_fpga_wr_beatsPerRequestFIFO
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  SizedFIFO #(.p1width(32'd8),
	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
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	      .guarded(32'd1)) m_fpga_wr_beatsPerRequestFIFO(.RST(RST_N_m32_axi_arestn),
							     .CLK(CLK_m32_axi_aclk),
							     .D_IN(m_fpga_wr_beatsPerRequestFIFO$D_IN),
							     .ENQ(m_fpga_wr_beatsPerRequestFIFO$ENQ),
							     .DEQ(m_fpga_wr_beatsPerRequestFIFO$DEQ),
							     .CLR(m_fpga_wr_beatsPerRequestFIFO$CLR),
							     .D_OUT(m_fpga_wr_beatsPerRequestFIFO$D_OUT),
							     .FULL_N(m_fpga_wr_beatsPerRequestFIFO$FULL_N),
							     .EMPTY_N(m_fpga_wr_beatsPerRequestFIFO$EMPTY_N));
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  // submodule m_fpga_wr_incomingBuffer
  FIFO2 #(.width(32'd512),
	  .guarded(32'd1)) m_fpga_wr_incomingBuffer(.RST(RST_N_m32_axi_arestn),
						    .CLK(CLK_m32_axi_aclk),
						    .D_IN(m_fpga_wr_incomingBuffer$D_IN),
						    .ENQ(m_fpga_wr_incomingBuffer$ENQ),
						    .DEQ(m_fpga_wr_incomingBuffer$DEQ),
						    .CLR(m_fpga_wr_incomingBuffer$CLR),
						    .D_OUT(m_fpga_wr_incomingBuffer$D_OUT),
						    .FULL_N(m_fpga_wr_incomingBuffer$FULL_N),
						    .EMPTY_N(m_fpga_wr_incomingBuffer$EMPTY_N));

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  // submodule m_fpga_wr_master_wr_in_addr
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  SizedFIFO #(.p1width(32'd95),
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	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
	      .guarded(32'd1)) m_fpga_wr_master_wr_in_addr(.RST(RST_N_m32_axi_arestn),
							   .CLK(CLK_m32_axi_aclk),
							   .D_IN(m_fpga_wr_master_wr_in_addr$D_IN),
							   .ENQ(m_fpga_wr_master_wr_in_addr$ENQ),
							   .DEQ(m_fpga_wr_master_wr_in_addr$DEQ),
							   .CLR(m_fpga_wr_master_wr_in_addr$CLR),
							   .D_OUT(m_fpga_wr_master_wr_in_addr$D_OUT),
							   .FULL_N(m_fpga_wr_master_wr_in_addr$FULL_N),
							   .EMPTY_N(m_fpga_wr_master_wr_in_addr$EMPTY_N));

  // submodule m_fpga_wr_master_wr_in_data
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  FIFO2 #(.width(32'd578),
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	  .guarded(32'd1)) m_fpga_wr_master_wr_in_data(.RST(RST_N_m32_axi_arestn),
						       .CLK(CLK_m32_axi_aclk),
						       .D_IN(m_fpga_wr_master_wr_in_data$D_IN),
						       .ENQ(m_fpga_wr_master_wr_in_data$ENQ),
						       .DEQ(m_fpga_wr_master_wr_in_data$DEQ),
						       .CLR(m_fpga_wr_master_wr_in_data$CLR),
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						       .D_OUT(m_fpga_wr_master_wr_in_data$D_OUT),
						       .FULL_N(m_fpga_wr_master_wr_in_data$FULL_N),
						       .EMPTY_N(m_fpga_wr_master_wr_in_data$EMPTY_N));
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  // submodule m_fpga_wr_master_wr_out
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  FIFO2 #(.width(32'd4),
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	  .guarded(32'd1)) m_fpga_wr_master_wr_out(.RST(RST_N_m32_axi_arestn),
						   .CLK(CLK_m32_axi_aclk),
						   .D_IN(m_fpga_wr_master_wr_out$D_IN),
						   .ENQ(m_fpga_wr_master_wr_out$ENQ),
						   .DEQ(m_fpga_wr_master_wr_out$DEQ),
						   .CLR(m_fpga_wr_master_wr_out$CLR),
						   .D_OUT(),
						   .FULL_N(m_fpga_wr_master_wr_out$FULL_N),
						   .EMPTY_N(m_fpga_wr_master_wr_out$EMPTY_N));

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  // submodule m_fpga_wr_reqGen_incomingBuffer
  FIFO2 #(.width(32'd132),
	  .guarded(32'd1)) m_fpga_wr_reqGen_incomingBuffer(.RST(RST_N_m32_axi_arestn),
							   .CLK(CLK_m32_axi_aclk),
							   .D_IN(m_fpga_wr_reqGen_incomingBuffer$D_IN),
							   .ENQ(m_fpga_wr_reqGen_incomingBuffer$ENQ),
							   .DEQ(m_fpga_wr_reqGen_incomingBuffer$DEQ),
							   .CLR(m_fpga_wr_reqGen_incomingBuffer$CLR),
							   .D_OUT(m_fpga_wr_reqGen_incomingBuffer$D_OUT),
							   .FULL_N(m_fpga_wr_reqGen_incomingBuffer$FULL_N),
							   .EMPTY_N(m_fpga_wr_reqGen_incomingBuffer$EMPTY_N));

  // submodule m_fpga_wr_reqGen_intermediateBuffer
  FIFO2 #(.width(32'd144),
	  .guarded(32'd1)) m_fpga_wr_reqGen_intermediateBuffer(.RST(RST_N_m32_axi_arestn),
							       .CLK(CLK_m32_axi_aclk),
							       .D_IN(m_fpga_wr_reqGen_intermediateBuffer$D_IN),
							       .ENQ(m_fpga_wr_reqGen_intermediateBuffer$ENQ),
							       .DEQ(m_fpga_wr_reqGen_intermediateBuffer$DEQ),
							       .CLR(m_fpga_wr_reqGen_intermediateBuffer$CLR),
							       .D_OUT(m_fpga_wr_reqGen_intermediateBuffer$D_OUT),
							       .FULL_N(m_fpga_wr_reqGen_intermediateBuffer$FULL_N),
							       .EMPTY_N(m_fpga_wr_reqGen_intermediateBuffer$EMPTY_N));

  // submodule m_fpga_wr_reqGen_intermediateBuffer2
  FIFO2 #(.width(32'd202),
	  .guarded(32'd1)) m_fpga_wr_reqGen_intermediateBuffer2(.RST(RST_N_m32_axi_arestn),
								.CLK(CLK_m32_axi_aclk),
								.D_IN(m_fpga_wr_reqGen_intermediateBuffer2$D_IN),
								.ENQ(m_fpga_wr_reqGen_intermediateBuffer2$ENQ),
								.DEQ(m_fpga_wr_reqGen_intermediateBuffer2$DEQ),
								.CLR(m_fpga_wr_reqGen_intermediateBuffer2$CLR),
								.D_OUT(m_fpga_wr_reqGen_intermediateBuffer2$D_OUT),
								.FULL_N(m_fpga_wr_reqGen_intermediateBuffer2$FULL_N),
								.EMPTY_N(m_fpga_wr_reqGen_intermediateBuffer2$EMPTY_N));

  // submodule m_fpga_wr_reqGen_outgoingBuffer
  FIFO2 #(.width(32'd211),
	  .guarded(32'd1)) m_fpga_wr_reqGen_outgoingBuffer(.RST(RST_N_m32_axi_arestn),
							   .CLK(CLK_m32_axi_aclk),
							   .D_IN(m_fpga_wr_reqGen_outgoingBuffer$D_IN),
							   .ENQ(m_fpga_wr_reqGen_outgoingBuffer$ENQ),
							   .DEQ(m_fpga_wr_reqGen_outgoingBuffer$DEQ),
							   .CLR(m_fpga_wr_reqGen_outgoingBuffer$CLR),
							   .D_OUT(m_fpga_wr_reqGen_outgoingBuffer$D_OUT),
							   .FULL_N(m_fpga_wr_reqGen_outgoingBuffer$FULL_N),
							   .EMPTY_N(m_fpga_wr_reqGen_outgoingBuffer$EMPTY_N));

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  // submodule m_pcie_rd_master_rd_in
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  SizedFIFO #(.p1width(32'd95),
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	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
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	      .guarded(32'd1)) m_pcie_rd_master_rd_in(.RST(RST_N_m64_axi_arestn),
						      .CLK(CLK_m64_axi_aclk),
						      .D_IN(m_pcie_rd_master_rd_in$D_IN),
						      .ENQ(m_pcie_rd_master_rd_in$ENQ),
						      .DEQ(m_pcie_rd_master_rd_in$DEQ),
						      .CLR(m_pcie_rd_master_rd_in$CLR),
						      .D_OUT(m_pcie_rd_master_rd_in$D_OUT),
						      .FULL_N(m_pcie_rd_master_rd_in$FULL_N),
						      .EMPTY_N(m_pcie_rd_master_rd_in$EMPTY_N));

  // submodule m_pcie_rd_master_rd_out
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  FIFO2 #(.width(32'd261),
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	  .guarded(32'd1)) m_pcie_rd_master_rd_out(.RST(RST_N_m64_axi_arestn),
						   .CLK(CLK_m64_axi_aclk),
						   .D_IN(m_pcie_rd_master_rd_out$D_IN),
						   .ENQ(m_pcie_rd_master_rd_out$ENQ),
						   .DEQ(m_pcie_rd_master_rd_out$DEQ),
						   .CLR(m_pcie_rd_master_rd_out$CLR),
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						   .D_OUT(m_pcie_rd_master_rd_out$D_OUT),
						   .FULL_N(m_pcie_rd_master_rd_out$FULL_N),
						   .EMPTY_N(m_pcie_rd_master_rd_out$EMPTY_N));

  // submodule m_pcie_rd_outgoingBuffer
  FIFO2 #(.width(32'd256),
	  .guarded(32'd1)) m_pcie_rd_outgoingBuffer(.RST(RST_N_m64_axi_arestn),
						    .CLK(CLK_m64_axi_aclk),
						    .D_IN(m_pcie_rd_outgoingBuffer$D_IN),
						    .ENQ(m_pcie_rd_outgoingBuffer$ENQ),
						    .DEQ(m_pcie_rd_outgoingBuffer$DEQ),
						    .CLR(m_pcie_rd_outgoingBuffer$CLR),
						    .D_OUT(m_pcie_rd_outgoingBuffer$D_OUT),
						    .FULL_N(m_pcie_rd_outgoingBuffer$FULL_N),
						    .EMPTY_N(m_pcie_rd_outgoingBuffer$EMPTY_N));
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  // submodule m_pcie_rd_reqGen_incomingBuffer
  FIFO2 #(.width(32'd132),
	  .guarded(32'd1)) m_pcie_rd_reqGen_incomingBuffer(.RST(RST_N_m64_axi_arestn),
							   .CLK(CLK_m64_axi_aclk),
							   .D_IN(m_pcie_rd_reqGen_incomingBuffer$D_IN),
							   .ENQ(m_pcie_rd_reqGen_incomingBuffer$ENQ),
							   .DEQ(m_pcie_rd_reqGen_incomingBuffer$DEQ),
							   .CLR(m_pcie_rd_reqGen_incomingBuffer$CLR),
							   .D_OUT(m_pcie_rd_reqGen_incomingBuffer$D_OUT),
							   .FULL_N(m_pcie_rd_reqGen_incomingBuffer$FULL_N),
							   .EMPTY_N(m_pcie_rd_reqGen_incomingBuffer$EMPTY_N));

  // submodule m_pcie_rd_reqGen_intermediateBuffer
  FIFO2 #(.width(32'd142),
	  .guarded(32'd1)) m_pcie_rd_reqGen_intermediateBuffer(.RST(RST_N_m64_axi_arestn),
							       .CLK(CLK_m64_axi_aclk),
							       .D_IN(m_pcie_rd_reqGen_intermediateBuffer$D_IN),
							       .ENQ(m_pcie_rd_reqGen_intermediateBuffer$ENQ),
							       .DEQ(m_pcie_rd_reqGen_intermediateBuffer$DEQ),
							       .CLR(m_pcie_rd_reqGen_intermediateBuffer$CLR),
							       .D_OUT(m_pcie_rd_reqGen_intermediateBuffer$D_OUT),
							       .FULL_N(m_pcie_rd_reqGen_intermediateBuffer$FULL_N),
							       .EMPTY_N(m_pcie_rd_reqGen_intermediateBuffer$EMPTY_N));

  // submodule m_pcie_rd_reqGen_intermediateBuffer2
  FIFO2 #(.width(32'd201),
	  .guarded(32'd1)) m_pcie_rd_reqGen_intermediateBuffer2(.RST(RST_N_m64_axi_arestn),
								.CLK(CLK_m64_axi_aclk),
								.D_IN(m_pcie_rd_reqGen_intermediateBuffer2$D_IN),
								.ENQ(m_pcie_rd_reqGen_intermediateBuffer2$ENQ),
								.DEQ(m_pcie_rd_reqGen_intermediateBuffer2$DEQ),
								.CLR(m_pcie_rd_reqGen_intermediateBuffer2$CLR),
								.D_OUT(m_pcie_rd_reqGen_intermediateBuffer2$D_OUT),
								.FULL_N(m_pcie_rd_reqGen_intermediateBuffer2$FULL_N),
								.EMPTY_N(m_pcie_rd_reqGen_intermediateBuffer2$EMPTY_N));

  // submodule m_pcie_rd_reqGen_outgoingBuffer
  FIFO2 #(.width(32'd210),
	  .guarded(32'd1)) m_pcie_rd_reqGen_outgoingBuffer(.RST(RST_N_m64_axi_arestn),
							   .CLK(CLK_m64_axi_aclk),
							   .D_IN(m_pcie_rd_reqGen_outgoingBuffer$D_IN),
							   .ENQ(m_pcie_rd_reqGen_outgoingBuffer$ENQ),
							   .DEQ(m_pcie_rd_reqGen_outgoingBuffer$DEQ),
							   .CLR(m_pcie_rd_reqGen_outgoingBuffer$CLR),
							   .D_OUT(m_pcie_rd_reqGen_outgoingBuffer$D_OUT),
							   .FULL_N(m_pcie_rd_reqGen_outgoingBuffer$FULL_N),
							   .EMPTY_N(m_pcie_rd_reqGen_outgoingBuffer$EMPTY_N));

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  // submodule m_pcie_wr_beatsPerRequestFIFO
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  SizedFIFO #(.p1width(32'd8),
	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
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	      .guarded(32'd1)) m_pcie_wr_beatsPerRequestFIFO(.RST(RST_N_m64_axi_arestn),
							     .CLK(CLK_m64_axi_aclk),
							     .D_IN(m_pcie_wr_beatsPerRequestFIFO$D_IN),
							     .ENQ(m_pcie_wr_beatsPerRequestFIFO$ENQ),
							     .DEQ(m_pcie_wr_beatsPerRequestFIFO$DEQ),
							     .CLR(m_pcie_wr_beatsPerRequestFIFO$CLR),
							     .D_OUT(m_pcie_wr_beatsPerRequestFIFO$D_OUT),
							     .FULL_N(m_pcie_wr_beatsPerRequestFIFO$FULL_N),
							     .EMPTY_N(m_pcie_wr_beatsPerRequestFIFO$EMPTY_N));
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  // submodule m_pcie_wr_incomingBuffer
  FIFO2 #(.width(32'd256),
	  .guarded(32'd1)) m_pcie_wr_incomingBuffer(.RST(RST_N_m64_axi_arestn),
						    .CLK(CLK_m64_axi_aclk),
						    .D_IN(m_pcie_wr_incomingBuffer$D_IN),
						    .ENQ(m_pcie_wr_incomingBuffer$ENQ),
						    .DEQ(m_pcie_wr_incomingBuffer$DEQ),
						    .CLR(m_pcie_wr_incomingBuffer$CLR),
						    .D_OUT(m_pcie_wr_incomingBuffer$D_OUT),
						    .FULL_N(m_pcie_wr_incomingBuffer$FULL_N),
						    .EMPTY_N(m_pcie_wr_incomingBuffer$EMPTY_N));

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  // submodule m_pcie_wr_master_wr_in_addr
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  SizedFIFO #(.p1width(32'd95),
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	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
	      .guarded(32'd1)) m_pcie_wr_master_wr_in_addr(.RST(RST_N_m64_axi_arestn),
							   .CLK(CLK_m64_axi_aclk),
							   .D_IN(m_pcie_wr_master_wr_in_addr$D_IN),
							   .ENQ(m_pcie_wr_master_wr_in_addr$ENQ),
							   .DEQ(m_pcie_wr_master_wr_in_addr$DEQ),
							   .CLR(m_pcie_wr_master_wr_in_addr$CLR),
							   .D_OUT(m_pcie_wr_master_wr_in_addr$D_OUT),
							   .FULL_N(m_pcie_wr_master_wr_in_addr$FULL_N),
							   .EMPTY_N(m_pcie_wr_master_wr_in_addr$EMPTY_N));

  // submodule m_pcie_wr_master_wr_in_data
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  FIFO2 #(.width(32'd290),
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	  .guarded(32'd1)) m_pcie_wr_master_wr_in_data(.RST(RST_N_m64_axi_arestn),
						       .CLK(CLK_m64_axi_aclk),
						       .D_IN(m_pcie_wr_master_wr_in_data$D_IN),
						       .ENQ(m_pcie_wr_master_wr_in_data$ENQ),
						       .DEQ(m_pcie_wr_master_wr_in_data$DEQ),
						       .CLR(m_pcie_wr_master_wr_in_data$CLR),
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						       .D_OUT(m_pcie_wr_master_wr_in_data$D_OUT),
						       .FULL_N(m_pcie_wr_master_wr_in_data$FULL_N),
						       .EMPTY_N(m_pcie_wr_master_wr_in_data$EMPTY_N));
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  // submodule m_pcie_wr_master_wr_out
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  FIFO2 #(.width(32'd4),
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	  .guarded(32'd1)) m_pcie_wr_master_wr_out(.RST(RST_N_m64_axi_arestn),
						   .CLK(CLK_m64_axi_aclk),
						   .D_IN(m_pcie_wr_master_wr_out$D_IN),
						   .ENQ(m_pcie_wr_master_wr_out$ENQ),
						   .DEQ(m_pcie_wr_master_wr_out$DEQ),
						   .CLR(m_pcie_wr_master_wr_out$CLR),
						   .D_OUT(),
						   .FULL_N(m_pcie_wr_master_wr_out$FULL_N),
						   .EMPTY_N(m_pcie_wr_master_wr_out$EMPTY_N));

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  // submodule m_pcie_wr_reqGen_incomingBuffer
  FIFO2 #(.width(32'd132),
	  .guarded(32'd1)) m_pcie_wr_reqGen_incomingBuffer(.RST(RST_N_m64_axi_arestn),
							   .CLK(CLK_m64_axi_aclk),
							   .D_IN(m_pcie_wr_reqGen_incomingBuffer$D_IN),
							   .ENQ(m_pcie_wr_reqGen_incomingBuffer$ENQ),
							   .DEQ(m_pcie_wr_reqGen_incomingBuffer$DEQ),
							   .CLR(m_pcie_wr_reqGen_incomingBuffer$CLR),
							   .D_OUT(m_pcie_wr_reqGen_incomingBuffer$D_OUT),
							   .FULL_N(m_pcie_wr_reqGen_incomingBuffer$FULL_N),
							   .EMPTY_N(m_pcie_wr_reqGen_incomingBuffer$EMPTY_N));

  // submodule m_pcie_wr_reqGen_intermediateBuffer
  FIFO2 #(.width(32'd142),
	  .guarded(32'd1)) m_pcie_wr_reqGen_intermediateBuffer(.RST(RST_N_m64_axi_arestn),
							       .CLK(CLK_m64_axi_aclk),
							       .D_IN(m_pcie_wr_reqGen_intermediateBuffer$D_IN),
							       .ENQ(m_pcie_wr_reqGen_intermediateBuffer$ENQ),
							       .DEQ(m_pcie_wr_reqGen_intermediateBuffer$DEQ),
							       .CLR(m_pcie_wr_reqGen_intermediateBuffer$CLR),
							       .D_OUT(m_pcie_wr_reqGen_intermediateBuffer$D_OUT),
							       .FULL_N(m_pcie_wr_reqGen_intermediateBuffer$FULL_N),
							       .EMPTY_N(m_pcie_wr_reqGen_intermediateBuffer$EMPTY_N));

  // submodule m_pcie_wr_reqGen_intermediateBuffer2
  FIFO2 #(.width(32'd201),
	  .guarded(32'd1)) m_pcie_wr_reqGen_intermediateBuffer2(.RST(RST_N_m64_axi_arestn),
								.CLK(CLK_m64_axi_aclk),
								.D_IN(m_pcie_wr_reqGen_intermediateBuffer2$D_IN),
								.ENQ(m_pcie_wr_reqGen_intermediateBuffer2$ENQ),
								.DEQ(m_pcie_wr_reqGen_intermediateBuffer2$DEQ),
								.CLR(m_pcie_wr_reqGen_intermediateBuffer2$CLR),
								.D_OUT(m_pcie_wr_reqGen_intermediateBuffer2$D_OUT),
								.FULL_N(m_pcie_wr_reqGen_intermediateBuffer2$FULL_N),
								.EMPTY_N(m_pcie_wr_reqGen_intermediateBuffer2$EMPTY_N));

  // submodule m_pcie_wr_reqGen_outgoingBuffer
  FIFO2 #(.width(32'd210),
	  .guarded(32'd1)) m_pcie_wr_reqGen_outgoingBuffer(.RST(RST_N_m64_axi_arestn),
							   .CLK(CLK_m64_axi_aclk),
							   .D_IN(m_pcie_wr_reqGen_outgoingBuffer$D_IN),
							   .ENQ(m_pcie_wr_reqGen_outgoingBuffer$ENQ),
							   .DEQ(m_pcie_wr_reqGen_outgoingBuffer$DEQ),
							   .CLR(m_pcie_wr_reqGen_outgoingBuffer$CLR),
							   .D_OUT(m_pcie_wr_reqGen_outgoingBuffer$D_OUT),
							   .FULL_N(m_pcie_wr_reqGen_outgoingBuffer$FULL_N),
							   .EMPTY_N(m_pcie_wr_reqGen_outgoingBuffer$EMPTY_N));

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  // submodule mclk_m_fpga_put_req_rd_ff
  SyncFIFO1 #(.dataWidth(32'd132)) mclk_m_fpga_put_req_rd_ff(.sCLK(CLK),
							     .dCLK(CLK_m32_axi_aclk),
							     .sRST(RST_N),
							     .sD_IN(mclk_m_fpga_put_req_rd_ff$sD_IN),
							     .sENQ(mclk_m_fpga_put_req_rd_ff$sENQ),
							     .dDEQ(mclk_m_fpga_put_req_rd_ff$dDEQ),
							     .sFULL_N(mclk_m_fpga_put_req_rd_ff$sFULL_N),
							     .dEMPTY_N(mclk_m_fpga_put_req_rd_ff$dEMPTY_N),
							     .dD_OUT(mclk_m_fpga_put_req_rd_ff$dD_OUT));

  // submodule mclk_m_fpga_put_req_wr_ff
  SyncFIFO1 #(.dataWidth(32'd132)) mclk_m_fpga_put_req_wr_ff(.sCLK(CLK),
							     .dCLK(CLK_m32_axi_aclk),
							     .sRST(RST_N),
							     .sD_IN(mclk_m_fpga_put_req_wr_ff$sD_IN),
							     .sENQ(mclk_m_fpga_put_req_wr_ff$sENQ),
							     .dDEQ(mclk_m_fpga_put_req_wr_ff$dDEQ),
							     .sFULL_N(mclk_m_fpga_put_req_wr_ff$sFULL_N),
							     .dEMPTY_N(mclk_m_fpga_put_req_wr_ff$dEMPTY_N),
							     .dD_OUT(mclk_m_fpga_put_req_wr_ff$dD_OUT));

  // submodule mclk_m_pcie_put_req_rd_ff
  SyncFIFO1 #(.dataWidth(32'd132)) mclk_m_pcie_put_req_rd_ff(.sCLK(CLK),
							     .dCLK(CLK_m64_axi_aclk),
							     .sRST(RST_N),
							     .sD_IN(mclk_m_pcie_put_req_rd_ff$sD_IN),
							     .sENQ(mclk_m_pcie_put_req_rd_ff$sENQ),
							     .dDEQ(mclk_m_pcie_put_req_rd_ff$dDEQ),
							     .sFULL_N(mclk_m_pcie_put_req_rd_ff$sFULL_N),
							     .dEMPTY_N(mclk_m_pcie_put_req_rd_ff$dEMPTY_N),
							     .dD_OUT(mclk_m_pcie_put_req_rd_ff$dD_OUT));

  // submodule mclk_m_pcie_put_req_wr_ff
  SyncFIFO1 #(.dataWidth(32'd132)) mclk_m_pcie_put_req_wr_ff(.sCLK(CLK),
							     .dCLK(CLK_m64_axi_aclk),
							     .sRST(RST_N),
							     .sD_IN(mclk_m_pcie_put_req_wr_ff$sD_IN),
							     .sENQ(mclk_m_pcie_put_req_wr_ff$sENQ),
							     .dDEQ(mclk_m_pcie_put_req_wr_ff$dDEQ),
							     .sFULL_N(mclk_m_pcie_put_req_wr_ff$sFULL_N),
							     .dEMPTY_N(mclk_m_pcie_put_req_wr_ff$dEMPTY_N),
							     .dD_OUT(mclk_m_pcie_put_req_wr_ff$dD_OUT));

  // submodule pcieDone
  SyncFIFO1 #(.dataWidth(32'd1)) pcieDone(.sCLK(CLK_m64_axi_aclk),
					  .dCLK(CLK),
					  .sRST(RST_N_m64_axi_arestn),
					  .sD_IN(pcieDone$sD_IN),
					  .sENQ(pcieDone$sENQ),
					  .dDEQ(pcieDone$dDEQ),
					  .sFULL_N(pcieDone$sFULL_N),
					  .dEMPTY_N(pcieDone$dEMPTY_N),
					  .dD_OUT());

  // submodule readConvBTT_ff
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  SyncFIFO1 #(.dataWidth(32'd65)) readConvBTT_ff(.sCLK(CLK),
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						 .dCLK(CLK_m64_axi_aclk),
						 .sRST(RST_N),
						 .sD_IN(readConvBTT_ff$sD_IN),
						 .sENQ(readConvBTT_ff$sENQ),
						 .dDEQ(readConvBTT_ff$dDEQ),
						 .sFULL_N(readConvBTT_ff$sFULL_N),
						 .dEMPTY_N(readConvBTT_ff$dEMPTY_N),
						 .dD_OUT(readConvBTT_ff$dD_OUT));

  // submodule s_config_readSlave_in
  FIFO1 #(.width(32'd67), .guarded(32'd1)) s_config_readSlave_in(.RST(RST_N),
								 .CLK(CLK),
								 .D_IN(s_config_readSlave_in$D_IN),
								 .ENQ(s_config_readSlave_in$ENQ),
								 .DEQ(s_config_readSlave_in$DEQ),
								 .CLR(s_config_readSlave_in$CLR),
								 .D_OUT(s_config_readSlave_in$D_OUT),
								 .FULL_N(s_config_readSlave_in$FULL_N),
								 .EMPTY_N(s_config_readSlave_in$EMPTY_N));

  // submodule s_config_readSlave_out
  FIFO1 #(.width(32'd66), .guarded(32'd1)) s_config_readSlave_out(.RST(RST_N),
								  .CLK(CLK),
								  .D_IN(s_config_readSlave_out$D_IN),
								  .ENQ(s_config_readSlave_out$ENQ),
								  .DEQ(s_config_readSlave_out$DEQ),
								  .CLR(s_config_readSlave_out$CLR),
								  .D_OUT(s_config_readSlave_out$D_OUT),
								  .FULL_N(s_config_readSlave_out$FULL_N),
								  .EMPTY_N(s_config_readSlave_out$EMPTY_N));

  // submodule s_config_writeSlave_in
  FIFO1 #(.width(32'd139),
	  .guarded(32'd1)) s_config_writeSlave_in(.RST(RST_N),
						  .CLK(CLK),
						  .D_IN(s_config_writeSlave_in$D_IN),
						  .ENQ(s_config_writeSlave_in$ENQ),
						  .DEQ(s_config_writeSlave_in$DEQ),
						  .CLR(s_config_writeSlave_in$CLR),
						  .D_OUT(s_config_writeSlave_in$D_OUT),
						  .FULL_N(s_config_writeSlave_in$FULL_N),
						  .EMPTY_N(s_config_writeSlave_in$EMPTY_N));

  // submodule s_config_writeSlave_out
  FIFO1 #(.width(32'd2), .guarded(32'd1)) s_config_writeSlave_out(.RST(RST_N),
								  .CLK(CLK),
								  .D_IN(s_config_writeSlave_out$D_IN),
								  .ENQ(s_config_writeSlave_out$ENQ),
								  .DEQ(s_config_writeSlave_out$DEQ),
								  .CLR(s_config_writeSlave_out$CLR),
								  .D_OUT(s_config_writeSlave_out$D_OUT),
								  .FULL_N(s_config_writeSlave_out$FULL_N),
								  .EMPTY_N(s_config_writeSlave_out$EMPTY_N));

  // submodule writeConvBTT_ff
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  SyncFIFO1 #(.dataWidth(32'd65)) writeConvBTT_ff(.sCLK(CLK),
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						  .dCLK(CLK_m64_axi_aclk),
						  .sRST(RST_N),
						  .sD_IN(writeConvBTT_ff$sD_IN),
						  .sENQ(writeConvBTT_ff$sENQ),
						  .dDEQ(writeConvBTT_ff$dDEQ),
						  .sFULL_N(writeConvBTT_ff$sFULL_N),
						  .dEMPTY_N(writeConvBTT_ff$dEMPTY_N),
						  .dD_OUT(writeConvBTT_ff$dD_OUT));

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  // submodule writeConverter_dataSync
  FIFO2 #(.width(32'd512),
	  .guarded(32'd1)) writeConverter_dataSync(.RST(RST_N_m64_axi_arestn),
						   .CLK(CLK_m64_axi_aclk),
						   .D_IN(writeConverter_dataSync$D_IN),
						   .ENQ(writeConverter_dataSync$ENQ),
						   .DEQ(writeConverter_dataSync$DEQ),
						   .CLR(writeConverter_dataSync$CLR),
						   .D_OUT(writeConverter_dataSync$D_OUT),
						   .FULL_N(writeConverter_dataSync$FULL_N),
						   .EMPTY_N(writeConverter_dataSync$EMPTY_N));

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  // rule RL_s_config_axiReadSpecialIsHandled
  assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd0 ;
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  // rule RL_s_config_axiReadSpecialIsHandled_1
  assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd1 ;
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  // rule RL_s_config_axiReadSpecialIsHandled_2
  assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd8 ;
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  // rule RL_s_config_axiReadSpecialIsHandled_3
  assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd9 ;
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  // rule RL_s_config_axiReadSpecialIsHandled_4
  assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd12 ;
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  // rule RL_s_config_axiReadSpecialIsHandled_5
  assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_5 =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd3 ;
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  // rule RL_s_config_axiReadSpecialIsHandled_6
  assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd2 ;
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  // rule RL_s_config_axiReadSpecialIsHandled_7
  assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd6 ;
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  // rule RL_s_config_axiReadSpecialIsHandled_8
  assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd7 ;
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  // rule RL_s_config_axiReadSpecial_5
  assign WILL_FIRE_RL_s_config_axiReadSpecial_5 =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd3 &&
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	     !s_config_readBusy ;

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  // rule RL_s_config_axiReadSpecial_7
  assign WILL_FIRE_RL_s_config_axiReadSpecial_7 =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd6 &&
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	     !s_config_readBusy ;

  // rule RL_handleRead
  assign CAN_FIRE_RL_handleRead =
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	     readIn_rv[192] && mclk_m_pcie_put_req_wr_ff$sFULL_N &&
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	     mclk_m_fpga_put_req_rd_ff$sFULL_N &&
	     readConvBTT_ff$sFULL_N &&
	     !opInProgress ;
  assign WILL_FIRE_RL_handleRead =
	     CAN_FIRE_RL_handleRead && !WILL_FIRE_RL_handleWrite ;

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  // rule RL_s_config_axiReadSpecial_8
  assign WILL_FIRE_RL_s_config_axiReadSpecial_8 =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
	     s_config_readSlave_in$D_OUT[9:6] == 4'd7 &&
	     !s_config_readBusy ;

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  // rule RL_handleWrite
  assign WILL_FIRE_RL_handleWrite =
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	     writeIn_rv[192] && mclk_m_pcie_put_req_rd_ff$sFULL_N &&
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	     mclk_m_fpga_put_req_wr_ff$sFULL_N &&
	     writeConvBTT_ff$sFULL_N &&
	     !opInProgress ;

  // rule RL_s_config_1_axiWriteSpecial
  assign WILL_FIRE_RL_s_config_1_axiWriteSpecial =
	     s_config_writeSlave_in$EMPTY_N &&
	     s_config_writeSlave_out$FULL_N &&
	     cmdsIn$FULL_N &&
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	     s_config_writeSlave_in$D_OUT[81:78] == 4'd4 ;
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  // rule RL_s_config_1_axiWriteSpecialIsHandled
  assign WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled =
	     s_config_readSlave_in$EMPTY_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd4 ;
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  // rule RL_s_config_axiReadSpecial
  assign WILL_FIRE_RL_s_config_axiReadSpecial =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd0 &&
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	     !s_config_readBusy ;

  // rule RL_s_config_1_axiWriteSpecial_1
  assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 =
	     s_config_writeSlave_in$EMPTY_N &&
	     s_config_writeSlave_out$FULL_N &&
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	     s_config_writeSlave_in$D_OUT[81:78] == 4'd0 ;
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  // rule RL_s_config_axiReadSpecial_1
  assign WILL_FIRE_RL_s_config_axiReadSpecial_1 =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd1 &&
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	     !s_config_readBusy ;

  // rule RL_s_config_1_axiWriteSpecial_2
  assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 =
	     s_config_writeSlave_in$EMPTY_N &&
	     s_config_writeSlave_out$FULL_N &&
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	     s_config_writeSlave_in$D_OUT[81:78] == 4'd1 ;

  // rule RL_s_config_axiReadSpecial_2
  assign WILL_FIRE_RL_s_config_axiReadSpecial_2 =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
	     s_config_readSlave_in$D_OUT[9:6] == 4'd8 &&
	     !s_config_readBusy ;

  // rule RL_s_config_1_axiWriteSpecial_3
  assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 =
	     s_config_writeSlave_in$EMPTY_N &&
	     s_config_writeSlave_out$FULL_N &&
	     s_config_writeSlave_in$D_OUT[81:78] == 4'd8 ;
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  // rule RL_s_config_axiReadSpecial_3
  assign WILL_FIRE_RL_s_config_axiReadSpecial_3 =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
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	     s_config_readSlave_in$D_OUT[9:6] == 4'd9 &&
	     !s_config_readBusy ;

  // rule RL_s_config_1_axiWriteSpecial_4
  assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 =
	     s_config_writeSlave_in$EMPTY_N &&
	     s_config_writeSlave_out$FULL_N &&
	     s_config_writeSlave_in$D_OUT[81:78] == 4'd9 ;

  // rule RL_setInterrupt
  assign WILL_FIRE_RL_setInterrupt =
	     pcieDone$dEMPTY_N && fpgaDone$dEMPTY_N && opInProgress ;

  // rule RL_s_config_axiReadSpecial_4
  assign WILL_FIRE_RL_s_config_axiReadSpecial_4 =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
	     s_config_readSlave_in$D_OUT[9:6] == 4'd12 &&
	     !s_config_readBusy ;

  // rule RL_s_config_1_axiWriteSpecial_5
  assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 =
	     s_config_writeSlave_in$EMPTY_N &&
	     s_config_writeSlave_out$FULL_N &&
	     s_config_writeSlave_in$D_OUT[81:78] == 4'd12 ;

  // rule RL_s_config_axiReadSpecial_6
  assign WILL_FIRE_RL_s_config_axiReadSpecial_6 =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
	     s_config_readSlave_in$D_OUT[9:6] == 4'd2 &&
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	     !s_config_readBusy ;

  // rule RL_s_config_axiReadFallback
  assign WILL_FIRE_RL_s_config_axiReadFallback =
	     s_config_readSlave_in$EMPTY_N && s_config_readSlave_out$FULL_N &&
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	     !s_config_readIsHandled$whas ;
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  // rule RL_s_config_1_axiWriteSpecial_6
  assign WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 =
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	     s_config_writeSlave_in$EMPTY_N &&
	     s_config_writeSlave_out$FULL_N &&
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	     s_config_writeSlave_in$D_OUT[81:78] == 4'd2 ;
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  // rule RL_s_config_1_axiWriteFallback
  assign WILL_FIRE_RL_s_config_1_axiWriteFallback =
	     s_config_writeSlave_in$EMPTY_N &&
	     s_config_writeSlave_out$FULL_N &&
	     !s_config_writeIsHandled$whas &&
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	     !WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 &&
	     !WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 &&
	     !WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 &&
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