mkBlueDMA.v 264 KB
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	     !WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 &&
	     !WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 &&
	     !WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 &&
	     !WILL_FIRE_RL_s_config_1_axiWriteSpecial ;

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  // rule RL_m_pcie_wr_fillBuffer
  assign WILL_FIRE_RL_m_pcie_wr_fillBuffer =
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	     m_pcie_wr_reqGen_outgoingBuffer$EMPTY_N &&
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	     m_pcie_wr_task_data_output_reg[64:6] == 59'd0 &&
	     m_pcie_wr_task_data_requests_reg[126:68] == 59'd0 ;

  // rule RL_m_pcie_wr_reqGen_finishRequest
  assign WILL_FIRE_RL_m_pcie_wr_reqGen_finishRequest =
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	     m_pcie_wr_reqGen_intermediateBuffer2$EMPTY_N &&
	     m_pcie_wr_reqGen_outgoingBuffer$FULL_N ;
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  // rule RL_m_pcie_wr_placeRequest
  assign WILL_FIRE_RL_m_pcie_wr_placeRequest =
	     m_pcie_wr_master_wr_in_addr$FULL_N &&
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	     m_pcie_wr_beatsPerRequestFIFO$FULL_N &&
	     m_pcie_wr_task_data_requests_reg[126:68] != 59'd0 &&
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	     m_pcie_wr_incomingBuffer$EMPTY_N ;
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  // rule RL_m_pcie_wr_forwardData
  assign WILL_FIRE_RL_m_pcie_wr_forwardData =
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	     m_pcie_wr_incomingBuffer$EMPTY_N &&
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	     m_pcie_wr_beatsPerRequestFIFO$EMPTY_N &&
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	     m_pcie_wr_master_wr_in_data$FULL_N &&
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	     m_pcie_wr_task_data_output_reg[64:6] != 59'd0 ;

  // rule RL_m_pcie_rd_fillBuffer
  assign WILL_FIRE_RL_m_pcie_rd_fillBuffer =
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	     m_pcie_rd_reqGen_outgoingBuffer$EMPTY_N &&
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	     m_pcie_rd_task_data_output_reg[64:6] == 59'd0 &&
	     m_pcie_rd_task_data_requests_reg[126:68] == 59'd0 ;

  // rule RL_m_pcie_rd_reqGen_finishRequest
  assign WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest =
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	     m_pcie_rd_reqGen_intermediateBuffer2$EMPTY_N &&
	     m_pcie_rd_reqGen_outgoingBuffer$FULL_N ;
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  // rule RL_m_pcie_rd_placeRequest
  assign WILL_FIRE_RL_m_pcie_rd_placeRequest =
	     m_pcie_rd_master_rd_in$FULL_N &&
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	     m_pcie_rd_task_data_requests_reg[126:68] != 59'd0 ;
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  // rule RL_m_pcie_rd_forwardData
  assign WILL_FIRE_RL_m_pcie_rd_forwardData =
	     m_pcie_rd_master_rd_out$EMPTY_N &&
	     m_pcie_rd_outgoingBuffer$FULL_N &&
	     m_pcie_rd_task_data_output_reg[64:6] != 59'd0 ;

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  // rule RL_m_fpga_wr_fillBuffer
  assign WILL_FIRE_RL_m_fpga_wr_fillBuffer =
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	     m_fpga_wr_reqGen_outgoingBuffer$EMPTY_N &&
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	     m_fpga_wr_task_data_output_reg[64:7] == 58'd0 &&
	     m_fpga_wr_task_data_requests_reg[125:68] == 58'd0 ;
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  // rule RL_m_fpga_wr_reqGen_finishRequest
  assign WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest =
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	     m_fpga_wr_reqGen_intermediateBuffer2$EMPTY_N &&
	     m_fpga_wr_reqGen_outgoingBuffer$FULL_N ;
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  // rule RL_m_fpga_wr_placeRequest
  assign WILL_FIRE_RL_m_fpga_wr_placeRequest =
	     m_fpga_wr_master_wr_in_addr$FULL_N &&
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	     m_fpga_wr_beatsPerRequestFIFO$FULL_N &&
	     m_fpga_wr_task_data_requests_reg[125:68] != 58'd0 &&
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	     m_fpga_wr_incomingBuffer$EMPTY_N ;
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  // rule RL_m_fpga_wr_forwardData
  assign WILL_FIRE_RL_m_fpga_wr_forwardData =
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	     m_fpga_wr_incomingBuffer$EMPTY_N &&
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	     m_fpga_wr_beatsPerRequestFIFO$EMPTY_N &&
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	     m_fpga_wr_master_wr_in_data$FULL_N &&
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	     m_fpga_wr_task_data_output_reg[64:7] != 58'd0 ;
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  // rule RL_m_fpga_rd_fillBuffer
  assign WILL_FIRE_RL_m_fpga_rd_fillBuffer =
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	     m_fpga_rd_reqGen_outgoingBuffer$EMPTY_N &&
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	     m_fpga_rd_task_data_output_reg[64:7] == 58'd0 &&
	     m_fpga_rd_task_data_requests_reg[125:68] == 58'd0 ;
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  // rule RL_m_fpga_rd_reqGen_finishRequest
  assign WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest =
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	     m_fpga_rd_reqGen_intermediateBuffer2$EMPTY_N &&
	     m_fpga_rd_reqGen_outgoingBuffer$FULL_N ;
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  // rule RL_m_fpga_rd_placeRequest
  assign WILL_FIRE_RL_m_fpga_rd_placeRequest =
	     m_fpga_rd_master_rd_in$FULL_N &&
	     m_fpga_rd_task_data_requests_reg[125:68] != 58'd0 ;
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  // rule RL_m_fpga_rd_forwardData
  assign WILL_FIRE_RL_m_fpga_rd_forwardData =
	     m_fpga_rd_master_rd_out$EMPTY_N &&
	     m_fpga_rd_outgoingBuffer$FULL_N &&
	     m_fpga_rd_task_data_output_reg[64:7] != 58'd0 ;

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  // rule RL_mkConnectionGetPut_2
  assign WILL_FIRE_RL_mkConnectionGetPut_2 =
	     !readConvBTT_ff$dEMPTY_N && !readConverter_bufferEmpty &&
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	     m_pcie_wr_incomingBuffer$FULL_N &&
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	     !readConvBTT_ff$dEMPTY_N ;

  // rule RL_mkConnectionGetPut_1
  assign WILL_FIRE_RL_mkConnectionGetPut_1 =
	     !readConvBTT_ff$dEMPTY_N &&
	     readConverter_bufferEmpty$port1__read &&
	     fpga_response_converter$dEMPTY_N &&
	     !readConvBTT_ff$dEMPTY_N ;

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  // rule RL_byteAlignerReader_forwardOutput
  assign WILL_FIRE_RL_byteAlignerReader_forwardOutput =
	     byteAlignerReader_outgoing$FULL_N &&
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	     !byteAlignerReader_addr_ff$dEMPTY_N &&
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	     byteAlignerReader_fetchedDatum &&
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	     !byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 &&
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	     !byteAlignerReader_addr_ff$dEMPTY_N ;
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  // rule RL_byteAlignerReader_fetchNewData
  assign WILL_FIRE_RL_byteAlignerReader_fetchNewData =
	     byteAlignerReader_incoming$EMPTY_N &&
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	     !byteAlignerReader_addr_ff$dEMPTY_N &&
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	     !byteAlignerReader_fetchedDatum$port1__read &&
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	     byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 &&
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	     !byteAlignerReader_addr_ff$dEMPTY_N ;

  // rule RL_byteAlignerReader_forwardOutputLast
  assign CAN_FIRE_RL_byteAlignerReader_forwardOutputLast =
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	     byteAlignerReader_outgoing$FULL_N &&
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	     !byteAlignerReader_addr_ff$dEMPTY_N &&
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	     !byteAlignerReader_fetchedDatum &&
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	     !byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 &&
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	     byteAlignerReader_bytes_out < byteAlignerReader_bytes_total ;
  assign WILL_FIRE_RL_byteAlignerReader_forwardOutputLast =
	     CAN_FIRE_RL_byteAlignerReader_forwardOutputLast &&
	     !byteAlignerReader_addr_ff$dEMPTY_N ;
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  // rule RL_mkConnectionGetPut_3
  assign WILL_FIRE_RL_mkConnectionGetPut_3 =
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	     !writeConvBTT_ff$dEMPTY_N && m_pcie_rd_outgoingBuffer$EMPTY_N &&
	     writeConverter_dataSync$FULL_N &&
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	     !writeConvBTT_ff$dEMPTY_N ;

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  // rule RL_byteAlignerWriter_forwardOutput
  assign WILL_FIRE_RL_byteAlignerWriter_forwardOutput =
	     byteAlignerWriter_outgoing$FULL_N &&
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	     !byteAlignerWriter_addr_ff$dEMPTY_N &&
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	     byteAlignerWriter_fetchedDatum &&
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	     !byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1577 &&
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	     !byteAlignerWriter_addr_ff$dEMPTY_N ;
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  // rule RL_byteAlignerWriter_fetchNewData
  assign WILL_FIRE_RL_byteAlignerWriter_fetchNewData =
	     byteAlignerWriter_incoming$EMPTY_N &&
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	     !byteAlignerWriter_addr_ff$dEMPTY_N &&
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	     !byteAlignerWriter_fetchedDatum$port1__read &&
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	     byteAlignerWriter_bytes_in_560_ULT_byteAligner_ETC___d1562 &&
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	     !byteAlignerWriter_addr_ff$dEMPTY_N ;

  // rule RL_byteAlignerWriter_forwardOutputLast
  assign CAN_FIRE_RL_byteAlignerWriter_forwardOutputLast =
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	     byteAlignerWriter_outgoing$FULL_N &&
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	     !byteAlignerWriter_addr_ff$dEMPTY_N &&
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	     !byteAlignerWriter_fetchedDatum &&
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	     !byteAlignerWriter_bytes_in_560_ULT_byteAligner_ETC___d1562 &&
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	     byteAlignerWriter_bytes_out < byteAlignerWriter_bytes_total ;
  assign WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast =
	     CAN_FIRE_RL_byteAlignerWriter_forwardOutputLast &&
	     !byteAlignerWriter_addr_ff$dEMPTY_N ;
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  // inputs to muxes for submodule ports
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  assign MUX_cycles_between$write_1__SEL_1 =
	     WILL_FIRE_RL_setInterrupt &&
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	     pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681 ;
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  assign MUX_opInProgress$write_1__SEL_2 =
	     WILL_FIRE_RL_handleRead || WILL_FIRE_RL_handleWrite ;
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  assign MUX_byteAlignerReader_buffer$port0__write_1__VAL_1 =
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	     { 256'd0, byteAlignerReader_buffer[511:256] } ;
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  assign MUX_byteAlignerReader_bytes_in$write_1__VAL_1 =
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	     byteAlignerReader_bytes_in + 64'd32 ;
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  assign MUX_byteAlignerReader_bytes_left_in_buffer$port0__write_1__VAL_1 =
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	     byteAlignerReader_bytes_left_in_buffer -
	     byteAlignerReader_bytes_out_needed ;
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  assign MUX_byteAlignerReader_bytes_out$write_1__VAL_1 =
	     byteAlignerReader_bytes_out +
	     { 58'd0, byteAlignerReader_bytes_out_needed } ;
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  assign MUX_byteAlignerReader_bytes_out$write_1__VAL_2 =
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	     byteAlignerReader_bytes_out + 64'd256 ;
  assign MUX_byteAlignerReader_bytes_out_needed$write_1__VAL_1 =
	     6'd32 - { 1'd0, byteAlignerReader_addr_ff$dD_OUT[68:64] } ;
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  assign MUX_byteAlignerWriter_buffer$port0__write_1__VAL_1 =
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	     { 256'd0, byteAlignerWriter_buffer[511:256] } ;
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  assign MUX_byteAlignerWriter_bytes_in$write_1__VAL_1 =
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	     byteAlignerWriter_bytes_in + 64'd32 ;
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  assign MUX_byteAlignerWriter_bytes_left_in_buffer$port0__write_1__VAL_1 =
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	     byteAlignerWriter_bytes_left_in_buffer -
	     byteAlignerWriter_bytes_out_needed ;
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  assign MUX_byteAlignerWriter_bytes_out$write_1__VAL_1 =
	     byteAlignerWriter_bytes_out +
	     { 58'd0, byteAlignerWriter_bytes_out_needed } ;
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  assign MUX_byteAlignerWriter_bytes_out$write_1__VAL_2 =
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	     byteAlignerWriter_bytes_out + 64'd256 ;
  assign MUX_byteAlignerWriter_bytes_out_needed$write_1__VAL_1 =
	     6'd32 - { 1'd0, byteAlignerWriter_addr_ff$dD_OUT[68:64] } ;
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  assign MUX_cycles_between$write_1__VAL_1 =
	     { 32'd0, clkCntr - pc_betweenStart } ;
  assign MUX_cycles_between$write_1__VAL_2 =
	     { s_config_writeSlave_in$D_OUT[10] ?
		 s_config_writeSlave_in$D_OUT[74:67] :
		 cycles_between[63:56],
	       s_config_writeSlave_in$D_OUT[9] ?
		 s_config_writeSlave_in$D_OUT[66:59] :
		 cycles_between[55:48],
	       s_config_writeSlave_in$D_OUT[8] ?
		 s_config_writeSlave_in$D_OUT[58:51] :
		 cycles_between[47:40],
	       s_config_writeSlave_in$D_OUT[7] ?
		 s_config_writeSlave_in$D_OUT[50:43] :
		 cycles_between[39:32],
	       s_config_writeSlave_in$D_OUT[6] ?
		 s_config_writeSlave_in$D_OUT[42:35] :
		 cycles_between[31:24],
	       s_config_writeSlave_in$D_OUT[5] ?
		 s_config_writeSlave_in$D_OUT[34:27] :
		 cycles_between[23:16],
	       s_config_writeSlave_in$D_OUT[4] ?
		 s_config_writeSlave_in$D_OUT[26:19] :
		 cycles_between[15:8],
	       s_config_writeSlave_in$D_OUT[3] ?
		 s_config_writeSlave_in$D_OUT[18:11] :
		 cycles_between[7:0] } ;
  assign MUX_cycles_last_request$write_1__VAL_1 =
	     { 32'd0, clkCntr - pc_start } ;
  assign MUX_cycles_last_request$write_1__VAL_2 =
	     { s_config_writeSlave_in$D_OUT[10] ?
		 s_config_writeSlave_in$D_OUT[74:67] :
		 cycles_last_request[63:56],
	       s_config_writeSlave_in$D_OUT[9] ?
		 s_config_writeSlave_in$D_OUT[66:59] :
		 cycles_last_request[55:48],
	       s_config_writeSlave_in$D_OUT[8] ?
		 s_config_writeSlave_in$D_OUT[58:51] :
		 cycles_last_request[47:40],
	       s_config_writeSlave_in$D_OUT[7] ?
		 s_config_writeSlave_in$D_OUT[50:43] :
		 cycles_last_request[39:32],
	       s_config_writeSlave_in$D_OUT[6] ?
		 s_config_writeSlave_in$D_OUT[42:35] :
		 cycles_last_request[31:24],
	       s_config_writeSlave_in$D_OUT[5] ?
		 s_config_writeSlave_in$D_OUT[34:27] :
		 cycles_last_request[23:16],
	       s_config_writeSlave_in$D_OUT[4] ?
		 s_config_writeSlave_in$D_OUT[26:19] :
		 cycles_last_request[15:8],
	       s_config_writeSlave_in$D_OUT[3] ?
		 s_config_writeSlave_in$D_OUT[18:11] :
		 cycles_last_request[7:0] } ;
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  assign MUX_m_fpga_rd_task_data_output_reg$write_1__VAL_1 =
	     { m_fpga_rd_task_data_output_reg[76:65],
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	       x_transfers_total__h58416,
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	       m_fpga_rd_task_data_output_reg[6:0] } ;
  assign MUX_m_fpga_rd_task_data_requests_reg$write_1__VAL_1 =
	     { m_fpga_rd_task_data_requests_reg[133:126],
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	       x_requests_total__h57966,
	       x_address__h57967,
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	       m_fpga_rd_task_data_requests_reg[3:0] } ;
  assign MUX_m_fpga_wr_beatsThisRequestCntr$write_1__VAL_1 =
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	     m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929 ?
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	       8'd0 :
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	       beatsThisRequestCntrT__h43807 ;
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  assign MUX_m_fpga_wr_task_data_output_reg$write_1__VAL_1 =
	     { m_fpga_wr_task_data_output_reg[76:65],
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	       x_transfers_total__h54839,
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	       m_fpga_wr_task_data_output_reg[6:1],
	       1'd0 } ;
  assign MUX_m_fpga_wr_task_data_requests_reg$write_1__VAL_1 =
	     { m_fpga_wr_task_data_requests_reg[133:126],
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	       x_requests_total__h43404,
	       x_address__h43405,
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	       m_fpga_wr_task_data_requests_reg[3:0] } ;
  assign MUX_m_pcie_rd_task_data_output_reg$write_1__VAL_1 =
	     { m_pcie_rd_task_data_output_reg[74:65],
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	       x_transfers_total__h39183,
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	       m_pcie_rd_task_data_output_reg[5:0] } ;
  assign MUX_m_pcie_rd_task_data_requests_reg$write_1__VAL_1 =
	     { m_pcie_rd_task_data_requests_reg[134:127],
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	       x_requests_total__h38733,
	       x_address__h38734,
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	       m_pcie_rd_task_data_requests_reg[3:0] } ;
  assign MUX_m_pcie_wr_beatsThisRequestCntr$write_1__VAL_1 =
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	       8'd0 :
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	       beatsThisRequestCntrT__h29979 ;
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  assign MUX_m_pcie_wr_task_data_output_reg$write_1__VAL_1 =
	     { m_pcie_wr_task_data_output_reg[74:65],
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	       x_transfers_total__h35603,
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	       m_pcie_wr_task_data_output_reg[5:1],
	       1'd0 } ;
  assign MUX_m_pcie_wr_task_data_requests_reg$write_1__VAL_1 =
	     { m_pcie_wr_task_data_requests_reg[134:127],
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	       x_requests_total__h29576,
	       x_address__h29577,
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	       m_pcie_wr_task_data_requests_reg[3:0] } ;
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  assign MUX_readConverter_byteCntr$write_1__VAL_2 =
	     readConverter_byteCntr - 64'd32 ;
  assign MUX_s_config_readSlave_out$enq_1__VAL_1 = { host_addr, 2'd0 } ;
  assign MUX_s_config_readSlave_out$enq_1__VAL_2 = { fpga_addr, 2'd0 } ;
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  assign MUX_s_config_readSlave_out$enq_1__VAL_3 =
	     { cycles_last_request, 2'd0 } ;
  assign MUX_s_config_readSlave_out$enq_1__VAL_4 = { cycles_between, 2'd0 } ;
  assign MUX_s_config_readSlave_out$enq_1__VAL_5 =
	     { cycles_between_set, 2'd0 } ;
  assign MUX_s_config_readSlave_out$enq_1__VAL_6 = { id, 2'd0 } ;
  assign MUX_s_config_readSlave_out$enq_1__VAL_7 = { transfer_length, 2'd0 } ;
  assign MUX_s_config_readSlave_out$enq_1__VAL_8 = { read_requests, 2'd0 } ;
  assign MUX_s_config_readSlave_out$enq_1__VAL_9 = { write_requests, 2'd0 } ;
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  assign MUX_writeConverter_byteCntr$write_1__VAL_2 =
	     writeConverter_byteCntr - 64'd32 ;
  assign MUX_writeConverter_wordInCntr$write_1__VAL_1 =
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	     { 1'd0, writeConvBTT_ff$dD_OUT[0] } ;
  assign MUX_writeConverter_wordInCntr$write_1__VAL_2 =
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	     (writeConverter_wordInCntr == 2'd1 ||
	      writeConverter_byteCntr <= 64'd32) ?
	       2'd0 :
	       writeConverter_wordInCntr + 2'd1 ;

  // inlined wires
  assign s_config_readIsHandled$whas =
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_8 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_7 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_5 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled ;
  assign s_config_writeIsHandled$whas =
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	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_6 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_4 ||
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	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 ||
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	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 ||
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	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_1 ||
	     WILL_FIRE_RL_s_config_axiReadSpecialIsHandled ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecialIsHandled ;
  always@(m_pcie_wr_master_wr_in_addr$D_OUT)
  begin
    case (m_pcie_wr_master_wr_in_addr$D_OUT[15:12])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd6, 4'd7, 4'd14:
	  m_pcie_wr_master_wr_wawcache$wget =
	      m_pcie_wr_master_wr_in_addr$D_OUT[15:12];
      default: m_pcie_wr_master_wr_wawcache$wget = 4'd15;
    endcase
  end
  always@(m_pcie_rd_master_rd_in$D_OUT)
  begin
    case (m_pcie_rd_master_rd_in$D_OUT[15:12])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd10, 4'd14, 4'd15:
	  m_pcie_rd_master_rd_warcache$wget =
	      m_pcie_rd_master_rd_in$D_OUT[15:12];
      default: m_pcie_rd_master_rd_warcache$wget = 4'd11;
    endcase
  end
  always@(m_fpga_wr_master_wr_in_addr$D_OUT)
  begin
    case (m_fpga_wr_master_wr_in_addr$D_OUT[15:12])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd6, 4'd7, 4'd14:
	  m_fpga_wr_master_wr_wawcache$wget =
	      m_fpga_wr_master_wr_in_addr$D_OUT[15:12];
      default: m_fpga_wr_master_wr_wawcache$wget = 4'd15;
    endcase
  end
  always@(m_fpga_rd_master_rd_in$D_OUT)
  begin
    case (m_fpga_rd_master_rd_in$D_OUT[15:12])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd10, 4'd14, 4'd15:
	  m_fpga_rd_master_rd_warcache$wget =
	      m_fpga_rd_master_rd_in$D_OUT[15:12];
      default: m_fpga_rd_master_rd_warcache$wget = 4'd11;
    endcase
  end
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  assign m_pcie_wr_master_wr_rinpkg$wget =
	     { pcie_wr_bid, pcie_wr_bresp, pcie_wr_buser } ;
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  assign m_pcie_rd_master_rd_rinpkg$wget =
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	     { pcie_rd_rid,
	       pcie_rd_rdata,
	       pcie_rd_rresp,
	       pcie_rd_rlast,
	       pcie_rd_ruser } ;
  assign m_fpga_wr_master_wr_rinpkg$wget =
	     { fpga_wr_bid, fpga_wr_bresp, fpga_wr_buser } ;
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  assign m_fpga_rd_master_rd_rinpkg$wget =
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	     { fpga_rd_rid,
	       fpga_rd_rdata,
	       fpga_rd_rresp,
	       fpga_rd_rlast,
	       fpga_rd_ruser } ;
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  assign s_config_writeSlave_addrIn_rv$EN_port0__write =
	     !s_config_writeSlave_addrIn_rv[67] && S_AXI_awvalid ;
  assign s_config_writeSlave_addrIn_rv$port0__write_1 =
	     { 1'd1, S_AXI_awaddr, S_AXI_awprot } ;
  assign s_config_writeSlave_addrIn_rv$port1__read =
	     s_config_writeSlave_addrIn_rv$EN_port0__write ?
	       s_config_writeSlave_addrIn_rv$port0__write_1 :
	       s_config_writeSlave_addrIn_rv ;
  assign s_config_writeSlave_addrIn_rv$EN_port1__write =
	     s_config_writeSlave_addrIn_rv$port1__read[67] &&
	     s_config_writeSlave_dataIn_rv$port1__read[72] &&
	     s_config_writeSlave_in$FULL_N ;
  assign s_config_writeSlave_addrIn_rv$port2__read =
	     s_config_writeSlave_addrIn_rv$EN_port1__write ?
	       68'h2AAAAAAAAAAAAAAAA :
	       s_config_writeSlave_addrIn_rv$port1__read ;
  assign s_config_writeSlave_dataIn_rv$EN_port0__write =
	     !s_config_writeSlave_dataIn_rv[72] && S_AXI_wvalid ;
  assign s_config_writeSlave_dataIn_rv$port0__write_1 =
	     { 1'd1, S_AXI_wdata, S_AXI_wstrb } ;
  assign s_config_writeSlave_dataIn_rv$port1__read =
	     s_config_writeSlave_dataIn_rv$EN_port0__write ?
	       s_config_writeSlave_dataIn_rv$port0__write_1 :
	       s_config_writeSlave_dataIn_rv ;
  assign s_config_writeSlave_dataIn_rv$EN_port1__write =
	     s_config_writeSlave_addrIn_rv$port1__read[67] &&
	     s_config_writeSlave_dataIn_rv$port1__read[72] &&
	     s_config_writeSlave_in$FULL_N ;
  assign s_config_writeSlave_dataIn_rv$port2__read =
	     s_config_writeSlave_dataIn_rv$EN_port1__write ?
	       73'h0AAAAAAAAAAAAAAAAAA :
	       s_config_writeSlave_dataIn_rv$port1__read ;
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  assign readIn_rv$port1__read =
	     WILL_FIRE_RL_handleRead ?
	       193'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
	       readIn_rv ;
  assign readIn_rv$EN_port1__write =
	     cmdsIn$EMPTY_N && !readIn_rv$port1__read[192] && !cmdsIn$D_OUT ;
  assign readIn_rv$port1__write_1 =
	     { 1'd1, host_addr, fpga_addr, transfer_length } ;
  assign readIn_rv$port2__read =
	     readIn_rv$EN_port1__write ?
	       readIn_rv$port1__write_1 :
	       readIn_rv$port1__read ;
  assign writeIn_rv$port1__read =
	     WILL_FIRE_RL_handleWrite ?
	       193'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
	       writeIn_rv ;
  assign writeIn_rv$EN_port1__write =
	     cmdsIn$EMPTY_N && !writeIn_rv$port1__read[192] && cmdsIn$D_OUT ;
  assign writeIn_rv$port2__read =
	     writeIn_rv$EN_port1__write ?
	       readIn_rv$port1__write_1 :
	       writeIn_rv$port1__read ;
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  assign readConverter_bufferEmpty$EN_port0__write =
	     WILL_FIRE_RL_mkConnectionGetPut_2 &&
	     ({ 1'd0, readConverter_wordInCntr } == 2'd1 ||
	      readConverter_byteCntr <= 64'd32) ;
  assign readConverter_bufferEmpty$port1__read =
	     readConverter_bufferEmpty$EN_port0__write ||
	     readConverter_bufferEmpty ;
  assign readConverter_bufferEmpty$EN_port1__write =
	     WILL_FIRE_RL_mkConnectionGetPut_1 || readConvBTT_ff$dEMPTY_N ;
  assign readConverter_bufferEmpty$port2__read =
	     readConverter_bufferEmpty$EN_port1__write ?
	       !WILL_FIRE_RL_mkConnectionGetPut_1 :
	       readConverter_bufferEmpty$port1__read ;
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  assign byteAlignerReader_buffer$EN_port0__write =
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	     WILL_FIRE_RL_byteAlignerReader_forwardOutput ||
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	     byteAlignerReader_addr_ff$dEMPTY_N ;
  assign byteAlignerReader_buffer$port0__write_1 =
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	     WILL_FIRE_RL_byteAlignerReader_forwardOutput ?
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	       MUX_byteAlignerReader_buffer$port0__write_1__VAL_1 :
	       512'd0 ;
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  assign byteAlignerReader_buffer$port1__read =
	     byteAlignerReader_buffer$EN_port0__write ?
	       byteAlignerReader_buffer$port0__write_1 :
	       byteAlignerReader_buffer ;
  assign byteAlignerReader_buffer$port1__write_1 =
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	     { byteAlignerReader_buffer$port1__read[511:256],
	       byteAlignerReader_incoming$D_OUT } ;
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  assign byteAlignerReader_buffer$port2__read =
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	     WILL_FIRE_RL_byteAlignerReader_fetchNewData ?
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	       byteAlignerReader_buffer$port1__write_1 :
	       byteAlignerReader_buffer$port1__read ;
  assign byteAlignerReader_bytes_left_in_buffer$EN_port0__write =
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	     WILL_FIRE_RL_byteAlignerReader_forwardOutput ||
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	     byteAlignerReader_addr_ff$dEMPTY_N ;
  assign byteAlignerReader_bytes_left_in_buffer$port0__write_1 =
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	     WILL_FIRE_RL_byteAlignerReader_forwardOutput ?
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	       MUX_byteAlignerReader_bytes_left_in_buffer$port0__write_1__VAL_1 :
	       6'd0 ;
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  assign byteAlignerReader_bytes_left_in_buffer$port1__write_1 =
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	     b__h72292 + 6'd32 ;
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  assign byteAlignerReader_bytes_left_in_buffer$port2__read =
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	     WILL_FIRE_RL_byteAlignerReader_fetchNewData ?
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	       byteAlignerReader_bytes_left_in_buffer$port1__write_1 :
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	       b__h72292 ;
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  assign byteAlignerReader_fetchedDatum$EN_port0__write =
	     byteAlignerReader_addr_ff$dEMPTY_N ||
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	     !byteAlignerReader_addr_ff$dEMPTY_N &&
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	     byteAlignerReader_fetchedDatum &&
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	     byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 ||
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	     WILL_FIRE_RL_byteAlignerReader_forwardOutput ;
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  assign byteAlignerReader_fetchedDatum$port1__read =
	     !byteAlignerReader_fetchedDatum$EN_port0__write &&
	     byteAlignerReader_fetchedDatum ;
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  assign byteAlignerReader_fetchedDatum$port2__read =
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	     WILL_FIRE_RL_byteAlignerReader_fetchNewData ||
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	     byteAlignerReader_fetchedDatum$port1__read ;
  assign byteAlignerWriter_buffer$EN_port0__write =
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	     WILL_FIRE_RL_byteAlignerWriter_forwardOutput ||
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	     byteAlignerWriter_addr_ff$dEMPTY_N ;
  assign byteAlignerWriter_buffer$port0__write_1 =
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	     WILL_FIRE_RL_byteAlignerWriter_forwardOutput ?
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	       MUX_byteAlignerWriter_buffer$port0__write_1__VAL_1 :
	       512'd0 ;
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  assign byteAlignerWriter_buffer$port1__read =
	     byteAlignerWriter_buffer$EN_port0__write ?
	       byteAlignerWriter_buffer$port0__write_1 :
	       byteAlignerWriter_buffer ;
  assign byteAlignerWriter_buffer$port1__write_1 =
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	     { byteAlignerWriter_buffer$port1__read[511:256],
	       byteAlignerWriter_incoming$D_OUT } ;
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  assign byteAlignerWriter_buffer$port2__read =
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	     WILL_FIRE_RL_byteAlignerWriter_fetchNewData ?
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	       byteAlignerWriter_buffer$port1__write_1 :
	       byteAlignerWriter_buffer$port1__read ;
  assign byteAlignerWriter_bytes_left_in_buffer$EN_port0__write =
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	     WILL_FIRE_RL_byteAlignerWriter_forwardOutput ||
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	     byteAlignerWriter_addr_ff$dEMPTY_N ;
  assign byteAlignerWriter_bytes_left_in_buffer$port0__write_1 =
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	     WILL_FIRE_RL_byteAlignerWriter_forwardOutput ?
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	       MUX_byteAlignerWriter_bytes_left_in_buffer$port0__write_1__VAL_1 :
	       6'd0 ;
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  assign byteAlignerWriter_bytes_left_in_buffer$port1__write_1 =
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	     b__h115475 + 6'd32 ;
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  assign byteAlignerWriter_bytes_left_in_buffer$port2__read =
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	     WILL_FIRE_RL_byteAlignerWriter_fetchNewData ?
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	       byteAlignerWriter_bytes_left_in_buffer$port1__write_1 :
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	       b__h115475 ;
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  assign byteAlignerWriter_fetchedDatum$EN_port0__write =
	     byteAlignerWriter_addr_ff$dEMPTY_N ||
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	     !byteAlignerWriter_addr_ff$dEMPTY_N &&
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	     byteAlignerWriter_fetchedDatum &&
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	     byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1577 ||
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	     WILL_FIRE_RL_byteAlignerWriter_forwardOutput ;
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  assign byteAlignerWriter_fetchedDatum$port1__read =
	     !byteAlignerWriter_fetchedDatum$EN_port0__write &&
	     byteAlignerWriter_fetchedDatum ;
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  assign byteAlignerWriter_fetchedDatum$port2__read =
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	     WILL_FIRE_RL_byteAlignerWriter_fetchNewData ||
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	     byteAlignerWriter_fetchedDatum$port1__read ;

  // register byteAlignerReader_buffer
  assign byteAlignerReader_buffer$D_IN =
	     byteAlignerReader_buffer$port2__read ;
  assign byteAlignerReader_buffer$EN = 1'b1 ;

  // register byteAlignerReader_bytes_in
  assign byteAlignerReader_bytes_in$D_IN =
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	     WILL_FIRE_RL_byteAlignerReader_fetchNewData ?
	       MUX_byteAlignerReader_bytes_in$write_1__VAL_1 :
	       64'd0 ;
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  assign byteAlignerReader_bytes_in$EN =
	     WILL_FIRE_RL_byteAlignerReader_fetchNewData ||
	     byteAlignerReader_addr_ff$dEMPTY_N ;

  // register byteAlignerReader_bytes_left_in_buffer
  assign byteAlignerReader_bytes_left_in_buffer$D_IN =
	     byteAlignerReader_bytes_left_in_buffer$port2__read ;
  assign byteAlignerReader_bytes_left_in_buffer$EN = 1'b1 ;

  // register byteAlignerReader_bytes_out
  always@(WILL_FIRE_RL_byteAlignerReader_forwardOutput or
	  MUX_byteAlignerReader_bytes_out$write_1__VAL_1 or
	  WILL_FIRE_RL_byteAlignerReader_forwardOutputLast or
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	  MUX_byteAlignerReader_bytes_out$write_1__VAL_2 or
	  byteAlignerReader_addr_ff$dEMPTY_N)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_byteAlignerReader_forwardOutput:
	  byteAlignerReader_bytes_out$D_IN =
	      MUX_byteAlignerReader_bytes_out$write_1__VAL_1;
      WILL_FIRE_RL_byteAlignerReader_forwardOutputLast:
	  byteAlignerReader_bytes_out$D_IN =
	      MUX_byteAlignerReader_bytes_out$write_1__VAL_2;
      byteAlignerReader_addr_ff$dEMPTY_N:
	  byteAlignerReader_bytes_out$D_IN = 64'd0;
      default: byteAlignerReader_bytes_out$D_IN =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
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  assign byteAlignerReader_bytes_out$EN =
	     WILL_FIRE_RL_byteAlignerReader_forwardOutput ||
	     WILL_FIRE_RL_byteAlignerReader_forwardOutputLast ||
	     byteAlignerReader_addr_ff$dEMPTY_N ;

  // register byteAlignerReader_bytes_out_needed
  assign byteAlignerReader_bytes_out_needed$D_IN =
	     byteAlignerReader_addr_ff$dEMPTY_N ?
	       MUX_byteAlignerReader_bytes_out_needed$write_1__VAL_1 :
	       6'd32 ;
  assign byteAlignerReader_bytes_out_needed$EN =
	     byteAlignerReader_addr_ff$dEMPTY_N ||
	     WILL_FIRE_RL_byteAlignerReader_forwardOutput ;

  // register byteAlignerReader_bytes_total
  assign byteAlignerReader_bytes_total$D_IN =
	     byteAlignerReader_addr_ff$dD_OUT[63:0] ;
  assign byteAlignerReader_bytes_total$EN =
	     byteAlignerReader_addr_ff$dEMPTY_N ;

  // register byteAlignerReader_fetchedDatum
  assign byteAlignerReader_fetchedDatum$D_IN =
	     byteAlignerReader_fetchedDatum$port2__read ;
  assign byteAlignerReader_fetchedDatum$EN = 1'b1 ;

  // register byteAlignerWriter_buffer
  assign byteAlignerWriter_buffer$D_IN =
	     byteAlignerWriter_buffer$port2__read ;
  assign byteAlignerWriter_buffer$EN = 1'b1 ;

  // register byteAlignerWriter_bytes_in
  assign byteAlignerWriter_bytes_in$D_IN =
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	     WILL_FIRE_RL_byteAlignerWriter_fetchNewData ?
	       MUX_byteAlignerWriter_bytes_in$write_1__VAL_1 :
	       64'd0 ;
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  assign byteAlignerWriter_bytes_in$EN =
	     WILL_FIRE_RL_byteAlignerWriter_fetchNewData ||
	     byteAlignerWriter_addr_ff$dEMPTY_N ;

  // register byteAlignerWriter_bytes_left_in_buffer
  assign byteAlignerWriter_bytes_left_in_buffer$D_IN =
	     byteAlignerWriter_bytes_left_in_buffer$port2__read ;
  assign byteAlignerWriter_bytes_left_in_buffer$EN = 1'b1 ;

  // register byteAlignerWriter_bytes_out
  always@(WILL_FIRE_RL_byteAlignerWriter_forwardOutput or
	  MUX_byteAlignerWriter_bytes_out$write_1__VAL_1 or
	  WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast or
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	  MUX_byteAlignerWriter_bytes_out$write_1__VAL_2 or
	  byteAlignerWriter_addr_ff$dEMPTY_N)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_byteAlignerWriter_forwardOutput:
	  byteAlignerWriter_bytes_out$D_IN =
	      MUX_byteAlignerWriter_bytes_out$write_1__VAL_1;
      WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast:
	  byteAlignerWriter_bytes_out$D_IN =
	      MUX_byteAlignerWriter_bytes_out$write_1__VAL_2;
      byteAlignerWriter_addr_ff$dEMPTY_N:
	  byteAlignerWriter_bytes_out$D_IN = 64'd0;
      default: byteAlignerWriter_bytes_out$D_IN =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
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  assign byteAlignerWriter_bytes_out$EN =
	     WILL_FIRE_RL_byteAlignerWriter_forwardOutput ||
	     WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast ||
	     byteAlignerWriter_addr_ff$dEMPTY_N ;

  // register byteAlignerWriter_bytes_out_needed
  assign byteAlignerWriter_bytes_out_needed$D_IN =
	     byteAlignerWriter_addr_ff$dEMPTY_N ?
	       MUX_byteAlignerWriter_bytes_out_needed$write_1__VAL_1 :
	       6'd32 ;
  assign byteAlignerWriter_bytes_out_needed$EN =
	     byteAlignerWriter_addr_ff$dEMPTY_N ||
	     WILL_FIRE_RL_byteAlignerWriter_forwardOutput ;

  // register byteAlignerWriter_bytes_total
  assign byteAlignerWriter_bytes_total$D_IN =
	     byteAlignerWriter_addr_ff$dD_OUT[63:0] ;
  assign byteAlignerWriter_bytes_total$EN =
	     byteAlignerWriter_addr_ff$dEMPTY_N ;

  // register byteAlignerWriter_fetchedDatum
  assign byteAlignerWriter_fetchedDatum$D_IN =
	     byteAlignerWriter_fetchedDatum$port2__read ;
  assign byteAlignerWriter_fetchedDatum$EN = 1'b1 ;

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  // register clkCntr
  assign clkCntr$D_IN = clkCntr + 32'd1 ;
  assign clkCntr$EN = 1'd1 ;

  // register cycles_between
  assign cycles_between$D_IN =
	     MUX_cycles_between$write_1__SEL_1 ?
	       MUX_cycles_between$write_1__VAL_1 :
	       MUX_cycles_between$write_1__VAL_2 ;
  assign cycles_between$EN =
	     WILL_FIRE_RL_setInterrupt &&
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	     pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681 ||
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	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 ;

  // register cycles_between_set
  assign cycles_between_set$D_IN =
	     { s_config_writeSlave_in$D_OUT[10] ?
		 s_config_writeSlave_in$D_OUT[74:67] :
		 cycles_between_set[63:56],
	       s_config_writeSlave_in$D_OUT[9] ?
		 s_config_writeSlave_in$D_OUT[66:59] :
		 cycles_between_set[55:48],
	       s_config_writeSlave_in$D_OUT[8] ?
		 s_config_writeSlave_in$D_OUT[58:51] :
		 cycles_between_set[47:40],
	       s_config_writeSlave_in$D_OUT[7] ?
		 s_config_writeSlave_in$D_OUT[50:43] :
		 cycles_between_set[39:32],
	       s_config_writeSlave_in$D_OUT[6] ?
		 s_config_writeSlave_in$D_OUT[42:35] :
		 cycles_between_set[31:24],
	       s_config_writeSlave_in$D_OUT[5] ?
		 s_config_writeSlave_in$D_OUT[34:27] :
		 cycles_between_set[23:16],
	       s_config_writeSlave_in$D_OUT[4] ?
		 s_config_writeSlave_in$D_OUT[26:19] :
		 cycles_between_set[15:8],
	       s_config_writeSlave_in$D_OUT[3] ?
		 s_config_writeSlave_in$D_OUT[18:11] :
		 cycles_between_set[7:0] } ;
  assign cycles_between_set$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 ;

  // register cycles_last_request
  assign cycles_last_request$D_IN =
	     WILL_FIRE_RL_setInterrupt ?
	       MUX_cycles_last_request$write_1__VAL_1 :
	       MUX_cycles_last_request$write_1__VAL_2 ;
  assign cycles_last_request$EN =
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 ||
	     WILL_FIRE_RL_setInterrupt ;

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  // register doneInterruptReg
  assign doneInterruptReg$D_IN = WILL_FIRE_RL_setInterrupt ;
  assign doneInterruptReg$EN = 1'd1 ;

  // register fpgaLastCycle
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  assign fpgaLastCycle$D_IN =
	     m_fpga_rd_task_data_output_reg[64:7] != 58'd0 ||
	     m_fpga_rd_task_data_requests_reg[125:68] != 58'd0 ||
	     m_fpga_wr_task_data_output_reg[64:7] != 58'd0 ||
	     m_fpga_wr_task_data_requests_reg[125:68] != 58'd0 ;
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  assign fpgaLastCycle$EN = fpgaDone$sFULL_N ;

  // register fpga_addr
  assign fpga_addr$D_IN =
	     { s_config_writeSlave_in$D_OUT[10] ?
		 s_config_writeSlave_in$D_OUT[74:67] :
		 fpga_addr[63:56],
	       s_config_writeSlave_in$D_OUT[9] ?
		 s_config_writeSlave_in$D_OUT[66:59] :
		 fpga_addr[55:48],
	       s_config_writeSlave_in$D_OUT[8] ?
		 s_config_writeSlave_in$D_OUT[58:51] :
		 fpga_addr[47:40],
	       s_config_writeSlave_in$D_OUT[7] ?
		 s_config_writeSlave_in$D_OUT[50:43] :
		 fpga_addr[39:32],
	       s_config_writeSlave_in$D_OUT[6] ?
		 s_config_writeSlave_in$D_OUT[42:35] :
		 fpga_addr[31:24],
	       s_config_writeSlave_in$D_OUT[5] ?
		 s_config_writeSlave_in$D_OUT[34:27] :
		 fpga_addr[23:16],
	       s_config_writeSlave_in$D_OUT[4] ?
		 s_config_writeSlave_in$D_OUT[26:19] :
		 fpga_addr[15:8],
	       s_config_writeSlave_in$D_OUT[3] ?
		 s_config_writeSlave_in$D_OUT[18:11] :
		 fpga_addr[7:0] } ;
  assign fpga_addr$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 ;

  // register host_addr
  assign host_addr$D_IN =
	     { s_config_writeSlave_in$D_OUT[10] ?
		 s_config_writeSlave_in$D_OUT[74:67] :
		 host_addr[63:56],
	       s_config_writeSlave_in$D_OUT[9] ?
		 s_config_writeSlave_in$D_OUT[66:59] :
		 host_addr[55:48],
	       s_config_writeSlave_in$D_OUT[8] ?
		 s_config_writeSlave_in$D_OUT[58:51] :
		 host_addr[47:40],
	       s_config_writeSlave_in$D_OUT[7] ?
		 s_config_writeSlave_in$D_OUT[50:43] :
		 host_addr[39:32],
	       s_config_writeSlave_in$D_OUT[6] ?
		 s_config_writeSlave_in$D_OUT[42:35] :
		 host_addr[31:24],
	       s_config_writeSlave_in$D_OUT[5] ?
		 s_config_writeSlave_in$D_OUT[34:27] :
		 host_addr[23:16],
	       s_config_writeSlave_in$D_OUT[4] ?
		 s_config_writeSlave_in$D_OUT[26:19] :
		 host_addr[15:8],
	       s_config_writeSlave_in$D_OUT[3] ?
		 s_config_writeSlave_in$D_OUT[18:11] :
		 host_addr[7:0] } ;
  assign host_addr$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 ;

  // register id
  assign id$D_IN = 64'h0 ;
  assign id$EN = 1'b0 ;

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  // register isWriteActive
  assign isWriteActive$D_IN = !WILL_FIRE_RL_handleRead ;
  assign isWriteActive$EN = MUX_opInProgress$write_1__SEL_2 ;

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  // register m_fpga_rd_clkCntr
  assign m_fpga_rd_clkCntr$D_IN = m_fpga_rd_clkCntr + 32'd1 ;
  assign m_fpga_rd_clkCntr$EN = 1'd1 ;

  // register m_fpga_rd_lastPut
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  assign m_fpga_rd_lastPut$D_IN = 32'h0 ;
  assign m_fpga_rd_lastPut$EN = 1'b0 ;
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  // register m_fpga_rd_putDelay
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  assign m_fpga_rd_putDelay$D_IN = 32'h0 ;
  assign m_fpga_rd_putDelay$EN = 1'b0 ;

  // register m_fpga_rd_task_data_output_reg
  assign m_fpga_rd_task_data_output_reg$D_IN =
	     WILL_FIRE_RL_m_fpga_rd_forwardData ?
	       MUX_m_fpga_rd_task_data_output_reg$write_1__VAL_1 :
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	       m_fpga_rd_reqGen_outgoingBuffer$D_OUT[76:0] ;
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  assign m_fpga_rd_task_data_output_reg$EN =
	     WILL_FIRE_RL_m_fpga_rd_forwardData ||
	     WILL_FIRE_RL_m_fpga_rd_fillBuffer ;
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  // register m_fpga_rd_task_data_requests_reg
  assign m_fpga_rd_task_data_requests_reg$D_IN =
	     WILL_FIRE_RL_m_fpga_rd_placeRequest ?
	       MUX_m_fpga_rd_task_data_requests_reg$write_1__VAL_1 :
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	       m_fpga_rd_reqGen_outgoingBuffer$D_OUT[210:77] ;
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  assign m_fpga_rd_task_data_requests_reg$EN =
	     WILL_FIRE_RL_m_fpga_rd_placeRequest ||
	     WILL_FIRE_RL_m_fpga_rd_fillBuffer ;
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  // register m_fpga_rd_totalPuts
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  assign m_fpga_rd_totalPuts$D_IN = 32'h0 ;
  assign m_fpga_rd_totalPuts$EN = 1'b0 ;

  // register m_fpga_wr_beatsThisRequestCntr
  assign m_fpga_wr_beatsThisRequestCntr$D_IN =
	     WILL_FIRE_RL_m_fpga_wr_forwardData ?
	       MUX_m_fpga_wr_beatsThisRequestCntr$write_1__VAL_1 :
	       8'd0 ;
  assign m_fpga_wr_beatsThisRequestCntr$EN =
	     WILL_FIRE_RL_m_fpga_wr_forwardData ||
	     WILL_FIRE_RL_m_fpga_wr_fillBuffer ;
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  // register m_fpga_wr_clkCntr
  assign m_fpga_wr_clkCntr$D_IN = m_fpga_wr_clkCntr + 32'd1 ;
  assign m_fpga_wr_clkCntr$EN = 1'd1 ;

  // register m_fpga_wr_lastPut
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  assign m_fpga_wr_lastPut$D_IN = 32'h0 ;
  assign m_fpga_wr_lastPut$EN = 1'b0 ;
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  // register m_fpga_wr_putDelay
  assign m_fpga_wr_putDelay$D_IN = 32'h0 ;
  assign m_fpga_wr_putDelay$EN = 1'b0 ;

  // register m_fpga_wr_task_data_output_reg
  assign m_fpga_wr_task_data_output_reg$D_IN =
	     WILL_FIRE_RL_m_fpga_wr_forwardData ?
	       MUX_m_fpga_wr_task_data_output_reg$write_1__VAL_1 :
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	       m_fpga_wr_reqGen_outgoingBuffer$D_OUT[76:0] ;
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  assign m_fpga_wr_task_data_output_reg$EN =
	     WILL_FIRE_RL_m_fpga_wr_forwardData ||
	     WILL_FIRE_RL_m_fpga_wr_fillBuffer ;

  // register m_fpga_wr_task_data_requests_reg
  assign m_fpga_wr_task_data_requests_reg$D_IN =
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	     WILL_FIRE_RL_m_fpga_wr_placeRequest ?
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	       MUX_m_fpga_wr_task_data_requests_reg$write_1__VAL_1 :
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	       m_fpga_wr_reqGen_outgoingBuffer$D_OUT[210:77] ;
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  assign m_fpga_wr_task_data_requests_reg$EN =
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	     WILL_FIRE_RL_m_fpga_wr_placeRequest ||
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	     WILL_FIRE_RL_m_fpga_wr_fillBuffer ;
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  // register m_fpga_wr_totalPuts
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  assign m_fpga_wr_totalPuts$D_IN = 32'h0 ;
  assign m_fpga_wr_totalPuts$EN = 1'b0 ;
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  // register m_pcie_rd_clkCntr
  assign m_pcie_rd_clkCntr$D_IN = m_pcie_rd_clkCntr + 32'd1 ;
  assign m_pcie_rd_clkCntr$EN = 1'd1 ;

  // register m_pcie_rd_lastPut
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  assign m_pcie_rd_lastPut$D_IN = 32'h0 ;
  assign m_pcie_rd_lastPut$EN = 1'b0 ;
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  // register m_pcie_rd_putDelay
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  assign m_pcie_rd_putDelay$D_IN = 32'h0 ;
  assign m_pcie_rd_putDelay$EN = 1'b0 ;

  // register m_pcie_rd_task_data_output_reg
  assign m_pcie_rd_task_data_output_reg$D_IN =
	     WILL_FIRE_RL_m_pcie_rd_forwardData ?
	       MUX_m_pcie_rd_task_data_output_reg$write_1__VAL_1 :
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	       m_pcie_rd_reqGen_outgoingBuffer$D_OUT[74:0] ;
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  assign m_pcie_rd_task_data_output_reg$EN =
	     WILL_FIRE_RL_m_pcie_rd_forwardData ||
	     WILL_FIRE_RL_m_pcie_rd_fillBuffer ;
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  // register m_pcie_rd_task_data_requests_reg
  assign m_pcie_rd_task_data_requests_reg$D_IN =
	     WILL_FIRE_RL_m_pcie_rd_placeRequest ?
	       MUX_m_pcie_rd_task_data_requests_reg$write_1__VAL_1 :
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	       m_pcie_rd_reqGen_outgoingBuffer$D_OUT[209:75] ;
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  assign m_pcie_rd_task_data_requests_reg$EN =
	     WILL_FIRE_RL_m_pcie_rd_placeRequest ||
	     WILL_FIRE_RL_m_pcie_rd_fillBuffer ;
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  // register m_pcie_rd_totalPuts
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  assign m_pcie_rd_totalPuts$D_IN = 32'h0 ;
  assign m_pcie_rd_totalPuts$EN = 1'b0 ;

  // register m_pcie_wr_beatsThisRequestCntr
  assign m_pcie_wr_beatsThisRequestCntr$D_IN =
	     WILL_FIRE_RL_m_pcie_wr_forwardData ?
	       MUX_m_pcie_wr_beatsThisRequestCntr$write_1__VAL_1 :
	       8'd0 ;
  assign m_pcie_wr_beatsThisRequestCntr$EN =
	     WILL_FIRE_RL_m_pcie_wr_forwardData ||
	     WILL_FIRE_RL_m_pcie_wr_fillBuffer ;
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  // register m_pcie_wr_clkCntr
  assign m_pcie_wr_clkCntr$D_IN = m_pcie_wr_clkCntr + 32'd1 ;
  assign m_pcie_wr_clkCntr$EN = 1'd1 ;

  // register m_pcie_wr_lastPut
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  assign m_pcie_wr_lastPut$D_IN = 32'h0 ;
  assign m_pcie_wr_lastPut$EN = 1'b0 ;
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  // register m_pcie_wr_putDelay
  assign m_pcie_wr_putDelay$D_IN = 32'h0 ;
  assign m_pcie_wr_putDelay$EN = 1'b0 ;

  // register m_pcie_wr_task_data_output_reg
  assign m_pcie_wr_task_data_output_reg$D_IN =
	     WILL_FIRE_RL_m_pcie_wr_forwardData ?
	       MUX_m_pcie_wr_task_data_output_reg$write_1__VAL_1 :
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	       m_pcie_wr_reqGen_outgoingBuffer$D_OUT[74:0] ;
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  assign m_pcie_wr_task_data_output_reg$EN =
	     WILL_FIRE_RL_m_pcie_wr_forwardData ||
	     WILL_FIRE_RL_m_pcie_wr_fillBuffer ;

  // register m_pcie_wr_task_data_requests_reg
  assign m_pcie_wr_task_data_requests_reg$D_IN =
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	     WILL_FIRE_RL_m_pcie_wr_placeRequest ?
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	       MUX_m_pcie_wr_task_data_requests_reg$write_1__VAL_1 :
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	       m_pcie_wr_reqGen_outgoingBuffer$D_OUT[209:75] ;
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  assign m_pcie_wr_task_data_requests_reg$EN =
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	     WILL_FIRE_RL_m_pcie_wr_placeRequest ||
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	     WILL_FIRE_RL_m_pcie_wr_fillBuffer ;
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  // register m_pcie_wr_totalPuts
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  assign m_pcie_wr_totalPuts$D_IN = 32'h0 ;
  assign m_pcie_wr_totalPuts$EN = 1'b0 ;
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  // register opInProgress
  assign opInProgress$D_IN = !WILL_FIRE_RL_setInterrupt ;
  assign opInProgress$EN =
	     WILL_FIRE_RL_setInterrupt || WILL_FIRE_RL_handleRead ||
	     WILL_FIRE_RL_handleWrite ;

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  // register pc_betweenStart
  assign pc_betweenStart$D_IN = clkCntr ;
  assign pc_betweenStart$EN =
	     MUX_opInProgress$write_1__SEL_2 && pc_reqCntr == 12'd0 ;

  // register pc_reqCntr
  assign pc_reqCntr$D_IN =
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	     pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681 ?
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	       12'd0 :
	       pc_reqCntr + 12'd1 ;
  assign pc_reqCntr$EN = WILL_FIRE_RL_setInterrupt ;

  // register pc_start
  assign pc_start$D_IN = clkCntr ;
  assign pc_start$EN = MUX_opInProgress$write_1__SEL_2 ;

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  // register pcieLastCycle
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  assign pcieLastCycle$D_IN =
	     m_pcie_rd_task_data_output_reg[64:6] != 59'd0 ||
	     m_pcie_rd_task_data_requests_reg[126:68] != 59'd0 ||
	     m_pcie_wr_task_data_output_reg[64:6] != 59'd0 ||
	     m_pcie_wr_task_data_requests_reg[126:68] != 59'd0 ;
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  assign pcieLastCycle$EN = pcieDone$sFULL_N ;

  // register readConverter_buffer
  assign readConverter_buffer$D_IN = fpga_response_converter$dD_OUT ;
  assign readConverter_buffer$EN = WILL_FIRE_RL_mkConnectionGetPut_1 ;

  // register readConverter_bufferEmpty
  assign readConverter_bufferEmpty$D_IN =
	     readConverter_bufferEmpty$port2__read ;
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