mkBlueDMA.v 264 KB
Newer Older
Jens Korinth's avatar
Jens Korinth committed
4001
4002
4003
4004
4005
  assign readConverter_bufferEmpty$EN = 1'b1 ;

  // register readConverter_byteCntr
  assign readConverter_byteCntr$D_IN =
	     readConvBTT_ff$dEMPTY_N ?
Jaco Hofmann's avatar
Jaco Hofmann committed
4006
	       readConvBTT_ff$dD_OUT[64:1] :
Jens Korinth's avatar
Jens Korinth committed
4007
4008
4009
4010
4011
4012
	       MUX_readConverter_byteCntr$write_1__VAL_2 ;
  assign readConverter_byteCntr$EN =
	     readConvBTT_ff$dEMPTY_N || WILL_FIRE_RL_mkConnectionGetPut_2 ;

  // register readConverter_wordInCntr
  assign readConverter_wordInCntr$D_IN =
Jaco Hofmann's avatar
Jaco Hofmann committed
4013
4014
4015
	     readConvBTT_ff$dEMPTY_N ?
	       readConvBTT_ff$dD_OUT[0] :
	       IF_0_CONCAT_readConverter_wordInCntr_EQ_1_OR_r_ETC__q1[0] ;
Jens Korinth's avatar
Jens Korinth committed
4016
  assign readConverter_wordInCntr$EN =
Jaco Hofmann's avatar
Jaco Hofmann committed
4017
4018
4019
4020
4021
	     readConvBTT_ff$dEMPTY_N || WILL_FIRE_RL_mkConnectionGetPut_2 ;

  // register readIn_rv
  assign readIn_rv$D_IN = readIn_rv$port2__read ;
  assign readIn_rv$EN = 1'b1 ;
Jens Korinth's avatar
Jens Korinth committed
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066

  // register read_requests
  assign read_requests$D_IN = read_requests + 64'd1 ;
  assign read_requests$EN = WILL_FIRE_RL_handleRead ;

  // register s_config_readBusy
  assign s_config_readBusy$D_IN = 1'b0 ;
  assign s_config_readBusy$EN = 1'b0 ;

  // register s_config_writeSlave_addrIn_rv
  assign s_config_writeSlave_addrIn_rv$D_IN =
	     s_config_writeSlave_addrIn_rv$port2__read ;
  assign s_config_writeSlave_addrIn_rv$EN = 1'b1 ;

  // register s_config_writeSlave_dataIn_rv
  assign s_config_writeSlave_dataIn_rv$D_IN =
	     s_config_writeSlave_dataIn_rv$port2__read ;
  assign s_config_writeSlave_dataIn_rv$EN = 1'b1 ;

  // register transfer_length
  assign transfer_length$D_IN =
	     { s_config_writeSlave_in$D_OUT[10] ?
		 s_config_writeSlave_in$D_OUT[74:67] :
		 transfer_length[63:56],
	       s_config_writeSlave_in$D_OUT[9] ?
		 s_config_writeSlave_in$D_OUT[66:59] :
		 transfer_length[55:48],
	       s_config_writeSlave_in$D_OUT[8] ?
		 s_config_writeSlave_in$D_OUT[58:51] :
		 transfer_length[47:40],
	       s_config_writeSlave_in$D_OUT[7] ?
		 s_config_writeSlave_in$D_OUT[50:43] :
		 transfer_length[39:32],
	       s_config_writeSlave_in$D_OUT[6] ?
		 s_config_writeSlave_in$D_OUT[42:35] :
		 transfer_length[31:24],
	       s_config_writeSlave_in$D_OUT[5] ?
		 s_config_writeSlave_in$D_OUT[34:27] :
		 transfer_length[23:16],
	       s_config_writeSlave_in$D_OUT[4] ?
		 s_config_writeSlave_in$D_OUT[26:19] :
		 transfer_length[15:8],
	       s_config_writeSlave_in$D_OUT[3] ?
		 s_config_writeSlave_in$D_OUT[18:11] :
		 transfer_length[7:0] } ;
4067
  assign transfer_length$EN = WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 ;
Jens Korinth's avatar
Jens Korinth committed
4068
4069

  // register writeConverter_buffer_0
Jaco Hofmann's avatar
Jaco Hofmann committed
4070
  assign writeConverter_buffer_0$D_IN = m_pcie_rd_outgoingBuffer$D_OUT ;
Jens Korinth's avatar
Jens Korinth committed
4071
4072
4073
4074
4075
4076
4077
  assign writeConverter_buffer_0$EN =
	     WILL_FIRE_RL_mkConnectionGetPut_3 &&
	     writeConverter_wordInCntr == 2'd0 ;

  // register writeConverter_byteCntr
  assign writeConverter_byteCntr$D_IN =
	     writeConvBTT_ff$dEMPTY_N ?
Jaco Hofmann's avatar
Jaco Hofmann committed
4078
	       writeConvBTT_ff$dD_OUT[64:1] :
Jens Korinth's avatar
Jens Korinth committed
4079
4080
4081
4082
4083
4084
	       MUX_writeConverter_byteCntr$write_1__VAL_2 ;
  assign writeConverter_byteCntr$EN =
	     writeConvBTT_ff$dEMPTY_N || WILL_FIRE_RL_mkConnectionGetPut_3 ;

  // register writeConverter_wordInCntr
  assign writeConverter_wordInCntr$D_IN =
Jaco Hofmann's avatar
Jaco Hofmann committed
4085
	     writeConvBTT_ff$dEMPTY_N ?
Jens Korinth's avatar
Jens Korinth committed
4086
	       MUX_writeConverter_wordInCntr$write_1__VAL_1 :
Jaco Hofmann's avatar
Jaco Hofmann committed
4087
	       MUX_writeConverter_wordInCntr$write_1__VAL_2 ;
Jens Korinth's avatar
Jens Korinth committed
4088
  assign writeConverter_wordInCntr$EN =
Jaco Hofmann's avatar
Jaco Hofmann committed
4089
4090
4091
4092
4093
	     writeConvBTT_ff$dEMPTY_N || WILL_FIRE_RL_mkConnectionGetPut_3 ;

  // register writeIn_rv
  assign writeIn_rv$D_IN = writeIn_rv$port2__read ;
  assign writeIn_rv$EN = 1'b1 ;
Jens Korinth's avatar
Jens Korinth committed
4094
4095
4096
4097
4098

  // register write_requests
  assign write_requests$D_IN = write_requests + 64'd1 ;
  assign write_requests$EN = WILL_FIRE_RL_handleWrite ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4099
4100
4101
4102
4103
  // submodule byteAlignerReader_addr_ff
  assign byteAlignerReader_addr_ff$sD_IN = 192'h0 ;
  assign byteAlignerReader_addr_ff$sENQ = 1'b0 ;
  assign byteAlignerReader_addr_ff$dDEQ = byteAlignerReader_addr_ff$dEMPTY_N ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
  // submodule byteAlignerReader_incoming
  assign byteAlignerReader_incoming$D_IN = 256'h0 ;
  assign byteAlignerReader_incoming$ENQ = 1'b0 ;
  assign byteAlignerReader_incoming$DEQ =
	     WILL_FIRE_RL_byteAlignerReader_fetchNewData ;
  assign byteAlignerReader_incoming$CLR = 1'b0 ;

  // submodule byteAlignerReader_outgoing
  assign byteAlignerReader_outgoing$D_IN = byteAlignerReader_buffer[255:0] ;
  assign byteAlignerReader_outgoing$ENQ =
	     WILL_FIRE_RL_byteAlignerReader_forwardOutputLast ||
	     WILL_FIRE_RL_byteAlignerReader_forwardOutput ;
  assign byteAlignerReader_outgoing$DEQ = 1'b0 ;
  assign byteAlignerReader_outgoing$CLR = 1'b0 ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4119
4120
4121
4122
4123
  // submodule byteAlignerWriter_addr_ff
  assign byteAlignerWriter_addr_ff$sD_IN = 192'h0 ;
  assign byteAlignerWriter_addr_ff$sENQ = 1'b0 ;
  assign byteAlignerWriter_addr_ff$dDEQ = byteAlignerWriter_addr_ff$dEMPTY_N ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
  // submodule byteAlignerWriter_incoming
  assign byteAlignerWriter_incoming$D_IN = 256'h0 ;
  assign byteAlignerWriter_incoming$ENQ = 1'b0 ;
  assign byteAlignerWriter_incoming$DEQ =
	     WILL_FIRE_RL_byteAlignerWriter_fetchNewData ;
  assign byteAlignerWriter_incoming$CLR = 1'b0 ;

  // submodule byteAlignerWriter_outgoing
  assign byteAlignerWriter_outgoing$D_IN = byteAlignerWriter_buffer[255:0] ;
  assign byteAlignerWriter_outgoing$ENQ =
	     WILL_FIRE_RL_byteAlignerWriter_forwardOutputLast ||
	     WILL_FIRE_RL_byteAlignerWriter_forwardOutput ;
  assign byteAlignerWriter_outgoing$DEQ = 1'b0 ;
  assign byteAlignerWriter_outgoing$CLR = 1'b0 ;

Jens Korinth's avatar
Jens Korinth committed
4139
4140
4141
4142
4143
4144
4145
4146
  // submodule cmdsIn
  assign cmdsIn$D_IN =
	     s_config_writeSlave_in$D_OUT[74:11] != 64'h0000000010001000 ;
  assign cmdsIn$ENQ =
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial &&
	     (s_config_writeSlave_in$D_OUT[74:11] == 64'h0000000010001000 ||
	      s_config_writeSlave_in$D_OUT[74:11] == 64'h0000000010000001) ;
  assign cmdsIn$DEQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4147
4148
	     cmdsIn$EMPTY_N && !writeIn_rv$port1__read[192] && cmdsIn$D_OUT ||
	     cmdsIn$EMPTY_N && !readIn_rv$port1__read[192] && !cmdsIn$D_OUT ;
Jens Korinth's avatar
Jens Korinth committed
4149
4150
4151
4152
4153
  assign cmdsIn$CLR = 1'b0 ;

  // submodule fpgaDone
  assign fpgaDone$sD_IN = 1'd1 ;
  assign fpgaDone$sENQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4154
	     fpgaDone$sFULL_N &&
4155
	     fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672 ;
Jens Korinth's avatar
Jens Korinth committed
4156
4157
4158
  assign fpgaDone$dDEQ = WILL_FIRE_RL_setInterrupt ;

  // submodule fpga_request_converter
Jaco Hofmann's avatar
Jaco Hofmann committed
4159
  assign fpga_request_converter$sD_IN = writeConverter_dataSync$D_OUT ;
Jens Korinth's avatar
Jens Korinth committed
4160
  assign fpga_request_converter$sENQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4161
4162
	     fpga_request_converter$sFULL_N &&
	     writeConverter_dataSync$EMPTY_N ;
Jens Korinth's avatar
Jens Korinth committed
4163
4164
  assign fpga_request_converter$dDEQ =
	     fpga_request_converter$dEMPTY_N &&
Jaco Hofmann's avatar
Jaco Hofmann committed
4165
	     m_fpga_wr_incomingBuffer$FULL_N ;
Jens Korinth's avatar
Jens Korinth committed
4166
4167

  // submodule fpga_response_converter
Jaco Hofmann's avatar
Jaco Hofmann committed
4168
  assign fpga_response_converter$sD_IN = m_fpga_rd_outgoingBuffer$D_OUT ;
Jens Korinth's avatar
Jens Korinth committed
4169
  assign fpga_response_converter$sENQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4170
4171
	     fpga_response_converter$sFULL_N &&
	     m_fpga_rd_outgoingBuffer$EMPTY_N ;
Jens Korinth's avatar
Jens Korinth committed
4172
4173
4174
4175
  assign fpga_response_converter$dDEQ = WILL_FIRE_RL_mkConnectionGetPut_1 ;

  // submodule m_fpga_rd_master_rd_in
  assign m_fpga_rd_master_rd_in$D_IN =
4176
4177
	     { 1'd0,
	       m_fpga_rd_task_data_requests_reg[67:4],
Jaco Hofmann's avatar
Jaco Hofmann committed
4178
4179
	       (m_fpga_rd_task_data_requests_reg[125:68] == 58'd1 &&
		m_fpga_rd_task_data_requests_reg[133:126] != 8'd0) ?
4180
		 beatsThisRequest___1__h57938 :
Jens Korinth's avatar
Jens Korinth committed
4181
4182
		 8'd255,
	       17'd102784,
Jaco Hofmann's avatar
Jaco Hofmann committed
4183
	       m_fpga_rd_task_data_requests_reg[3:0],
Jens Korinth's avatar
Jens Korinth committed
4184
4185
4186
4187
4188
4189
4190
	       1'd0 } ;
  assign m_fpga_rd_master_rd_in$ENQ = WILL_FIRE_RL_m_fpga_rd_placeRequest ;
  assign m_fpga_rd_master_rd_in$DEQ =
	     m_fpga_rd_master_rd_in$EMPTY_N && fpga_rd_arready ;
  assign m_fpga_rd_master_rd_in$CLR = 1'b0 ;

  // submodule m_fpga_rd_master_rd_out
Jaco Hofmann's avatar
Jaco Hofmann committed
4191
4192
4193
4194
  assign m_fpga_rd_master_rd_out$D_IN = m_fpga_rd_master_rd_rinpkg$wget ;
  assign m_fpga_rd_master_rd_out$ENQ =
	     m_fpga_rd_master_rd_out$FULL_N && fpga_rd_rvalid ;
  assign m_fpga_rd_master_rd_out$DEQ = WILL_FIRE_RL_m_fpga_rd_forwardData ;
Jens Korinth's avatar
Jens Korinth committed
4195
4196
  assign m_fpga_rd_master_rd_out$CLR = 1'b0 ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4197
4198
4199
4200
4201
4202
4203
4204
4205
  // submodule m_fpga_rd_outgoingBuffer
  assign m_fpga_rd_outgoingBuffer$D_IN =
	     m_fpga_rd_master_rd_out$D_OUT[515:4] ;
  assign m_fpga_rd_outgoingBuffer$ENQ = WILL_FIRE_RL_m_fpga_rd_forwardData ;
  assign m_fpga_rd_outgoingBuffer$DEQ =
	     fpga_response_converter$sFULL_N &&
	     m_fpga_rd_outgoingBuffer$EMPTY_N ;
  assign m_fpga_rd_outgoingBuffer$CLR = 1'b0 ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
  // submodule m_fpga_rd_reqGen_incomingBuffer
  assign m_fpga_rd_reqGen_incomingBuffer$D_IN =
	     mclk_m_fpga_put_req_rd_ff$dD_OUT ;
  assign m_fpga_rd_reqGen_incomingBuffer$ENQ =
	     mclk_m_fpga_put_req_rd_ff$dEMPTY_N &&
	     m_fpga_rd_reqGen_incomingBuffer$FULL_N ;
  assign m_fpga_rd_reqGen_incomingBuffer$DEQ =
	     m_fpga_rd_reqGen_incomingBuffer$EMPTY_N &&
	     m_fpga_rd_reqGen_intermediateBuffer$FULL_N ;
  assign m_fpga_rd_reqGen_incomingBuffer$CLR = 1'b0 ;

  // submodule m_fpga_rd_reqGen_intermediateBuffer
  assign m_fpga_rd_reqGen_intermediateBuffer$D_IN =
4219
	     { x__h55526[5:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4220
	       m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6[5:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
	       m_fpga_rd_reqGen_incomingBuffer$D_OUT } ;
  assign m_fpga_rd_reqGen_intermediateBuffer$ENQ =
	     m_fpga_rd_reqGen_incomingBuffer$EMPTY_N &&
	     m_fpga_rd_reqGen_intermediateBuffer$FULL_N ;
  assign m_fpga_rd_reqGen_intermediateBuffer$DEQ =
	     m_fpga_rd_reqGen_intermediateBuffer$EMPTY_N &&
	     m_fpga_rd_reqGen_intermediateBuffer2$FULL_N ;
  assign m_fpga_rd_reqGen_intermediateBuffer$CLR = 1'b0 ;

  // submodule m_fpga_rd_reqGen_intermediateBuffer2
  assign m_fpga_rd_reqGen_intermediateBuffer2$D_IN =
	     { m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:132],
4233
	       x__h55707[57:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
	       m_fpga_rd_reqGen_intermediateBuffer$D_OUT[131:0] } ;
  assign m_fpga_rd_reqGen_intermediateBuffer2$ENQ =
	     m_fpga_rd_reqGen_intermediateBuffer$EMPTY_N &&
	     m_fpga_rd_reqGen_intermediateBuffer2$FULL_N ;
  assign m_fpga_rd_reqGen_intermediateBuffer2$DEQ =
	     WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest ;
  assign m_fpga_rd_reqGen_intermediateBuffer2$CLR = 1'b0 ;

  // submodule m_fpga_rd_reqGen_outgoingBuffer
  assign m_fpga_rd_reqGen_outgoingBuffer$D_IN =
	     { m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[139:132],
4245
4246
	       request_data_requests_total__h55844,
	       request_data_address__h55845,
Jaco Hofmann's avatar
Jaco Hofmann committed
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
	       m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[3:0],
	       m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[201:132],
	       m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[73:68],
	       1'd1 } ;
  assign m_fpga_rd_reqGen_outgoingBuffer$ENQ =
	     WILL_FIRE_RL_m_fpga_rd_reqGen_finishRequest ;
  assign m_fpga_rd_reqGen_outgoingBuffer$DEQ =
	     WILL_FIRE_RL_m_fpga_rd_fillBuffer ;
  assign m_fpga_rd_reqGen_outgoingBuffer$CLR = 1'b0 ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4257
  // submodule m_fpga_wr_beatsPerRequestFIFO
4258
  assign m_fpga_wr_beatsPerRequestFIFO$D_IN = _theResult____h43299 ;
Jaco Hofmann's avatar
Jaco Hofmann committed
4259
4260
4261
4262
  assign m_fpga_wr_beatsPerRequestFIFO$ENQ =
	     WILL_FIRE_RL_m_fpga_wr_placeRequest ;
  assign m_fpga_wr_beatsPerRequestFIFO$DEQ =
	     WILL_FIRE_RL_m_fpga_wr_forwardData &&
4263
	     m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929 ;
Jaco Hofmann's avatar
Jaco Hofmann committed
4264
  assign m_fpga_wr_beatsPerRequestFIFO$CLR = 1'b0 ;
Jens Korinth's avatar
Jens Korinth committed
4265

Jaco Hofmann's avatar
Jaco Hofmann committed
4266
4267
4268
4269
4270
4271
4272
4273
  // submodule m_fpga_wr_incomingBuffer
  assign m_fpga_wr_incomingBuffer$D_IN = fpga_request_converter$dD_OUT ;
  assign m_fpga_wr_incomingBuffer$ENQ =
	     fpga_request_converter$dEMPTY_N &&
	     m_fpga_wr_incomingBuffer$FULL_N ;
  assign m_fpga_wr_incomingBuffer$DEQ = WILL_FIRE_RL_m_fpga_wr_forwardData ;
  assign m_fpga_wr_incomingBuffer$CLR = 1'b0 ;

Jens Korinth's avatar
Jens Korinth committed
4274
4275
  // submodule m_fpga_wr_master_wr_in_addr
  assign m_fpga_wr_master_wr_in_addr$D_IN =
4276
4277
4278
	     { 1'd0,
	       m_fpga_wr_task_data_requests_reg[67:4],
	       _theResult____h43299,
Jens Korinth's avatar
Jens Korinth committed
4279
	       17'd102784,
Jaco Hofmann's avatar
Jaco Hofmann committed
4280
	       m_fpga_wr_task_data_requests_reg[3:0],
Jens Korinth's avatar
Jens Korinth committed
4281
4282
4283
4284
4285
4286
4287
4288
	       1'd0 } ;
  assign m_fpga_wr_master_wr_in_addr$ENQ =
	     WILL_FIRE_RL_m_fpga_wr_placeRequest ;
  assign m_fpga_wr_master_wr_in_addr$DEQ =
	     m_fpga_wr_master_wr_in_addr$EMPTY_N && fpga_wr_awready ;
  assign m_fpga_wr_master_wr_in_addr$CLR = 1'b0 ;

  // submodule m_fpga_wr_master_wr_in_data
Jaco Hofmann's avatar
Jaco Hofmann committed
4289
4290
  assign m_fpga_wr_master_wr_in_data$D_IN =
	     { m_fpga_wr_incomingBuffer$D_OUT,
4291
4292
	       x_strb__h43921,
	       m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929,
Jaco Hofmann's avatar
Jaco Hofmann committed
4293
4294
4295
4296
4297
	       1'd0 } ;
  assign m_fpga_wr_master_wr_in_data$ENQ =
	     WILL_FIRE_RL_m_fpga_wr_forwardData ;
  assign m_fpga_wr_master_wr_in_data$DEQ =
	     m_fpga_wr_master_wr_in_data$EMPTY_N && fpga_wr_wready ;
Jens Korinth's avatar
Jens Korinth committed
4298
4299
4300
4301
4302
4303
4304
4305
4306
  assign m_fpga_wr_master_wr_in_data$CLR = 1'b0 ;

  // submodule m_fpga_wr_master_wr_out
  assign m_fpga_wr_master_wr_out$D_IN = m_fpga_wr_master_wr_rinpkg$wget ;
  assign m_fpga_wr_master_wr_out$ENQ =
	     m_fpga_wr_master_wr_out$FULL_N && fpga_wr_bvalid ;
  assign m_fpga_wr_master_wr_out$DEQ = m_fpga_wr_master_wr_out$EMPTY_N ;
  assign m_fpga_wr_master_wr_out$CLR = 1'b0 ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
  // submodule m_fpga_wr_reqGen_incomingBuffer
  assign m_fpga_wr_reqGen_incomingBuffer$D_IN =
	     mclk_m_fpga_put_req_wr_ff$dD_OUT ;
  assign m_fpga_wr_reqGen_incomingBuffer$ENQ =
	     mclk_m_fpga_put_req_wr_ff$dEMPTY_N &&
	     m_fpga_wr_reqGen_incomingBuffer$FULL_N ;
  assign m_fpga_wr_reqGen_incomingBuffer$DEQ =
	     m_fpga_wr_reqGen_incomingBuffer$EMPTY_N &&
	     m_fpga_wr_reqGen_intermediateBuffer$FULL_N ;
  assign m_fpga_wr_reqGen_incomingBuffer$CLR = 1'b0 ;

  // submodule m_fpga_wr_reqGen_intermediateBuffer
  assign m_fpga_wr_reqGen_intermediateBuffer$D_IN =
4320
	     { x__h40179[5:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4321
	       m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7[5:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
	       m_fpga_wr_reqGen_incomingBuffer$D_OUT } ;
  assign m_fpga_wr_reqGen_intermediateBuffer$ENQ =
	     m_fpga_wr_reqGen_incomingBuffer$EMPTY_N &&
	     m_fpga_wr_reqGen_intermediateBuffer$FULL_N ;
  assign m_fpga_wr_reqGen_intermediateBuffer$DEQ =
	     m_fpga_wr_reqGen_intermediateBuffer$EMPTY_N &&
	     m_fpga_wr_reqGen_intermediateBuffer2$FULL_N ;
  assign m_fpga_wr_reqGen_intermediateBuffer$CLR = 1'b0 ;

  // submodule m_fpga_wr_reqGen_intermediateBuffer2
  assign m_fpga_wr_reqGen_intermediateBuffer2$D_IN =
	     { m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:132],
4334
	       x__h40360[57:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
	       m_fpga_wr_reqGen_intermediateBuffer$D_OUT[131:0] } ;
  assign m_fpga_wr_reqGen_intermediateBuffer2$ENQ =
	     m_fpga_wr_reqGen_intermediateBuffer$EMPTY_N &&
	     m_fpga_wr_reqGen_intermediateBuffer2$FULL_N ;
  assign m_fpga_wr_reqGen_intermediateBuffer2$DEQ =
	     WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest ;
  assign m_fpga_wr_reqGen_intermediateBuffer2$CLR = 1'b0 ;

  // submodule m_fpga_wr_reqGen_outgoingBuffer
  assign m_fpga_wr_reqGen_outgoingBuffer$D_IN =
	     { m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[139:132],
4346
4347
	       request_data_requests_total__h40497,
	       request_data_address__h40498,
Jaco Hofmann's avatar
Jaco Hofmann committed
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
	       m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[3:0],
	       m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[201:132],
	       m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[73:68],
	       1'd1 } ;
  assign m_fpga_wr_reqGen_outgoingBuffer$ENQ =
	     WILL_FIRE_RL_m_fpga_wr_reqGen_finishRequest ;
  assign m_fpga_wr_reqGen_outgoingBuffer$DEQ =
	     WILL_FIRE_RL_m_fpga_wr_fillBuffer ;
  assign m_fpga_wr_reqGen_outgoingBuffer$CLR = 1'b0 ;

Jens Korinth's avatar
Jens Korinth committed
4358
4359
  // submodule m_pcie_rd_master_rd_in
  assign m_pcie_rd_master_rd_in$D_IN =
4360
4361
	     { 1'd0,
	       m_pcie_rd_task_data_requests_reg[67:4],
Jaco Hofmann's avatar
Jaco Hofmann committed
4362
4363
	       (m_pcie_rd_task_data_requests_reg[126:68] == 59'd1 &&
		m_pcie_rd_task_data_requests_reg[134:127] != 8'd0) ?
4364
		 beatsThisRequest___1__h38705 :
Jaco Hofmann's avatar
Jaco Hofmann committed
4365
		 8'd63,
Jens Korinth's avatar
Jens Korinth committed
4366
	       17'd86400,
Jaco Hofmann's avatar
Jaco Hofmann committed
4367
	       m_pcie_rd_task_data_requests_reg[3:0],
Jens Korinth's avatar
Jens Korinth committed
4368
4369
4370
4371
4372
4373
4374
	       1'd0 } ;
  assign m_pcie_rd_master_rd_in$ENQ = WILL_FIRE_RL_m_pcie_rd_placeRequest ;
  assign m_pcie_rd_master_rd_in$DEQ =
	     m_pcie_rd_master_rd_in$EMPTY_N && pcie_rd_arready ;
  assign m_pcie_rd_master_rd_in$CLR = 1'b0 ;

  // submodule m_pcie_rd_master_rd_out
Jaco Hofmann's avatar
Jaco Hofmann committed
4375
4376
4377
4378
  assign m_pcie_rd_master_rd_out$D_IN = m_pcie_rd_master_rd_rinpkg$wget ;
  assign m_pcie_rd_master_rd_out$ENQ =
	     m_pcie_rd_master_rd_out$FULL_N && pcie_rd_rvalid ;
  assign m_pcie_rd_master_rd_out$DEQ = WILL_FIRE_RL_m_pcie_rd_forwardData ;
Jens Korinth's avatar
Jens Korinth committed
4379
4380
  assign m_pcie_rd_master_rd_out$CLR = 1'b0 ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4381
4382
4383
4384
4385
4386
4387
  // submodule m_pcie_rd_outgoingBuffer
  assign m_pcie_rd_outgoingBuffer$D_IN =
	     m_pcie_rd_master_rd_out$D_OUT[259:4] ;
  assign m_pcie_rd_outgoingBuffer$ENQ = WILL_FIRE_RL_m_pcie_rd_forwardData ;
  assign m_pcie_rd_outgoingBuffer$DEQ = WILL_FIRE_RL_mkConnectionGetPut_3 ;
  assign m_pcie_rd_outgoingBuffer$CLR = 1'b0 ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
  // submodule m_pcie_rd_reqGen_incomingBuffer
  assign m_pcie_rd_reqGen_incomingBuffer$D_IN =
	     mclk_m_pcie_put_req_rd_ff$dD_OUT ;
  assign m_pcie_rd_reqGen_incomingBuffer$ENQ =
	     mclk_m_pcie_put_req_rd_ff$dEMPTY_N &&
	     m_pcie_rd_reqGen_incomingBuffer$FULL_N ;
  assign m_pcie_rd_reqGen_incomingBuffer$DEQ =
	     m_pcie_rd_reqGen_incomingBuffer$EMPTY_N &&
	     m_pcie_rd_reqGen_intermediateBuffer$FULL_N ;
  assign m_pcie_rd_reqGen_incomingBuffer$CLR = 1'b0 ;

  // submodule m_pcie_rd_reqGen_intermediateBuffer
  assign m_pcie_rd_reqGen_intermediateBuffer$D_IN =
4401
	     { x__h36290[4:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4402
	       m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8[4:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
	       m_pcie_rd_reqGen_incomingBuffer$D_OUT } ;
  assign m_pcie_rd_reqGen_intermediateBuffer$ENQ =
	     m_pcie_rd_reqGen_incomingBuffer$EMPTY_N &&
	     m_pcie_rd_reqGen_intermediateBuffer$FULL_N ;
  assign m_pcie_rd_reqGen_intermediateBuffer$DEQ =
	     m_pcie_rd_reqGen_intermediateBuffer$EMPTY_N &&
	     m_pcie_rd_reqGen_intermediateBuffer2$FULL_N ;
  assign m_pcie_rd_reqGen_intermediateBuffer$CLR = 1'b0 ;

  // submodule m_pcie_rd_reqGen_intermediateBuffer2
  assign m_pcie_rd_reqGen_intermediateBuffer2$D_IN =
	     { m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:132],
4415
	       x__h36471[58:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
	       m_pcie_rd_reqGen_intermediateBuffer$D_OUT[131:0] } ;
  assign m_pcie_rd_reqGen_intermediateBuffer2$ENQ =
	     m_pcie_rd_reqGen_intermediateBuffer$EMPTY_N &&
	     m_pcie_rd_reqGen_intermediateBuffer2$FULL_N ;
  assign m_pcie_rd_reqGen_intermediateBuffer2$DEQ =
	     WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest ;
  assign m_pcie_rd_reqGen_intermediateBuffer2$CLR = 1'b0 ;

  // submodule m_pcie_rd_reqGen_outgoingBuffer
  assign m_pcie_rd_reqGen_outgoingBuffer$D_IN =
4426
4427
4428
	     { requests_last__h36571,
	       request_data_requests_total__h36608,
	       request_data_address__h36609,
Jaco Hofmann's avatar
Jaco Hofmann committed
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
	       m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[3:0],
	       m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[200:132],
	       m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[72:68],
	       1'd1 } ;
  assign m_pcie_rd_reqGen_outgoingBuffer$ENQ =
	     WILL_FIRE_RL_m_pcie_rd_reqGen_finishRequest ;
  assign m_pcie_rd_reqGen_outgoingBuffer$DEQ =
	     WILL_FIRE_RL_m_pcie_rd_fillBuffer ;
  assign m_pcie_rd_reqGen_outgoingBuffer$CLR = 1'b0 ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4439
  // submodule m_pcie_wr_beatsPerRequestFIFO
4440
  assign m_pcie_wr_beatsPerRequestFIFO$D_IN = _theResult____h29471 ;
Jaco Hofmann's avatar
Jaco Hofmann committed
4441
4442
4443
4444
  assign m_pcie_wr_beatsPerRequestFIFO$ENQ =
	     WILL_FIRE_RL_m_pcie_wr_placeRequest ;
  assign m_pcie_wr_beatsPerRequestFIFO$DEQ =
	     WILL_FIRE_RL_m_pcie_wr_forwardData &&
4445
	     m_pcie_wr_beatsThisRequestCntr_42_EQ_m_pcie_wr_ETC___d444 ;
Jaco Hofmann's avatar
Jaco Hofmann committed
4446
  assign m_pcie_wr_beatsPerRequestFIFO$CLR = 1'b0 ;
Jens Korinth's avatar
Jens Korinth committed
4447

Jaco Hofmann's avatar
Jaco Hofmann committed
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
  // submodule m_pcie_wr_incomingBuffer
  always@(readConverter_wordInCntr or readConverter_buffer)
  begin
    case (readConverter_wordInCntr)
      1'd0: m_pcie_wr_incomingBuffer$D_IN = readConverter_buffer[255:0];
      1'd1: m_pcie_wr_incomingBuffer$D_IN = readConverter_buffer[511:256];
    endcase
  end
  assign m_pcie_wr_incomingBuffer$ENQ = WILL_FIRE_RL_mkConnectionGetPut_2 ;
  assign m_pcie_wr_incomingBuffer$DEQ = WILL_FIRE_RL_m_pcie_wr_forwardData ;
  assign m_pcie_wr_incomingBuffer$CLR = 1'b0 ;

Jens Korinth's avatar
Jens Korinth committed
4460
4461
  // submodule m_pcie_wr_master_wr_in_addr
  assign m_pcie_wr_master_wr_in_addr$D_IN =
4462
4463
4464
	     { 1'd0,
	       m_pcie_wr_task_data_requests_reg[67:4],
	       _theResult____h29471,
Jens Korinth's avatar
Jens Korinth committed
4465
	       17'd86400,
Jaco Hofmann's avatar
Jaco Hofmann committed
4466
	       m_pcie_wr_task_data_requests_reg[3:0],
Jens Korinth's avatar
Jens Korinth committed
4467
4468
4469
4470
4471
4472
4473
4474
	       1'd0 } ;
  assign m_pcie_wr_master_wr_in_addr$ENQ =
	     WILL_FIRE_RL_m_pcie_wr_placeRequest ;
  assign m_pcie_wr_master_wr_in_addr$DEQ =
	     m_pcie_wr_master_wr_in_addr$EMPTY_N && pcie_wr_awready ;
  assign m_pcie_wr_master_wr_in_addr$CLR = 1'b0 ;

  // submodule m_pcie_wr_master_wr_in_data
Jaco Hofmann's avatar
Jaco Hofmann committed
4475
4476
  assign m_pcie_wr_master_wr_in_data$D_IN =
	     { m_pcie_wr_incomingBuffer$D_OUT,
4477
4478
	       x_strb__h30093,
	       m_pcie_wr_beatsThisRequestCntr_42_EQ_m_pcie_wr_ETC___d444,
Jaco Hofmann's avatar
Jaco Hofmann committed
4479
4480
4481
4482
4483
	       1'd0 } ;
  assign m_pcie_wr_master_wr_in_data$ENQ =
	     WILL_FIRE_RL_m_pcie_wr_forwardData ;
  assign m_pcie_wr_master_wr_in_data$DEQ =
	     m_pcie_wr_master_wr_in_data$EMPTY_N && pcie_wr_wready ;
Jens Korinth's avatar
Jens Korinth committed
4484
4485
4486
4487
4488
4489
4490
4491
4492
  assign m_pcie_wr_master_wr_in_data$CLR = 1'b0 ;

  // submodule m_pcie_wr_master_wr_out
  assign m_pcie_wr_master_wr_out$D_IN = m_pcie_wr_master_wr_rinpkg$wget ;
  assign m_pcie_wr_master_wr_out$ENQ =
	     m_pcie_wr_master_wr_out$FULL_N && pcie_wr_bvalid ;
  assign m_pcie_wr_master_wr_out$DEQ = m_pcie_wr_master_wr_out$EMPTY_N ;
  assign m_pcie_wr_master_wr_out$CLR = 1'b0 ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
  // submodule m_pcie_wr_reqGen_incomingBuffer
  assign m_pcie_wr_reqGen_incomingBuffer$D_IN =
	     mclk_m_pcie_put_req_wr_ff$dD_OUT ;
  assign m_pcie_wr_reqGen_incomingBuffer$ENQ =
	     mclk_m_pcie_put_req_wr_ff$dEMPTY_N &&
	     m_pcie_wr_reqGen_incomingBuffer$FULL_N ;
  assign m_pcie_wr_reqGen_incomingBuffer$DEQ =
	     m_pcie_wr_reqGen_incomingBuffer$EMPTY_N &&
	     m_pcie_wr_reqGen_intermediateBuffer$FULL_N ;
  assign m_pcie_wr_reqGen_incomingBuffer$CLR = 1'b0 ;

  // submodule m_pcie_wr_reqGen_intermediateBuffer
  assign m_pcie_wr_reqGen_intermediateBuffer$D_IN =
4506
	     { x__h26336[4:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4507
	       m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9[4:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
	       m_pcie_wr_reqGen_incomingBuffer$D_OUT } ;
  assign m_pcie_wr_reqGen_intermediateBuffer$ENQ =
	     m_pcie_wr_reqGen_incomingBuffer$EMPTY_N &&
	     m_pcie_wr_reqGen_intermediateBuffer$FULL_N ;
  assign m_pcie_wr_reqGen_intermediateBuffer$DEQ =
	     m_pcie_wr_reqGen_intermediateBuffer$EMPTY_N &&
	     m_pcie_wr_reqGen_intermediateBuffer2$FULL_N ;
  assign m_pcie_wr_reqGen_intermediateBuffer$CLR = 1'b0 ;

  // submodule m_pcie_wr_reqGen_intermediateBuffer2
  assign m_pcie_wr_reqGen_intermediateBuffer2$D_IN =
	     { m_pcie_wr_reqGen_intermediateBuffer$D_OUT[141:132],
4520
	       x__h26517[58:0],
Jaco Hofmann's avatar
Jaco Hofmann committed
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
	       m_pcie_wr_reqGen_intermediateBuffer$D_OUT[131:0] } ;
  assign m_pcie_wr_reqGen_intermediateBuffer2$ENQ =
	     m_pcie_wr_reqGen_intermediateBuffer$EMPTY_N &&
	     m_pcie_wr_reqGen_intermediateBuffer2$FULL_N ;
  assign m_pcie_wr_reqGen_intermediateBuffer2$DEQ =
	     WILL_FIRE_RL_m_pcie_wr_reqGen_finishRequest ;
  assign m_pcie_wr_reqGen_intermediateBuffer2$CLR = 1'b0 ;

  // submodule m_pcie_wr_reqGen_outgoingBuffer
  assign m_pcie_wr_reqGen_outgoingBuffer$D_IN =
4531
4532
4533
	     { requests_last__h26617,
	       request_data_requests_total__h26654,
	       request_data_address__h26655,
Jaco Hofmann's avatar
Jaco Hofmann committed
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
	       m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[3:0],
	       m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[200:132],
	       m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[72:68],
	       1'd1 } ;
  assign m_pcie_wr_reqGen_outgoingBuffer$ENQ =
	     WILL_FIRE_RL_m_pcie_wr_reqGen_finishRequest ;
  assign m_pcie_wr_reqGen_outgoingBuffer$DEQ =
	     WILL_FIRE_RL_m_pcie_wr_fillBuffer ;
  assign m_pcie_wr_reqGen_outgoingBuffer$CLR = 1'b0 ;

Jens Korinth's avatar
Jens Korinth committed
4544
  // submodule mclk_m_fpga_put_req_rd_ff
Jaco Hofmann's avatar
Jaco Hofmann committed
4545
  assign mclk_m_fpga_put_req_rd_ff$sD_IN = { readIn_rv[127:0], 4'd0 } ;
Jens Korinth's avatar
Jens Korinth committed
4546
4547
  assign mclk_m_fpga_put_req_rd_ff$sENQ = WILL_FIRE_RL_handleRead ;
  assign mclk_m_fpga_put_req_rd_ff$dDEQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4548
	     mclk_m_fpga_put_req_rd_ff$dEMPTY_N &&
Jaco Hofmann's avatar
Jaco Hofmann committed
4549
	     m_fpga_rd_reqGen_incomingBuffer$FULL_N ;
Jens Korinth's avatar
Jens Korinth committed
4550
4551

  // submodule mclk_m_fpga_put_req_wr_ff
Jaco Hofmann's avatar
Jaco Hofmann committed
4552
  assign mclk_m_fpga_put_req_wr_ff$sD_IN = { writeIn_rv[127:0], 4'd0 } ;
Jens Korinth's avatar
Jens Korinth committed
4553
4554
  assign mclk_m_fpga_put_req_wr_ff$sENQ = WILL_FIRE_RL_handleWrite ;
  assign mclk_m_fpga_put_req_wr_ff$dDEQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4555
	     mclk_m_fpga_put_req_wr_ff$dEMPTY_N &&
Jaco Hofmann's avatar
Jaco Hofmann committed
4556
	     m_fpga_wr_reqGen_incomingBuffer$FULL_N ;
Jens Korinth's avatar
Jens Korinth committed
4557
4558
4559

  // submodule mclk_m_pcie_put_req_rd_ff
  assign mclk_m_pcie_put_req_rd_ff$sD_IN =
Jaco Hofmann's avatar
Jaco Hofmann committed
4560
	     { writeIn_rv[191:128], writeIn_rv[63:0], 4'd0 } ;
Jens Korinth's avatar
Jens Korinth committed
4561
4562
  assign mclk_m_pcie_put_req_rd_ff$sENQ = WILL_FIRE_RL_handleWrite ;
  assign mclk_m_pcie_put_req_rd_ff$dDEQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4563
	     mclk_m_pcie_put_req_rd_ff$dEMPTY_N &&
Jaco Hofmann's avatar
Jaco Hofmann committed
4564
	     m_pcie_rd_reqGen_incomingBuffer$FULL_N ;
Jens Korinth's avatar
Jens Korinth committed
4565
4566
4567

  // submodule mclk_m_pcie_put_req_wr_ff
  assign mclk_m_pcie_put_req_wr_ff$sD_IN =
Jaco Hofmann's avatar
Jaco Hofmann committed
4568
	     { readIn_rv[191:128], readIn_rv[63:0], 4'd0 } ;
Jens Korinth's avatar
Jens Korinth committed
4569
4570
  assign mclk_m_pcie_put_req_wr_ff$sENQ = WILL_FIRE_RL_handleRead ;
  assign mclk_m_pcie_put_req_wr_ff$dDEQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4571
	     mclk_m_pcie_put_req_wr_ff$dEMPTY_N &&
Jaco Hofmann's avatar
Jaco Hofmann committed
4572
	     m_pcie_wr_reqGen_incomingBuffer$FULL_N ;
Jens Korinth's avatar
Jens Korinth committed
4573
4574
4575
4576

  // submodule pcieDone
  assign pcieDone$sD_IN = 1'd1 ;
  assign pcieDone$sENQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4577
	     pcieDone$sFULL_N &&
4578
	     pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665 ;
Jens Korinth's avatar
Jens Korinth committed
4579
4580
4581
  assign pcieDone$dDEQ = WILL_FIRE_RL_setInterrupt ;

  // submodule readConvBTT_ff
4582
  assign readConvBTT_ff$sD_IN = { btt__h102089, readIn_rv[69] } ;
Jens Korinth's avatar
Jens Korinth committed
4583
4584
4585
4586
4587
4588
4589
4590
  assign readConvBTT_ff$sENQ = WILL_FIRE_RL_handleRead ;
  assign readConvBTT_ff$dDEQ = readConvBTT_ff$dEMPTY_N ;

  // submodule s_config_readSlave_in
  assign s_config_readSlave_in$D_IN = { S_AXI_araddr, S_AXI_arprot } ;
  assign s_config_readSlave_in$ENQ =
	     s_config_readSlave_in$FULL_N && S_AXI_arvalid ;
  assign s_config_readSlave_in$DEQ =
Jaco Hofmann's avatar
Jaco Hofmann committed
4591
	     WILL_FIRE_RL_s_config_axiReadFallback ||
Jens Korinth's avatar
Jens Korinth committed
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
	     WILL_FIRE_RL_s_config_axiReadSpecial_8 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_7 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_6 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_5 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_4 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_3 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_2 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_1 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial ;
  assign s_config_readSlave_in$CLR = 1'b0 ;

  // submodule s_config_readSlave_out
  always@(WILL_FIRE_RL_s_config_axiReadSpecial or
	  MUX_s_config_readSlave_out$enq_1__VAL_1 or
	  WILL_FIRE_RL_s_config_axiReadSpecial_1 or
	  MUX_s_config_readSlave_out$enq_1__VAL_2 or
	  WILL_FIRE_RL_s_config_axiReadSpecial_2 or
	  MUX_s_config_readSlave_out$enq_1__VAL_3 or
	  WILL_FIRE_RL_s_config_axiReadSpecial_3 or
	  MUX_s_config_readSlave_out$enq_1__VAL_4 or
	  WILL_FIRE_RL_s_config_axiReadSpecial_4 or
	  MUX_s_config_readSlave_out$enq_1__VAL_5 or
	  WILL_FIRE_RL_s_config_axiReadSpecial_5 or
	  MUX_s_config_readSlave_out$enq_1__VAL_6 or
	  WILL_FIRE_RL_s_config_axiReadSpecial_6 or
	  MUX_s_config_readSlave_out$enq_1__VAL_7 or
	  WILL_FIRE_RL_s_config_axiReadSpecial_7 or
	  MUX_s_config_readSlave_out$enq_1__VAL_8 or
	  WILL_FIRE_RL_s_config_axiReadSpecial_8 or
	  MUX_s_config_readSlave_out$enq_1__VAL_9 or
	  WILL_FIRE_RL_s_config_axiReadFallback)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_s_config_axiReadSpecial:
	  s_config_readSlave_out$D_IN =
	      MUX_s_config_readSlave_out$enq_1__VAL_1;
      WILL_FIRE_RL_s_config_axiReadSpecial_1:
	  s_config_readSlave_out$D_IN =
	      MUX_s_config_readSlave_out$enq_1__VAL_2;
      WILL_FIRE_RL_s_config_axiReadSpecial_2:
	  s_config_readSlave_out$D_IN =
	      MUX_s_config_readSlave_out$enq_1__VAL_3;
      WILL_FIRE_RL_s_config_axiReadSpecial_3:
	  s_config_readSlave_out$D_IN =
	      MUX_s_config_readSlave_out$enq_1__VAL_4;
      WILL_FIRE_RL_s_config_axiReadSpecial_4:
	  s_config_readSlave_out$D_IN =
	      MUX_s_config_readSlave_out$enq_1__VAL_5;
      WILL_FIRE_RL_s_config_axiReadSpecial_5:
	  s_config_readSlave_out$D_IN =
	      MUX_s_config_readSlave_out$enq_1__VAL_6;
      WILL_FIRE_RL_s_config_axiReadSpecial_6:
	  s_config_readSlave_out$D_IN =
	      MUX_s_config_readSlave_out$enq_1__VAL_7;
      WILL_FIRE_RL_s_config_axiReadSpecial_7:
	  s_config_readSlave_out$D_IN =
	      MUX_s_config_readSlave_out$enq_1__VAL_8;
      WILL_FIRE_RL_s_config_axiReadSpecial_8:
	  s_config_readSlave_out$D_IN =
	      MUX_s_config_readSlave_out$enq_1__VAL_9;
      WILL_FIRE_RL_s_config_axiReadFallback:
	  s_config_readSlave_out$D_IN = 66'd0;
      default: s_config_readSlave_out$D_IN =
		   66'h2AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign s_config_readSlave_out$ENQ =
	     WILL_FIRE_RL_s_config_axiReadSpecial ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_1 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_2 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_3 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_4 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_5 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_6 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_7 ||
	     WILL_FIRE_RL_s_config_axiReadSpecial_8 ||
	     WILL_FIRE_RL_s_config_axiReadFallback ;
  assign s_config_readSlave_out$DEQ =
	     s_config_readSlave_out$EMPTY_N && S_AXI_rready ;
  assign s_config_readSlave_out$CLR = 1'b0 ;

  // submodule s_config_writeSlave_in
  assign s_config_writeSlave_in$D_IN =
	     { s_config_writeSlave_addrIn_rv$port1__read[66:3],
	       s_config_writeSlave_dataIn_rv$port1__read[71:0],
	       s_config_writeSlave_addrIn_rv$port1__read[2:0] } ;
  assign s_config_writeSlave_in$ENQ =
	     s_config_writeSlave_addrIn_rv$port1__read[67] &&
	     s_config_writeSlave_dataIn_rv$port1__read[72] &&
	     s_config_writeSlave_in$FULL_N ;
  assign s_config_writeSlave_in$DEQ =
4683
4684
4685
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 ||
Jens Korinth's avatar
Jens Korinth committed
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 ||
	     WILL_FIRE_RL_s_config_1_axiWriteFallback ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial ;
  assign s_config_writeSlave_in$CLR = 1'b0 ;

  // submodule s_config_writeSlave_out
  assign s_config_writeSlave_out$D_IN = 2'd0 ;
  assign s_config_writeSlave_out$ENQ =
4696
4697
4698
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_6 ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_5 ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_4 ||
Jens Korinth's avatar
Jens Korinth committed
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_3 ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_2 ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial_1 ||
	     WILL_FIRE_RL_s_config_1_axiWriteFallback ||
	     WILL_FIRE_RL_s_config_1_axiWriteSpecial ;
  assign s_config_writeSlave_out$DEQ =
	     s_config_writeSlave_out$EMPTY_N && S_AXI_bready ;
  assign s_config_writeSlave_out$CLR = 1'b0 ;

  // submodule writeConvBTT_ff
4709
  assign writeConvBTT_ff$sD_IN = { btt__h145195, writeIn_rv[69] } ;
Jens Korinth's avatar
Jens Korinth committed
4710
4711
4712
  assign writeConvBTT_ff$sENQ = WILL_FIRE_RL_handleWrite ;
  assign writeConvBTT_ff$dDEQ = writeConvBTT_ff$dEMPTY_N ;

Jaco Hofmann's avatar
Jaco Hofmann committed
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
  // submodule writeConverter_dataSync
  assign writeConverter_dataSync$D_IN =
	     { (writeConverter_wordInCntr == 2'd1) ?
		 m_pcie_rd_outgoingBuffer$D_OUT :
		 256'd0,
	       (writeConverter_wordInCntr == 2'd0) ?
		 m_pcie_rd_outgoingBuffer$D_OUT :
		 writeConverter_buffer_0 } ;
  assign writeConverter_dataSync$ENQ =
	     WILL_FIRE_RL_mkConnectionGetPut_3 &&
	     (writeConverter_wordInCntr == 2'd1 ||
	      writeConverter_byteCntr <= 64'd32) ;
  assign writeConverter_dataSync$DEQ =
	     fpga_request_converter$sFULL_N &&
	     writeConverter_dataSync$EMPTY_N ;
  assign writeConverter_dataSync$CLR = 1'b0 ;

Jens Korinth's avatar
Jens Korinth committed
4730
4731
4732
4733
4734
4735
  // remaining internal signals
  assign IF_0_CONCAT_readConverter_wordInCntr_EQ_1_OR_r_ETC__q1 =
	     ({ 1'd0, readConverter_wordInCntr } == 2'd1 ||
	      readConverter_byteCntr <= 64'd32) ?
	       2'd0 :
	       { 1'd0, readConverter_wordInCntr } + 2'd1 ;
4736
  assign IF_m_fpga_wr_task_data_output_reg_22_BIT_0_33__ETC___d950 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4737
4738
	     (m_fpga_wr_task_data_output_reg[0] &&
	      m_fpga_wr_task_data_output_reg[76:71] != 6'd0) ?
4739
	       endByte___1__h46830 :
Jaco Hofmann's avatar
Jaco Hofmann committed
4740
4741
4742
	       ((m_fpga_wr_task_data_output_reg[64:7] == 58'd1) ?
		  ((m_fpga_wr_task_data_output_reg[70:65] == 6'd0) ?
		     7'd64 :
4743
		     endByte___1__h46856) :
Jaco Hofmann's avatar
Jaco Hofmann committed
4744
		  7'd64) ;
4745
  assign IF_m_pcie_wr_task_data_output_reg_37_BIT_0_48__ETC___d465 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4746
4747
	     (m_pcie_wr_task_data_output_reg[0] &&
	      m_pcie_wr_task_data_output_reg[74:70] != 5'd0) ?
4748
	       endByte___1__h31594 :
Jaco Hofmann's avatar
Jaco Hofmann committed
4749
4750
4751
	       ((m_pcie_wr_task_data_output_reg[64:6] == 59'd1) ?
		  ((m_pcie_wr_task_data_output_reg[69:65] == 5'd0) ?
		     6'd32 :
4752
		     endByte___1__h31620) :
Jaco Hofmann's avatar
Jaco Hofmann committed
4753
		  6'd32) ;
4754
  assign _theResult____h26331 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4755
	     (m_pcie_wr_reqGen_incomingBuffer$D_OUT[72:68] == 5'd0) ?
4756
4757
4758
	       bytes_first__h26330 :
	       bytes_first___1__h26366 ;
  assign _theResult____h26515 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4759
	     (m_pcie_wr_reqGen_intermediateBuffer$D_OUT[141:137] == 5'd0) ?
4760
4761
	       transfers_total__h26514 :
	       transfers_total___1__h26523 ;
4762
  assign _theResult____h29471 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4763
4764
	     (m_pcie_wr_task_data_requests_reg[126:68] == 59'd1 &&
	      m_pcie_wr_task_data_requests_reg[134:127] != 8'd0) ?
4765
	       beatsThisRequest___1__h29519 :
Jaco Hofmann's avatar
Jaco Hofmann committed
4766
	       8'd63 ;
4767
  assign _theResult____h36285 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4768
	     (m_pcie_rd_reqGen_incomingBuffer$D_OUT[72:68] == 5'd0) ?
4769
4770
4771
	       bytes_first__h36284 :
	       bytes_first___1__h36320 ;
  assign _theResult____h36469 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4772
	     (m_pcie_rd_reqGen_intermediateBuffer$D_OUT[141:137] == 5'd0) ?
4773
4774
4775
	       transfers_total__h36468 :
	       transfers_total___1__h36477 ;
  assign _theResult____h40174 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4776
	     (m_fpga_wr_reqGen_incomingBuffer$D_OUT[73:68] == 6'd0) ?
4777
4778
4779
	       bytes_first__h40173 :
	       bytes_first___1__h40209 ;
  assign _theResult____h40358 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4780
	     (m_fpga_wr_reqGen_intermediateBuffer$D_OUT[143:138] == 6'd0) ?
4781
4782
4783
	       transfers_total__h40357 :
	       transfers_total___1__h40366 ;
  assign _theResult____h43299 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4784
4785
	     (m_fpga_wr_task_data_requests_reg[125:68] == 58'd1 &&
	      m_fpga_wr_task_data_requests_reg[133:126] != 8'd0) ?
4786
	       beatsThisRequest___1__h43347 :
Jaco Hofmann's avatar
Jaco Hofmann committed
4787
	       8'd255 ;
4788
  assign _theResult____h55521 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4789
	     (m_fpga_rd_reqGen_incomingBuffer$D_OUT[73:68] == 6'd0) ?
4790
4791
4792
	       bytes_first__h55520 :
	       bytes_first___1__h55556 ;
  assign _theResult____h55705 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4793
	     (m_fpga_rd_reqGen_intermediateBuffer$D_OUT[143:138] == 6'd0) ?
4794
4795
4796
	       transfers_total__h55704 :
	       transfers_total___1__h55713 ;
  assign b__h115475 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4797
4798
4799
	     byteAlignerWriter_bytes_left_in_buffer$EN_port0__write ?
	       byteAlignerWriter_bytes_left_in_buffer$port0__write_1 :
	       byteAlignerWriter_bytes_left_in_buffer ;
4800
  assign b__h72292 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4801
4802
4803
	     byteAlignerReader_bytes_left_in_buffer$EN_port0__write ?
	       byteAlignerReader_bytes_left_in_buffer$port0__write_1 :
	       byteAlignerReader_bytes_left_in_buffer ;
4804
  assign beatsThisRequestCntrT__h29979 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4805
	     m_pcie_wr_beatsThisRequestCntr + 8'd1 ;
4806
  assign beatsThisRequestCntrT__h43807 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4807
	     m_fpga_wr_beatsThisRequestCntr + 8'd1 ;
4808
  assign beatsThisRequest___1__h29519 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4809
	     m_pcie_wr_task_data_requests_reg[134:127] - 8'd1 ;
4810
  assign beatsThisRequest___1__h38705 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4811
	     m_pcie_rd_task_data_requests_reg[134:127] - 8'd1 ;
4812
  assign beatsThisRequest___1__h43347 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4813
	     m_fpga_wr_task_data_requests_reg[133:126] - 8'd1 ;
4814
  assign beatsThisRequest___1__h57938 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4815
	     m_fpga_rd_task_data_requests_reg[133:126] - 8'd1 ;
4816
4817
4818
  assign btt__h102089 = readIn_rv[63:0] + y__h102126 ;
  assign btt__h145195 = writeIn_rv[63:0] + y__h145223 ;
  assign byteAlignerReader_bytes_in_438_ULT_byteAligner_ETC___d1440 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4819
	     byteAlignerReader_bytes_in < byteAlignerReader_bytes_total ;
4820
  assign byteAlignerReader_bytes_left_in_buffer_port0___ETC___d1455 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4821
4822
	     byteAlignerReader_bytes_left_in_buffer <
	     byteAlignerReader_bytes_out_needed ;
4823
  assign byteAlignerWriter_bytes_in_560_ULT_byteAligner_ETC___d1562 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4824
	     byteAlignerWriter_bytes_in < byteAlignerWriter_bytes_total ;
4825
  assign byteAlignerWriter_bytes_left_in_buffer_port0___ETC___d1577 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4826
4827
	     byteAlignerWriter_bytes_left_in_buffer <
	     byteAlignerWriter_bytes_out_needed ;
4828
  assign bytes_first___1__h26366 = 64'd32 - bytes_first__h26330 ;
4829
4830
4831
  assign bytes_first___1__h36320 = 64'd32 - bytes_first__h36284 ;
  assign bytes_first___1__h40209 = 64'd64 - bytes_first__h40173 ;
  assign bytes_first___1__h55556 = 64'd64 - bytes_first__h55520 ;
4832
  assign bytes_first__h26330 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4833
	     { 59'd0, m_pcie_wr_reqGen_incomingBuffer$D_OUT[72:68] } ;
4834
  assign bytes_first__h36284 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4835
	     { 59'd0, m_pcie_rd_reqGen_incomingBuffer$D_OUT[72:68] } ;
4836
  assign bytes_first__h40173 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4837
	     { 58'd0, m_fpga_wr_reqGen_incomingBuffer$D_OUT[73:68] } ;
4838
  assign bytes_first__h55520 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4839
	     { 58'd0, m_fpga_rd_reqGen_incomingBuffer$D_OUT[73:68] } ;
4840
4841
  assign endByte___1__h31594 =
	     startByte___1__h31593 +
Jaco Hofmann's avatar
Jaco Hofmann committed
4842
	     { 1'd0, m_pcie_wr_task_data_output_reg[74:70] } ;
4843
  assign endByte___1__h31620 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4844
	     { 1'd0, m_pcie_wr_task_data_output_reg[69:65] } ;
4845
4846
  assign endByte___1__h46830 =
	     startByte___1__h46829 +
Jaco Hofmann's avatar
Jaco Hofmann committed
4847
	     { 1'd0, m_fpga_wr_task_data_output_reg[76:71] } ;
4848
  assign endByte___1__h46856 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4849
	     { 1'd0, m_fpga_wr_task_data_output_reg[70:65] } ;
4850
  assign fpgaLastCycle_670_AND_m_fpga_rd_task_data_outp_ETC___d1672 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4851
4852
4853
4854
	     fpgaLastCycle && m_fpga_rd_task_data_output_reg[64:7] == 58'd0 &&
	     m_fpga_rd_task_data_requests_reg[125:68] == 58'd0 &&
	     m_fpga_wr_task_data_output_reg[64:7] == 58'd0 &&
	     m_fpga_wr_task_data_requests_reg[125:68] == 58'd0 ;
Jaco Hofmann's avatar
Jaco Hofmann committed
4855
  assign m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6 =
4856
4857
	     m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h55600 ;
  assign m_fpga_wr_beatsThisRequestCntr_27_EQ_m_fpga_wr_ETC___d929 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4858
4859
	     m_fpga_wr_beatsThisRequestCntr ==
	     m_fpga_wr_beatsPerRequestFIFO$D_OUT ;
Jaco Hofmann's avatar
Jaco Hofmann committed
4860
  assign m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7 =
4861
	     m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h40253 ;
Jaco Hofmann's avatar
Jaco Hofmann committed
4862
  assign m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8 =
4863
4864
	     m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] - y__h36364 ;
  assign m_pcie_wr_beatsThisRequestCntr_42_EQ_m_pcie_wr_ETC___d444 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4865
4866
	     m_pcie_wr_beatsThisRequestCntr ==
	     m_pcie_wr_beatsPerRequestFIFO$D_OUT ;
Jaco Hofmann's avatar
Jaco Hofmann committed
4867
  assign m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9 =
4868
	     m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] - y__h26410 ;
4869
  assign pc_reqCntr_499_EQ_cycles_between_set_6_BITS_11_ETC___d1681 =
4870
	     pc_reqCntr == cycles_between_set[11:0] ;
4871
  assign pcieLastCycle_663_AND_m_pcie_rd_task_data_outp_ETC___d1665 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4872
4873
4874
4875
	     pcieLastCycle && m_pcie_rd_task_data_output_reg[64:6] == 59'd0 &&
	     m_pcie_rd_task_data_requests_reg[126:68] == 59'd0 &&
	     m_pcie_wr_task_data_output_reg[64:6] == 59'd0 &&
	     m_pcie_wr_task_data_requests_reg[126:68] == 59'd0 ;
4876
  assign request_data_address__h26655 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4877
	     { m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[131:73], 5'd0 } ;
4878
  assign request_data_address__h36609 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4879
	     { m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[131:73], 5'd0 } ;
4880
  assign request_data_address__h40498 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4881
	     { m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[131:74], 6'd0 } ;
4882
  assign request_data_address__h55845 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4883
	     { m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[131:74], 6'd0 } ;
4884
  assign request_data_requests_total__h26654 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4885
	     (m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[137:132] == 6'd0) ?
4886
4887
	       requests_total__h26618 :
	       requests_total___1__h26680 ;
4888
  assign request_data_requests_total__h36608 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4889
	     (m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[137:132] == 6'd0) ?
4890
4891
4892
	       requests_total__h36572 :
	       requests_total___1__h36634 ;
  assign request_data_requests_total__h40497 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4893
	     (m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[139:132] == 8'd0) ?
4894
4895
4896
	       requests_total__h40461 :
	       requests_total___1__h40523 ;
  assign request_data_requests_total__h55844 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4897
	     (m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[139:132] == 8'd0) ?
4898
4899
	       requests_total__h55808 :
	       requests_total___1__h55870 ;
4900
  assign requests_last__h26617 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4901
	     { 2'd0, m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[137:132] } ;
4902
  assign requests_last__h36571 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4903
	     { 2'd0, m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[137:132] } ;
4904
  assign requests_total___1__h26680 = requests_total__h26618 + 59'd1 ;
4905
4906
4907
  assign requests_total___1__h36634 = requests_total__h36572 + 59'd1 ;
  assign requests_total___1__h40523 = requests_total__h40461 + 58'd1 ;
  assign requests_total___1__h55870 = requests_total__h55808 + 58'd1 ;
4908
  assign requests_total__h26618 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4909
	     m_pcie_wr_reqGen_intermediateBuffer2$D_OUT[190:132] >> 6 ;
4910
  assign requests_total__h36572 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4911
	     m_pcie_rd_reqGen_intermediateBuffer2$D_OUT[190:132] >> 6 ;
4912
  assign requests_total__h40461 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4913
	     m_fpga_wr_reqGen_intermediateBuffer2$D_OUT[189:132] >> 8 ;
4914
  assign requests_total__h55808 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4915
	     m_fpga_rd_reqGen_intermediateBuffer2$D_OUT[189:132] >> 8 ;
4916
  assign startByte___1__h31593 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4917
	     { 1'd0, m_pcie_wr_task_data_output_reg[5:1] } ;
4918
  assign startByte___1__h46829 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4919
	     { 1'd0, m_fpga_wr_task_data_output_reg[6:1] } ;
4920
  assign transfers_total___1__h26523 = transfers_total__h26514 + 64'd1 ;
4921
4922
4923
  assign transfers_total___1__h36477 = transfers_total__h36468 + 64'd1 ;
  assign transfers_total___1__h40366 = transfers_total__h40357 + 64'd1 ;
  assign transfers_total___1__h55713 = transfers_total__h55704 + 64'd1 ;
4924
4925
  assign transfers_total__h26514 = (x__h26543 - y__h26544) >> 5 ;
  assign transfers_total__h26520 = _theResult____h26515 + 64'd1 ;
4926
4927
4928
4929
4930
4931
  assign transfers_total__h36468 = (x__h36497 - y__h36498) >> 5 ;
  assign transfers_total__h36474 = _theResult____h36469 + 64'd1 ;
  assign transfers_total__h40357 = (x__h40386 - y__h40387) >> 6 ;
  assign transfers_total__h40363 = _theResult____h40358 + 64'd1 ;
  assign transfers_total__h55704 = (x__h55733 - y__h55734) >> 6 ;
  assign transfers_total__h55710 = _theResult____h55705 + 64'd1 ;
4932
  assign x__h26336 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4933
	     (m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] <
4934
4935
	      _theResult____h26331 ||
	      _theResult____h26331 == 64'd0 &&
Jaco Hofmann's avatar
Jaco Hofmann committed
4936
4937
	      m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] < 64'd32) ?
	       m_pcie_wr_reqGen_incomingBuffer$D_OUT[67:4] :
4938
4939
	       _theResult____h26331 ;
  assign x__h26517 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4940
	     (m_pcie_wr_reqGen_intermediateBuffer$D_OUT[136:132] == 5'd0) ?
4941
4942
4943
4944
	       _theResult____h26515 :
	       transfers_total__h26520 ;
  assign x__h26543 =
	     m_pcie_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h26546 ;
4945
  assign x__h31580 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4946
4947
	     (m_pcie_wr_task_data_output_reg[0] &&
	      m_pcie_wr_task_data_output_reg[74:70] != 5'd0) ?
4948
	       startByte___1__h31593 :
Jaco Hofmann's avatar
Jaco Hofmann committed
4949
	       6'd0 ;
4950
  assign x__h36290 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4951
	     (m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] <
4952
4953
	      _theResult____h36285 ||
	      _theResult____h36285 == 64'd0 &&
Jaco Hofmann's avatar
Jaco Hofmann committed
4954
4955
	      m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] < 64'd32) ?
	       m_pcie_rd_reqGen_incomingBuffer$D_OUT[67:4] :
4956
4957
	       _theResult____h36285 ;
  assign x__h36471 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4958
	     (m_pcie_rd_reqGen_intermediateBuffer$D_OUT[136:132] == 5'd0) ?
4959
4960
4961
4962
4963
	       _theResult____h36469 :
	       transfers_total__h36474 ;
  assign x__h36497 =
	     m_pcie_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h36500 ;
  assign x__h40179 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4964
	     (m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] <
4965
4966
	      _theResult____h40174 ||
	      _theResult____h40174 == 64'd0 &&
Jaco Hofmann's avatar
Jaco Hofmann committed
4967
4968
	      m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] < 64'd64) ?
	       m_fpga_wr_reqGen_incomingBuffer$D_OUT[67:4] :
4969
4970
	       _theResult____h40174 ;
  assign x__h40360 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4971
	     (m_fpga_wr_reqGen_intermediateBuffer$D_OUT[137:132] == 6'd0) ?
4972
4973
4974
4975
4976
	       _theResult____h40358 :
	       transfers_total__h40363 ;
  assign x__h40386 =
	     m_fpga_wr_reqGen_intermediateBuffer$D_OUT[67:4] - y__h40389 ;
  assign x__h46816 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4977
4978
	     (m_fpga_wr_task_data_output_reg[0] &&
	      m_fpga_wr_task_data_output_reg[76:71] != 6'd0) ?
4979
	       startByte___1__h46829 :
Jaco Hofmann's avatar
Jaco Hofmann committed
4980
	       7'd0 ;
4981
  assign x__h55526 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4982
	     (m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] <
4983
4984
	      _theResult____h55521 ||
	      _theResult____h55521 == 64'd0 &&
Jaco Hofmann's avatar
Jaco Hofmann committed
4985
4986
	      m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] < 64'd64) ?
	       m_fpga_rd_reqGen_incomingBuffer$D_OUT[67:4] :
4987
4988
	       _theResult____h55521 ;
  assign x__h55707 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4989
	     (m_fpga_rd_reqGen_intermediateBuffer$D_OUT[137:132] == 6'd0) ?
4990
4991
4992
4993
4994
	       _theResult____h55705 :
	       transfers_total__h55710 ;
  assign x__h55733 =
	     m_fpga_rd_reqGen_intermediateBuffer$D_OUT[67:4] - y__h55736 ;
  assign x_address__h29577 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4995
	     m_pcie_wr_task_data_requests_reg[67:4] + 64'd2048 ;
4996
  assign x_address__h38734 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4997
	     m_pcie_rd_task_data_requests_reg[67:4] + 64'd2048 ;
4998
  assign x_address__h43405 =
Jaco Hofmann's avatar
Jaco Hofmann committed
4999
	     m_fpga_wr_task_data_requests_reg[67:4] + 64'd16384 ;
5000
  assign x_address__h57967 =
For faster browsing, not all history is shown. View entire blame