AxiMuxSuite.scala 3.11 KB
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package chisel.axiutils.axi4
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import  chisel.axi.Axi4._
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import  chisel.axiutils._
import  chisel.miscutils.Logging
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import  chisel3._
import  chisel3.util._
import  chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
import  chisel.axi._

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/**
 * Read test module for AxiMux:
 * Checks parallel reads from multiple AXI-MM masters.
 * @param n Number of parallel masters.
 * @param axi Implicit AXI interface configuration.
 **/
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class AxiMuxReadTestModule(val n: Int)
                          (implicit axi: Axi4.Configuration,
                           logLevel: Logging.Level) extends Module {
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  val io = IO(new Bundle {
    val afa_deq_ready = Output(UInt(n.W))
    val afa_deq_valid = Output(UInt(n.W))
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    val afa_deq_bits  = Input(Vec(n, UInt(axi.dataWidth)))
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  })
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  val mux = Module(new AxiMux(n))
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  private val asmcfg = SlaveModel.Configuration(size = Some(n * 128))
  val saxi = Module(new SlaveModel(asmcfg))
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  private val afacfg = AxiFifoAdapter.Configuration(fifoDepth = 8, burstSize = Some(4))
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  val afa = for (i <- 0 until n) yield Module(new AxiFifoAdapter(afacfg))
  val bases = (0 until n) map (_ * 128 * (axi.dataWidth / 8))

  mux.io.maxi <> saxi.io.saxi
  ((afa zip mux.io.saxi) zip bases) map { case ((a, s), b) => {
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    a.io.maxi      <> s
    a.io.base      := b.U
    a.io.deq.ready := true.B
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  }}
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  afa.zipWithIndex map { case (a, i) =>
    io.afa_deq_ready(i) := a.io.deq.ready
    io.afa_deq_valid(i) := a.io.deq.valid
    io.afa_deq_bits(i)  <> a.io.deq.bits
  }
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}

/**
 * Unit test for reading across an AxiMux module:
 * Connects multiple AxiFifoAdapters with increasing base addresses 
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 * to single SlaveModel and checks the data for correctness.
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 * No performance measurement!
 * @param m Test module.
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 * @param isTrace if true, will enable tracing in Chisel PeekPokeTester.
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 **/
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class AxiMuxReadTester(m: AxiMuxReadTestModule)
                      (implicit axi: Axi4.Configuration) extends PeekPokeTester(m) {
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  implicit val tester = this
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  //SlaveModel.fillWithLinearSeq(m.saxi, axi.dataWidth)
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  reset(10)

  var counter: Array[Int] = Array.fill[Int](m.n)(0)
  def finished: Boolean = counter map (_ >= 128) reduce (_&&_)
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  def handshake(i: Int) = peek(m.io.afa_deq_ready) != 0 && peek(m.io.afa_deq_valid) != 0
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  while (! finished) {
    for (i <- 0 until m.n if handshake(i)) {
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      val ok = peek(m.io.afa_deq_bits(i)) == counter(i) + i * 128
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      assert(ok)
      if (ok) counter(i) += 1
    }
    step(1)
  }
}

/**
 * Unit test suit for AxiMux.
 **/
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class AxiMuxSuite extends ChiselFlatSpec {
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  implicit val logLevel = Logging.Level.Info
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  val chiselArgs = Array("--fint-write-vcd")
  implicit val axi = Axi4.Configuration(addrWidth = AddrWidth(32), dataWidth = DataWidth(64))
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  private def testMuxRead(n: Int) = {
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    val args = chiselArgs ++ Array("--target-dir", "test/AxiMuxSuite/%02d".format(n))
    Driver.execute(args, () => new AxiMuxReadTestModule(n))
      { m => new AxiMuxReadTester(m) }
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  }

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  "testMuxRead1" should "be ok" in  { testMuxRead( 1) }
  "testMuxRead2" should "be ok" in  { testMuxRead( 2) }
  "testMuxRead3" should "be ok" in  { testMuxRead( 3) }
  "testMuxRead10" should "be ok" in { testMuxRead(10) }
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}