Registers.scala 2.88 KB
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package chisel.axi.axi4lite
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import  chisel.axi._
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import  Chisel.{Reg, UInt}
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/**
 * Abstract base class for control registers.
 * Provides base methods for describing and accessing control register data.
 * @param _name Name of the register (optional).
 * @param bitfield Bit partitioning of the value (optional).
 **/
sealed abstract class ControlRegister(_name: Option[String], bitfield: BitfieldMap = Map()) {
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  /** Format description string for bitfield (if any). */
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  private def bf: String = bitfield.toList.sortWith((a, b) => a._2.to > b._2.to) map (e =>
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      if (e._2.to == e._2.from) {
        "_%d:_ %s".format(e._2.to, e._1)
      } else {
        "_%d-%d:_ %s".format(e._2.to, e._2.from, e._1)
      }
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    ) mkString (" ")

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  /** Name of the register. */
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  def name: Option[String] = _name

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  /** Description of the register. */
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  def description: String  = if (bitfield.size > 0) bf else _name.getOrElse("Reserved")
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  /** Access to named bit range. */
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  def apply(s: String): Option[UInt] = read() map { v =>
    bitfield getOrElse (s, None) match { case BitRange(to, from) => v(to, from) }
  }
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  /** Perform Chisel wiring to value. */
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  def write(v: UInt): UInt = Response.slverr
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  /** Perform Chisel read on value. **/
  def read(): Option[UInt]
}

/**
 * Control register with an constant value (no write).
 * @param name Name of the register (optional).
 * @param bitfield Bit partitioning of the value (optional).
 * @param value Constant value for the register.
 **/
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class ConstantRegister(name: Option[String] = None, bitfield: BitfieldMap = Map(), val value: BigInt)
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    extends ControlRegister(name, bitfield) {
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  override def description: String = "%s - _const:_ 0x%x (%d)".format(super.description, value, value)
  def read(): Option[UInt] = Some(UInt(value))
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  override lazy val toString: String = s"%s: 0x%x (%d)".format(name getOrElse "const", value, value)
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}

/**
 * Basic register with internal Chisel Reg (read/write).
 * @param name Name of the register (optional).
 * @param bitfield Bit partitioning of the value (optional).
 **/
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class Register(name: Option[String] = None, bitfield: BitfieldMap = Map(), width: Int)
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    extends ControlRegister(name, bitfield) {
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  private lazy val _r = Reg(UInt(width = width))
  def read(): Option[UInt] = Some(_r)
  override def write(v: UInt) = {
    _r := v
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    Response.okay
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  }
}

/**
 * Virtual register: read and write callbacks are triggered on access.
 * @param name Name of the register (optional).
 * @param bitfield Bit partitioning of the value (optional).
 * @param onRead Callback for read access.
 * @param onWrite Callback for write access.
 **/
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class VirtualRegister(name: Option[String] = None,
                      bitfield: BitfieldMap = Map(),
                      onRead: () => Option[UInt],
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                      onWrite: UInt => UInt) extends ControlRegister(name, bitfield) {
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  def read() = onRead()
  override def write(v: UInt) = onWrite(v)
}