• Jens Korinth's avatar
    Closes #5 - VC709: Support multiple FPGAs in JTAG chain · 310d1be1
    Jens Korinth authored
    * scanning all targets and devices, programming the first VX690T
    * improved the bit_reload.sh scripts:
       - normal option parsing
       - enabled verbose output w/o driver reload
       - disabled 'default' bitstream (I mean, WTF?)
    * moved bit_reload in VC709 into standard location in module