• Jens Korinth's avatar
    Fix reset behavior in RegisterFile · 325673de
    Jens Korinth authored
    * AXI mandates that all ready signals be low during reset
    * unfortunately, not only is this not the case in Queues, but they
      actively start working while reset is high (insane)
    * fixed by manually pulling the signals low on reset
    * tested with Xilinx AXI Verification IP, all's well