* two scripts to generate block designs that will use AxiFifoAdapter
  and FifoAxiAdapter with the Cadence AXI BFMs
* server also as cross-verification of Chisel AXI slave model
* checks are not automated, results must be verified manually
* AxiFifoAdapter uses Zynq BFM to preload DDR memory
* added testbench and memory preload data for AxiFifoAdapter project
* also added source code of preload file generator