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  • Jens Korinth's avatar
    Fix problems with clocks and resets bridges · 8a43f455
    Jens Korinth authored
    * found a way to express in IP-XACT that the interfaces are only bridged
      directly; there seems to be no way of doing this via Vivado, but since
      Xilinx is using it themselves (e.g., System Cache) I hope it'll work
    * also remove interconnect_reset port, since they do not exist on the
      reset generators
    8a43f455