• Jens Korinth's avatar
    Closes #51 - Parse component.xml to exclude Verilog includes · a1dc2f2e
    Jens Korinth authored
    * LS patched this on TPC, forward ported it to TaPaSCo:
    * OOC must extract Verilog includes, but must not add them via add_files
    * hard to determine what an 'include' is, but IP-XACT component.xml
      contains this information -> parsed to an exclusion set
    * confirmed to work with example from LS and standard "counter"
    a1dc2f2e
EvaluateIP.scala 8.65 KB