Commit 02193e96 authored by Carsten Heinz's avatar Carsten Heinz
Browse files

Versal basic platform design

parent 1502a621
......@@ -31,3 +31,5 @@ dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:5.0"
dict set stdcomps util_buf vlnv "xilinx.com:ip:util_ds_buf:2.2"
dict set stdcomps axi_iic vlnv "xilinx.com:ip:axi_iic:2.1"
dict set stdcomps hbm vlnv "xilinx.com:ip:hbm:1.0"
dict set stdcomps versal_cips vlnv "xilinx.com:ip:versal_cips:3.1"
dict set stdcomps axi_noc vlnv "xilinx.com:ip:axi_noc:1.0"
......@@ -43,6 +43,7 @@ dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:3.0"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:tapasco:tapasco_status:1.4"
dict set stdcomps axi_pcie3_0_usp vlnv "xilinx.com:ip:xdma:3.1"
dict set stdcomps clk_wiz vlnv "xilinx.com:ip:clk_wiz:5.4"
dict set stdcomps clk_wizard vlnv "xilinx.com:ip:clk_wizard:1.0"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axioffset vlnv "esa.informatik.tu-darmstadt.de:user:AXIOffset:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
......@@ -64,6 +65,7 @@ dict set stdcomps axi_bram_ctrl vlnv "xilinx.com:ip:axi_bram_ctrl"
dict set stdcomps bram_ctrl vlnv "xilinx.com:ip:blk_mem_gen"
dict set stdcomps versal_emb_mem_gen vlnv "xilinx.com:ip:emb_mem_gen"
dict set stdcomps axi_gpio vlnv "xilinx.com:ip:axi_gpio:2.0"
dict set stdcomps qdma vlnv "xilinx.com:ip:qdma:4.0"
dict set stdcomps axioffset_hbm vlnv "esa.informatik.tu-darmstadt.de:user:AXIOffsetHBM:1.0"
dict set stdcomps sume_clock_prog vlnv "esa.informatik.tu-darmstadt.de:user:SumeClockProgrammer:1.0"
dict set stdcomps dmi vlnv "esa.informatik.tu-darmstadt.de:user:DMI_rtl:1.0"
......
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