Commit 027726dd authored by Johannes Wirth's avatar Johannes Wirth
Browse files

update zynq ultra ps version

parent 9604727c
Pipeline #2586 passed with stages
in 260 minutes and 54 seconds
......@@ -23,7 +23,7 @@ dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.1"
dict set stdcomps axi_pcie3_0_usp vlnv "xilinx.com:ip:xdma:4.1"
dict set stdcomps clk_wiz vlnv "xilinx.com:ip:clk_wiz:6.0"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.2"
dict set stdcomps ultra_ps vlnv "xilinx.com:ip:zynq_ultra_ps_e:3.3"
dict set stdcomps ultra_ps vlnv "xilinx.com:ip:zynq_ultra_ps_e:3.4"
dict set stdcomps xxv_ethernet vlnv "xilinx.com:ip:xxv_ethernet:4.1"
dict set stdcomps 100g_ethernet vlnv "xilinx.com:ip:cmac_usplus:3.1"
dict set stdcomps aurora vlnv "xilinx.com:ip:aurora_64b66b:12.0"
......
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