Commit 03d74ebf authored by Jens Korinth's avatar Jens Korinth
Browse files

Closes #71 - Rename baseline to axi4mm

* baseline sounds suboptimal and does not give any idea towards the kind
  of Architecture
* since it is based on AXI4 memory mapped interfaces it is renamed to
  axi4mm
* fixed all occurrences of baseline
parent 766370fb
......@@ -18,7 +18,7 @@ Terminology
* _Architecture_
The basic template for your hardware thread pool, i.e., the organisation
of your _Core instances. Currently there is only one such _Architecture_
called `baseline`.
called `axi4mm`.
* _ThreadPool_
Consists of a number of _Processing Elements (PEs)_, which can all operate
......@@ -253,7 +253,7 @@ logfiles, you can watch them via `tail --follow <FILE>` on a separate shell,
if you like.
If everything went well, there should be a `.bit` file in
`$TAPASCO_HOME/bd/<YOUR BD>/baseline/zedboard` afterwards (refer to the logging
`$TAPASCO_HOME/bd/<YOUR BD>/axi4mm/zedboard` afterwards (refer to the logging
output for the value of `<YOUR BD>` - if you had used an external _Composition_
description file, it would use that name instead of the hash).
......
cmake_minimum_required(VERSION 2.6)
project(arch-baseline)
project(arch-axi4mm)
set(CMAKE_INSTALL_PREFIX "..")
set(CMAKE_SKIP_RPATH true)
......
{
"Name" : "axi4mm",
"Description" : "Architecture based on AXI4 memory-mapped master/slave interfaces.",
"TclLibrary" : "axi4mm.tcl",
"HLSTclTemplate" : "../../common/hls.tcl.template"
}
......@@ -16,12 +16,8 @@
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
# @file baseline.tcl
# @brief Baseline architecture implementation: Connects up to 64 cores
# (resp. 64 master interfaces, 256 slaves interfaces), host
# connection to AXI slaves via GP0 and a two-level interconnect
# hierarchy, memory connection from AXI masters via independent
# interconnects to HP0-2.
# @file axi4mm.tcl
# @brief AXI4 memory mapped master/slave interface based Architectures.
# @author J. Korinth, TU Darmstadt (jk@esa.tu-darmstadt.de)
#
namespace eval arch {
......@@ -37,14 +33,14 @@ namespace eval arch {
set arch_irq_concats [list]
# scan plugin directory
foreach f [glob -nocomplain -directory "$::env(TAPASCO_HOME)/arch/baseline/plugins" "*.tcl"] {
foreach f [glob -nocomplain -directory "$::env(TAPASCO_HOME)/arch/axi4mm/plugins" "*.tcl"] {
source -notrace $f
}
# Returns a list of the bd_cells of slave interfaces of the threadpool.
proc get_slaves {} {
set inst [current_bd_instance]
current_bd_instance "Threadpool"
current_bd_instance "Architecture"
set r [list [get_bd_intf_pins -of [get_bd_cells "in1"] -filter { MODE == "Slave" }]]
current_bd_instance $inst
return $r
......@@ -57,12 +53,12 @@ namespace eval arch {
}
proc get_processing_elements {} {
return [get_bd_cells "Threadpool/target*"]
return [get_bd_cells "Architecture/target*"]
}
# Returns a list of interrupt lines from the threadpool.
proc get_irqs {} {
return [get_bd_pins -of_objects [get_bd_cells "Threadpool"] -filter {TYPE == "intr" && DIR == "O"}]
return [get_bd_pins -of_objects [get_bd_cells "Architecture"] -filter {TYPE == "intr" && DIR == "O"}]
}
# Checks, if the current composition can be instantiated. Exits script with
......@@ -380,7 +376,7 @@ namespace eval arch {
}
# create hierarchical group
set group [create_bd_cell -type hier "Threadpool"]
set group [create_bd_cell -type hier "Architecture"]
set instance [current_bd_instance .]
current_bd_instance $group
......
{
"Name" : "baseline",
"Description" : "Baseline Architecture with SW-based thread pool control.",
"TclLibrary" : "baseline.tcl",
"HLSTclTemplate" : "../../common/hls.tcl.template"
}
......@@ -27,7 +27,7 @@ print('Platform: ' + os.environ['TAPASCO_PLATFORM'])
moddir = '$TAPASCO_HOME/platform/$TAPASCO_PLATFORM/module'
pdir = '$TAPASCO_HOME/platform/$TAPASCO_PLATFORM/build'
adir = '$TAPASCO_HOME/arch/baseline/build'
adir = '$TAPASCO_HOME/arch/axi4mm/build'
tdir = '$TAPASCO_HOME/arch/tests/build'
if clean or args.rebuild:
......
Architecture = baseline
Platform = zynq
Bitstream = arrayinit.bd
Architecture = baseline
Platform = zynq
Bitstream = arraysum.bd
{"Platforms":["zedboard","zc706","vc709"],"Architectures":["baseline"],"DesignSpaceExploration":"freq","Compositions":["basic_test.bd"],"PlatformFeatures":{"LED":{"Enabled":true},"OLED":{"Enabled":true},"Cache":{"Enabled":false,"Size":32768,"Associativity":2},"Debug":{"Enabled":false,"Depth":2048,"Stages":2}}}
{"Platforms":["zedboard","zc706","vc709"],"Architectures":["axi4mm"],"DesignSpaceExploration":"freq","Compositions":["basic_test.bd"],"PlatformFeatures":{"LED":{"Enabled":true},"OLED":{"Enabled":true},"Cache":{"Enabled":false,"Size":32768,"Associativity":2},"Debug":{"Enabled":false,"Depth":2048,"Stages":2}}}
# Example configuration: baseline, zynq, 48 instances of readwrite1.
Architecture = baseline
Platform = zynq
Bitstream = warraw.bd
{
"Name" : "baseline",
"Name" : "axi4mm",
"Description" : "Baseline Architecture with SW-based thread pool control.",
"TestAPI" : "test-api.svh",
"TestHarness" : "test-harness.svh",
"VerilogIncludeAPI" : "test-api.svh",
"VerilogIncludeHarness" : "test-harness.svh",
"TclLibrary" : "baseline.tcl"
"TclLibrary" : "axi4mm.tcl"
}
......@@ -4,7 +4,7 @@
"Version" : "0.1",
"Id" : 42,
"Target": {
"Architecture": "baseline",
"Architecture": "axi4mm",
"Platform": "zedboard"
},
"Description" : "A correct core description.",
......
......@@ -5,6 +5,6 @@
"TestHarness" : "test-harness.svh",
"VerilogIncludeAPI" : "test-api.svh",
"VerilogIncludeHarness" : "test-harness.svh",
"TclLibrary" : "baseline.tcl",
"TclLibrary" : "axi4mm.tcl",
"UnknownKey2" : "should be ignored"
}
......@@ -5,7 +5,7 @@
"Id" : 42,
"Description" : "A correct core description.",
"Target": {
"Architecture": "baseline",
"Architecture": "axi4mm",
"Platform": "zc706"
}
}
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