Closes #71 - Rename baseline to axi4mm

* baseline sounds suboptimal and does not give any idea towards the kind
  of Architecture
* since it is based on AXI4 memory mapped interfaces it is renamed to
  axi4mm
* fixed all occurrences of baseline

json-examples/invalid-core2.json

@@ -4,7 +4,7 @@
 	"Version" : "0.1",
 	"Description" : "A correct core description.",
 	"Target": {
-		"Architecture": "baseline",
+		"Architecture": "axi4mm",
 		"Platform": "zc706"
 	}
 }

json-examples/invalid-core3.json

@@ -4,7 +4,7 @@
 	"Id" : 42,
 	"Description" : "A correct core description.",
 	"Target": {
-		"Architecture": "baseline",
+		"Architecture": "axi4mm",
 		"Platform": "zc706"
 	}
 }

json-examples/invalid-core4.json

@@ -4,7 +4,7 @@
 	"Id" : 42,
 	"Description" : "A correct core description.",
 	"Target": {
-		"Architecture": "baseline",
+		"Architecture": "axi4mm",
 		"Platform": "zc706"
 	}
 }

json-examples/jobs/ComposeJob.json

@@ -12,7 +12,7 @@
   },
   "Design Frequency" : 123,
   "Implementation" : "Vivado",
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "pynq", "zedboard" ],
   "DebugMode" : "r"
 }
\ No newline at end of file

json-examples/jobs/CoreStatisticsJob.json

 {
   "Job" : "CoreStatistics",
   "File Prefix" : "somePrefix_",
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "vc709", "zc706" ]
 }
\ No newline at end of file

json-examples/jobs/DesignSpaceExplorationJob.json

@@ -19,7 +19,7 @@
   "Heuristic" : "Job Throughput",
   "Batch Size" : 16,
   "Output Path" : "nonstandard/base/path",
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "pynq", "vc709" ],
   "DebugMode" : "r"
 }
\ No newline at end of file

json-examples/jobs/HighLevelSynthesisJob.json

 {
   "Job" : "HighLevelSynthesis",
   "Implementation" : "VivadoHLS",
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "zedboard", "zc706" ],
   "Kernels" : [ "counter", "arraysum" ]
 }
\ No newline at end of file

json-examples/jobs/ImportJob.json

@@ -4,6 +4,6 @@
   "Id" : 42,
   "Description" : "Optional description of the core.",
   "Average Clock Cycles" : 13124425,
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "zedboard", "zc706" ]
 }
\ No newline at end of file

json-examples/jobs/Jobs.json

@@ -15,13 +15,13 @@
   },
   "Design Frequency" : 123,
   "Implementation" : "Vivado",
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "pynq", "zedboard" ],
   "DebugMode" : "r"
 }, {
   "Job" : "CoreStatistics",
   "File Prefix" : "somePrefix_",
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "vc709", "zc706" ]
 }, {
   "Job" : "DesignSpaceExploration",
@@ -44,13 +44,13 @@
   "Heuristic" : "Job Throughput",
   "Batch Size" : 16,
   "Output Path" : "nonstandard/base/path",
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "pynq", "vc709" ],
   "DebugMode" : "r"
 }, {
   "Job" : "HighLevelSynthesis",
   "Implementation" : "VivadoHLS",
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "zedboard", "zc706" ],
   "Kernels" : [ "counter", "arraysum" ]
 }, {
@@ -59,6 +59,6 @@
   "Id" : 42,
   "Description" : "Optional description of the core.",
   "Average Clock Cycles" : 13124425,
-  "Architectures" : [ "baseline" ],
+  "Architectures" : [ "axi4mm" ],
   "Platforms" : [ "zedboard", "zc706" ]
 } ]
\ No newline at end of file

json-examples/missing-file-arch.json

 {
-	"Name" : "baseline",
+	"Name" : "axi4mm",
 	"Description" : "Baseline Architecture with SW-based thread pool control.",
 	"TestAPI" : "test-api.svh",
 	"TestHarness" : "test-harness.svh",

json-examples/unknown-arch.json

 {
 	"UnknownKey" : ["Some", "Stuff"],
-	"Name" : "baseline",
+	"Name" : "axi4mm",
 	"Description" : "Baseline Architecture with SW-based thread pool control.",
 	"TestAPI" : "test-api.svh",
 	"TestHarness" : "test-harness.svh",
 	"VerilogIncludeAPI" : "test-api.svh",
 	"VerilogIncludeHarness" : "test-harness.svh",
-	"TclLibrary" : "baseline.tcl",
+	"TclLibrary" : "axi4mm.tcl",
 	"UnknownKey2" : "should be ignored"
 }

json-examples/unknown-core.json

@@ -5,13 +5,13 @@
 	"Version" : "0.1",
 	"Id" : 42,
 	"Target": {
-		"Architecture": "baseline",
+		"Architecture": "axi4mm",
 		"Platform": "vc709"
 	},
 	"Description" : "A correct core description.",
 	"AnotherKey" : 123,
 	"Target": {
-		"Architecture": "baseline",
+		"Architecture": "axi4mm",
 		"Platform": "vc709"
 	}
 }

kernel/rot13/CMakeLists.txt

@@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 2.6)
 project (rot13)
 
 include_directories("$ENV{TAPASCO_HOME}/arch/common/include" "$ENV{TAPASCO_HOME}/platform/common/include")
-link_directories("$ENV{TAPASCO_HOME}/arch/baseline/lib/${CMAKE_SYSTEM_PROCESSOR}" "$ENV{TAPASCO_HOME}/platform/vc709/lib/${CMAKE_SYSTEM_PROCESSOR}")
+link_directories("$ENV{TAPASCO_HOME}/arch/axi4mm/lib/${CMAKE_SYSTEM_PROCESSOR}" "$ENV{TAPASCO_HOME}/platform/vc709/lib/${CMAKE_SYSTEM_PROCESSOR}")
 
 add_executable(rot13 rot13.cpp)
 add_executable(tapasco-rot13 tapasco_rot13.cpp)

kernel/sudoku/src/compile.sh

@@ -17,4 +17,4 @@
 # You should have received a copy of the GNU Lesser General Public License
 # along with Tapasco.  If not, see <http://www.gnu.org/licenses/>.
 #
-${CROSS_COMPILE}g++ -o sudoku_mt -std=c++11 -Wall -Werror -g -pthread -I/scratch/jk/rcu/arch/common/include -I/scratch/jk/rcu/platform/common/include -L/scratch/jk/rcu/arch/baseline/lib/${ARCH} -L/scratch/jk/rcu/platform/zynq/lib/${ARCH} -lrt -ltapasco -lplatform-client multithreaded.cpp Sudoku.cpp Sudoku_HLS.cpp
+${CROSS_COMPILE}g++ -o sudoku_mt -std=c++11 -Wall -Werror -g -pthread -I/scratch/jk/rcu/arch/common/include -I/scratch/jk/rcu/platform/common/include -L/scratch/jk/rcu/arch/axi4mm/lib/${ARCH} -L/scratch/jk/rcu/platform/zynq/lib/${ARCH} -lrt -ltapasco -lplatform-client multithreaded.cpp Sudoku.cpp Sudoku_HLS.cpp

man/man7/tapasco-concepts.7

@@ -83,7 +83,7 @@ The main Tcl script of the Architecture generates a pre-wired cell called the
 \'thread pool\' in which all PEs are instantiated and all their interfaces are
 wired to macro-cell inputs/outputs.
 .PP
-Example: The \'baseline\' Architecture uses AXI4Lite interfaces for the control
+Example: The \'axi4mm\' Architecture uses AXI4Lite interfaces for the control
 registers of the PEs, AXI4-MM master interfaces for memory accesses of the PEs
 and single wire, level-sensitive interrupt lines for signaling. The PEs are
 connected using AXI Interconnect hierarchies.

platform/zynq/buildLibs.py

@@ -8,7 +8,7 @@ driver_debug = len(sys.argv) > 1 and sys.argv[1] == "driver_debug"
 
 moddir = "$TAPASCO_HOME/platform/zynq/module"
 pdir = "$TAPASCO_HOME/platform/zynq/build"
-adir = "$TAPASCO_HOME/arch/baseline/build"
+adir = "$TAPASCO_HOME/arch/axi4mm/build"
 
 if clean:
 	subprocess.call(["rm -rf " + pdir], shell=True)

sim_setup.sh

-#
-# Copyright (C) 2014 Jens Korinth, TU Darmstadt
-#
-# This file is part of Tapasco (TPC).
-#
-# Tapasco is free software: you can redistribute it and/or modify
-# it under the terms of the GNU Lesser General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# Tapasco is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU Lesser General Public License for more details.
-#
-# You should have received a copy of the GNU Lesser General Public License
-# along with Tapasco.  If not, see <http://www.gnu.org/licenses/>.
-#
-export ARCH=`uname -m`
-export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$TAPASCO_HOME/arch/baseline/lib/$ARCH:$TAPASCO_HOME/platform/zynq/lib/$ARCH
-export LIBPLATFORM_SERVER_LIB=$TAPASCO_HOME/platform/zynq/lib/$ARCH/libplatform-server
-export LIBPLATFORM_DEBUG=0xffffffff
-

src/main/scala/tapasco/base/Configuration.scala

@@ -52,7 +52,7 @@ trait Configuration {
     coreDir.resolve(kernel.name.toString).resolve(target.ad.name).resolve(target.pd.name)
 
   /** Returns the default output directory for the given composition, target and frequency.
-   *  _Example_: `arrayinit__counter/020_042/075.0/baseline/pynq`
+   *  _Example_: `arrayinit__counter/020_042/075.0/axi4mm/pynq`
    */
   def outputDir(composition: Composition, target: Target, freq: Heuristics.Frequency): Path = compositionDir
     .resolve(target.ad.name)

src/main/scala/tapasco/jobs/JobExamples.scala

@@ -19,12 +19,12 @@ object JobExamples {
   val composeJob = ComposeJob(composition,
                               123.0,
                               "Vivado",
-                              Some(Seq("baseline")),
+                              Some(Seq("axi4mm")),
                               Some(Seq("pynq", "zedboard")),
                               None, // FIXME Features missing
                               Some("r"))
   val coreStatisticsJob = CoreStatisticsJob(Some("somePrefix_"),
-                                            Some(Seq("baseline")),
+                                            Some(Seq("axi4mm")),
                                             Some(Seq("vc709", "zc706")))
   val dseJob = DesignSpaceExplorationJob(composition,
                                          123.0,
@@ -32,19 +32,19 @@ object JobExamples {
                                          Heuristics.ThroughputHeuristic,
                                          16,
                                          Some(Paths.get("nonstandard/base/path")),
-                                         Some(Seq("baseline")),
+                                         Some(Seq("axi4mm")),
                                          Some(Seq("pynq", "vc709")),
                                          None, // FIXME Features missing
                                          Some("r"))
   val hlsJob = HighLevelSynthesisJob("VivadoHLS",
-                                     Some(Seq("baseline")),
+                                     Some(Seq("axi4mm")),
                                      Some(Seq("zedboard", "zc706")),
                                      Some(Seq("counter", "arraysum")))
   val importJob = ImportJob(Paths.get("path/to/ipxact-archive.zip"),
                             42,
                             Some("Optional description of the core."),
                             Some(13124425),
-                            Some(Seq("baseline")),
+                            Some(Seq("axi4mm")),
                             Some(Seq("zedboard", "zc706")))
 
   val jobs: Seq[Job] = Seq(bulkImportJob, composeJob, coreStatisticsJob, dseJob, hlsJob, importJob)

src/test/scala/tapasco/base/ArchitectureTest.scala

@@ -41,8 +41,8 @@ class ArchitectureSpec extends FlatSpec with Matchers {
     val oc = Architecture.from(jsonPath.resolve("correct-arch.json"))
     lazy val c = oc.right.get
     assert(oc.isRight)
-    c.name should equal ("baseline")
-    c.tclLibrary should equal (jsonPath.resolve("baseline.tcl"))
+    c.name should equal ("axi4mm")
+    c.tclLibrary should equal (jsonPath.resolve("axi4mm.tcl"))
     c.valueArgTemplate should equal (jsonPath.resolve("valuearg.directives.template"))
     c.referenceArgTemplate should equal (jsonPath.resolve("referencearg.directives.template"))
   }
@@ -51,8 +51,8 @@ class ArchitectureSpec extends FlatSpec with Matchers {
     val oc = Architecture.from(jsonPath.resolve("unknown-arch.json"))
     lazy val c = oc.right.get
     assert(oc.isRight)
-    c.name should equal ("baseline")
-    c.tclLibrary should equal (jsonPath.resolve("baseline.tcl"))
+    c.name should equal ("axi4mm")
+    c.tclLibrary should equal (jsonPath.resolve("axi4mm.tcl"))
     c.valueArgTemplate should equal (jsonPath.resolve("valuearg.directives.template"))
     c.referenceArgTemplate should equal (jsonPath.resolve("referencearg.directives.template"))
   }