Commit 03d74ebf authored by Jens Korinth's avatar Jens Korinth
Browse files

Closes #71 - Rename baseline to axi4mm

* baseline sounds suboptimal and does not give any idea towards the kind
  of Architecture
* since it is based on AXI4 memory mapped interfaces it is renamed to
  axi4mm
* fixed all occurrences of baseline
parent 766370fb
......@@ -60,11 +60,11 @@ class FileAssetManagerSpec extends FlatSpec with Matchers {
"Creating new core.jsons during runtime" should "be reflected in the caches" in {
val p = Files.createTempDirectory("tapasco-fileassetmanager-")
val d = p.resolve("Test").resolve("baseline").resolve("vc709").resolve("ipcore")
val d = p.resolve("Test").resolve("axi4mm").resolve("vc709").resolve("ipcore")
Files.createDirectories(d)
FileAssetManager.basepath(Entities.Cores).set(p)
assert(FileAssetManager.entities.cores.size == 0)
val zip = d.resolve("test_baseline.zip")
val zip = d.resolve("test_axi4mm.zip")
val cf = d.resolve("core.json")
Files.createFile(zip)
val t = Target(FileAssetManager.entities.architectures.toSeq.head, FileAssetManager.entities.platforms.toSeq.head)
......
......@@ -47,10 +47,10 @@ class ReportManagerSpec extends FlatSpec with Matchers {
}
private def setupStructure(p: Path): (Path, Path, Path, Path) = {
val cosimPath = p.resolve("arraysum").resolve("baseline").resolve("vc709").resolve("ipcore")
val cosimPath = p.resolve("arraysum").resolve("axi4mm").resolve("vc709").resolve("ipcore")
val powerPath = p.resolve("arrayinit").resolve("blueline").resolve("zedboard").resolve("ipcore")
val synthPath = p.resolve("aes").resolve("blackline").resolve("zc706").resolve("ipcore")
val timingPath = p.resolve("test").resolve("baseline").resolve("zc706").resolve("ipcore")
val timingPath = p.resolve("test").resolve("axi4mm").resolve("zc706").resolve("ipcore")
Files.createDirectories(cosimPath)
Files.createDirectories(powerPath)
Files.createDirectories(synthPath)
......@@ -79,7 +79,7 @@ class ReportManagerSpec extends FlatSpec with Matchers {
assert(rc.powerReports.size == 1)
assert(rc.timingReports.size == 1)
val r1 = rc.cosimReport("arraysum", "baseline", "vc709")
val r1 = rc.cosimReport("arraysum", "axi4mm", "vc709")
assert(r1.nonEmpty)
assert(r1.get.latency.avg == 280)
......@@ -92,7 +92,7 @@ class ReportManagerSpec extends FlatSpec with Matchers {
assert(r3.get.area.nonEmpty)
assert(r3.get.area.get.resources.FF == 776)
val r4 = rc.timingReport("test", "baseline", "zc706")
val r4 = rc.timingReport("test", "axi4mm", "zc706")
assert(r4.nonEmpty)
assert(r4.get.worstNegativeSlack == -5.703)
......@@ -116,7 +116,7 @@ class ReportManagerSpec extends FlatSpec with Matchers {
assert(rc.powerReports.size == 1)
assert(rc.timingReports.size == 1)
val r1 = rc.cosimReport("arraysum", "baseline", "vc709")
val r1 = rc.cosimReport("arraysum", "axi4mm", "vc709")
assert(r1.nonEmpty)
assert(r1.get.latency.avg == 280)
......@@ -125,7 +125,7 @@ class ReportManagerSpec extends FlatSpec with Matchers {
StandardCopyOption.REPLACE_EXISTING)
Thread.sleep(FS_SLEEP)
val r2 = rc.cosimReport("arraysum", "baseline", "vc709")
val r2 = rc.cosimReport("arraysum", "axi4mm", "vc709")
assert(r2.nonEmpty)
assert(r2.get.latency.avg == 2279)
......
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