Commit 0608e988 authored by Jaco Hofmann's avatar Jaco Hofmann
Browse files

Adds newest BlueDMA version

    - PCIE Burst Length 64
    - FPGA Burst Length 256
    - Alignment 32 Bytes
    - Fixes SUPPORTS_NARROW_BURST parameters
    - Adds NUM_READ_OUTSTANDING and NUM_WRITE_OUTSTANDING to help
    interconnects decide on the DMA features
parent 2785e65e
...@@ -528,6 +528,20 @@ ...@@ -528,6 +528,20 @@
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
</spirit:portMaps> </spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>m64_axi</spirit:name> <spirit:name>m64_axi</spirit:name>
...@@ -890,6 +904,20 @@ ...@@ -890,6 +904,20 @@
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
</spirit:portMaps> </spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>s_axi_aresetn</spirit:name> <spirit:name>s_axi_aresetn</spirit:name>
...@@ -1096,7 +1124,7 @@ ...@@ -1096,7 +1124,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>ded3be7f</spirit:value> <spirit:value>6dca3063</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -1112,7 +1140,7 @@ ...@@ -1112,7 +1140,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>ded3be7f</spirit:value> <spirit:value>6dca3063</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -2983,7 +3011,7 @@ ...@@ -2983,7 +3011,7 @@
<spirit:file> <spirit:file>
<spirit:name>src/mkBlueDMAVivado.v</spirit:name> <spirit:name>src/mkBlueDMAVivado.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType> <spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_578878b6</spirit:userFileType> <spirit:userFileType>CHECKSUM_031e6e27</spirit:userFileType>
</spirit:file> </spirit:file>
</spirit:fileSet> </spirit:fileSet>
<spirit:fileSet> <spirit:fileSet>
...@@ -3055,17 +3083,17 @@ ...@@ -3055,17 +3083,17 @@
<xilinx:displayName>BlueDMA</xilinx:displayName> <xilinx:displayName>BlueDMA</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource> <xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision> <xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-06T11:01:37Z</xilinx:coreCreationDateTime> <xilinx:coreCreationDateTime>2017-07-07T08:39:29Z</xilinx:coreCreationDateTime>
<xilinx:tags> <xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/> <xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags> </xilinx:tags>
</xilinx:coreExtensions> </xilinx:coreExtensions>
<xilinx:packagingInfo> <xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion> <xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="4abcc88b"/> <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9aa6aa20"/>
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/> <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/> <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d8fab998"/> <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f4bc37ca"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="8523f8a5"/> <xilinx:checksum xilinx:scope="ports" xilinx:value="8523f8a5"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1bb46e31"/> <xilinx:checksum xilinx:scope="parameters" xilinx:value="1bb46e31"/>
</xilinx:packagingInfo> </xilinx:packagingInfo>
......
// //
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
// //
// On Thu Jul 6 13:00:48 CEST 2017 // On Fri Jul 7 10:38:49 CEST 2017
// //
// //
// Ports: // Ports:
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
// pcie_rd_arqos O 4 // pcie_rd_arqos O 4
// pcie_rd_arregion O 4 // pcie_rd_arregion O 4
// pcie_rd_aruser O 1 // pcie_rd_aruser O 1
// pcie_rd_rready O 1 // pcie_rd_rready O 1 reg
// pcie_wr_awvalid O 1 reg // pcie_wr_awvalid O 1 reg
// pcie_wr_awid O 1 // pcie_wr_awid O 1
// pcie_wr_awaddr O 64 // pcie_wr_awaddr O 64
...@@ -39,7 +39,7 @@ ...@@ -39,7 +39,7 @@
// pcie_wr_awqos O 4 // pcie_wr_awqos O 4
// pcie_wr_awregion O 4 // pcie_wr_awregion O 4
// pcie_wr_awuser O 1 // pcie_wr_awuser O 1
// pcie_wr_wvalid O 1 // pcie_wr_wvalid O 1 reg
// pcie_wr_wdata O 256 // pcie_wr_wdata O 256
// pcie_wr_wstrb O 32 // pcie_wr_wstrb O 32
// pcie_wr_wlast O 1 // pcie_wr_wlast O 1
...@@ -57,7 +57,7 @@ ...@@ -57,7 +57,7 @@
// fpga_rd_arqos O 4 // fpga_rd_arqos O 4
// fpga_rd_arregion O 4 // fpga_rd_arregion O 4
// fpga_rd_aruser O 1 // fpga_rd_aruser O 1
// fpga_rd_rready O 1 // fpga_rd_rready O 1 reg
// fpga_wr_awvalid O 1 reg // fpga_wr_awvalid O 1 reg
// fpga_wr_awid O 1 // fpga_wr_awid O 1
// fpga_wr_awaddr O 64 // fpga_wr_awaddr O 64
...@@ -70,7 +70,7 @@ ...@@ -70,7 +70,7 @@
// fpga_wr_awqos O 4 // fpga_wr_awqos O 4
// fpga_wr_awregion O 4 // fpga_wr_awregion O 4
// fpga_wr_awuser O 1 // fpga_wr_awuser O 1
// fpga_wr_wvalid O 1 // fpga_wr_wvalid O 1 reg
// fpga_wr_wdata O 512 // fpga_wr_wdata O 512
// fpga_wr_wstrb O 64 // fpga_wr_wstrb O 64
// fpga_wr_wlast O 1 // fpga_wr_wlast O 1
...@@ -96,11 +96,11 @@ ...@@ -96,11 +96,11 @@
// S_AXI_bready I 1 // S_AXI_bready I 1
// pcie_rd_arready I 1 // pcie_rd_arready I 1
// pcie_rd_rvalid I 1 // pcie_rd_rvalid I 1
// pcie_rd_rid I 1 // pcie_rd_rid I 1 reg
// pcie_rd_rdata I 256 // pcie_rd_rdata I 256 reg
// pcie_rd_rresp I 2 // pcie_rd_rresp I 2 reg
// pcie_rd_rlast I 1 // pcie_rd_rlast I 1 reg
// pcie_rd_ruser I 1 // pcie_rd_ruser I 1 reg
// pcie_wr_awready I 1 // pcie_wr_awready I 1
// pcie_wr_wready I 1 // pcie_wr_wready I 1
// pcie_wr_bvalid I 1 // pcie_wr_bvalid I 1
...@@ -109,11 +109,11 @@ ...@@ -109,11 +109,11 @@
// pcie_wr_buser I 1 reg // pcie_wr_buser I 1 reg
// fpga_rd_arready I 1 // fpga_rd_arready I 1
// fpga_rd_rvalid I 1 // fpga_rd_rvalid I 1
// fpga_rd_rid I 1 // fpga_rd_rid I 1 reg
// fpga_rd_rdata I 512 // fpga_rd_rdata I 512 reg
// fpga_rd_rresp I 2 // fpga_rd_rresp I 2 reg
// fpga_rd_rlast I 1 // fpga_rd_rlast I 1 reg
// fpga_rd_ruser I 1 // fpga_rd_ruser I 1 reg
// fpga_wr_awready I 1 // fpga_wr_awready I 1
// fpga_wr_wready I 1 // fpga_wr_wready I 1
// fpga_wr_bvalid I 1 // fpga_wr_bvalid I 1
...@@ -730,22 +730,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -730,22 +730,7 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_fpga_wr_master_wr_wawcache$wget, m_fpga_wr_master_wr_wawcache$wget,
m_pcie_rd_master_rd_warcache$wget, m_pcie_rd_master_rd_warcache$wget,
m_pcie_wr_master_wr_wawcache$wget; m_pcie_wr_master_wr_wawcache$wget;
wire [578 : 0] m_fpga_wr_master_wr_in_data_1_rv$port1__read,
m_fpga_wr_master_wr_in_data_1_rv$port1__write_1,
m_fpga_wr_master_wr_in_data_1_rv$port2__read;
wire [517 : 0] m_fpga_rd_master_rd_out_1_rv$port1__read,
m_fpga_rd_master_rd_out_1_rv$port1__write_1,
m_fpga_rd_master_rd_out_1_rv$port2__read;
wire [516 : 0] m_fpga_rd_master_rd_rinpkg$wget; wire [516 : 0] m_fpga_rd_master_rd_rinpkg$wget;
wire [512 : 0] m_fpga_rd_outgoingBuffer_rv$port1__read,
m_fpga_rd_outgoingBuffer_rv$port1__write_1,
m_fpga_rd_outgoingBuffer_rv$port2__read,
m_fpga_wr_incomingBuffer_rv$port1__read,
m_fpga_wr_incomingBuffer_rv$port1__write_1,
m_fpga_wr_incomingBuffer_rv$port2__read,
writeConverter_dataSync_rv$port1__read,
writeConverter_dataSync_rv$port1__write_1,
writeConverter_dataSync_rv$port2__read;
wire [511 : 0] byteAlignerReader_buffer$port0__write_1, wire [511 : 0] byteAlignerReader_buffer$port0__write_1,
byteAlignerReader_buffer$port1__read, byteAlignerReader_buffer$port1__read,
byteAlignerReader_buffer$port1__write_1, byteAlignerReader_buffer$port1__write_1,
...@@ -754,25 +739,7 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -754,25 +739,7 @@ module mkBlueDMA(CLK_m32_axi_aclk,
byteAlignerWriter_buffer$port1__read, byteAlignerWriter_buffer$port1__read,
byteAlignerWriter_buffer$port1__write_1, byteAlignerWriter_buffer$port1__write_1,
byteAlignerWriter_buffer$port2__read; byteAlignerWriter_buffer$port2__read;
wire [290 : 0] m_pcie_wr_master_wr_in_data_1_rv$port1__read,
m_pcie_wr_master_wr_in_data_1_rv$port1__write_1,
m_pcie_wr_master_wr_in_data_1_rv$port2__read;
wire [261 : 0] m_pcie_rd_master_rd_out_1_rv$port1__read,
m_pcie_rd_master_rd_out_1_rv$port1__write_1,
m_pcie_rd_master_rd_out_1_rv$port2__read;
wire [260 : 0] m_pcie_rd_master_rd_rinpkg$wget; wire [260 : 0] m_pcie_rd_master_rd_rinpkg$wget;
wire [256 : 0] byteAlignerReader_incoming_rv$port1__read,
byteAlignerReader_outgoing_rv$port1__write_1,
byteAlignerReader_outgoing_rv$port2__read,
byteAlignerWriter_incoming_rv$port1__read,
byteAlignerWriter_outgoing_rv$port1__write_1,
byteAlignerWriter_outgoing_rv$port2__read,
m_pcie_rd_outgoingBuffer_rv$port1__read,
m_pcie_rd_outgoingBuffer_rv$port1__write_1,
m_pcie_rd_outgoingBuffer_rv$port2__read,
m_pcie_wr_incomingBuffer_rv$port1__read,
m_pcie_wr_incomingBuffer_rv$port1__write_1,
m_pcie_wr_incomingBuffer_rv$port2__read;
wire [192 : 0] readIn_rv$port1__read, wire [192 : 0] readIn_rv$port1__read,
readIn_rv$port1__write_1, readIn_rv$port1__write_1,
readIn_rv$port2__read, readIn_rv$port2__read,
...@@ -795,23 +762,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -795,23 +762,13 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire byteAlignerReader_buffer$EN_port0__write, wire byteAlignerReader_buffer$EN_port0__write,
byteAlignerReader_bytes_left_in_buffer$EN_port0__write, byteAlignerReader_bytes_left_in_buffer$EN_port0__write,
byteAlignerReader_fetchedDatum$EN_port0__write, byteAlignerReader_fetchedDatum$EN_port0__write,
byteAlignerReader_fetchedDatum$EN_port1__write,
byteAlignerReader_fetchedDatum$port1__read, byteAlignerReader_fetchedDatum$port1__read,
byteAlignerReader_fetchedDatum$port2__read, byteAlignerReader_fetchedDatum$port2__read,
byteAlignerReader_outgoing_rv$EN_port1__write,
byteAlignerWriter_buffer$EN_port0__write, byteAlignerWriter_buffer$EN_port0__write,
byteAlignerWriter_bytes_left_in_buffer$EN_port0__write, byteAlignerWriter_bytes_left_in_buffer$EN_port0__write,
byteAlignerWriter_fetchedDatum$EN_port0__write, byteAlignerWriter_fetchedDatum$EN_port0__write,
byteAlignerWriter_fetchedDatum$EN_port1__write,
byteAlignerWriter_fetchedDatum$port1__read, byteAlignerWriter_fetchedDatum$port1__read,
byteAlignerWriter_fetchedDatum$port2__read, byteAlignerWriter_fetchedDatum$port2__read,
byteAlignerWriter_outgoing_rv$EN_port1__write,
m_fpga_rd_master_rd_out_1_rv$EN_port1__write,
m_fpga_rd_outgoingBuffer_rv$EN_port0__write,
m_fpga_wr_incomingBuffer_rv$EN_port1__write,
m_fpga_wr_master_wr_in_data_1_rv$EN_port0__write,
m_pcie_rd_master_rd_out_1_rv$EN_port1__write,
m_pcie_wr_master_wr_in_data_1_rv$EN_port0__write,
readConverter_bufferEmpty$EN_port0__write, readConverter_bufferEmpty$EN_port0__write,
readConverter_bufferEmpty$EN_port1__write, readConverter_bufferEmpty$EN_port1__write,
readConverter_bufferEmpty$port1__read, readConverter_bufferEmpty$port1__read,
...@@ -823,8 +780,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -823,8 +780,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
s_config_writeSlave_addrIn_rv$EN_port1__write, s_config_writeSlave_addrIn_rv$EN_port1__write,
s_config_writeSlave_dataIn_rv$EN_port0__write, s_config_writeSlave_dataIn_rv$EN_port0__write,
s_config_writeSlave_dataIn_rv$EN_port1__write, s_config_writeSlave_dataIn_rv$EN_port1__write,
writeConverter_dataSync_rv$EN_port0__write,
writeConverter_dataSync_rv$EN_port1__write,
writeIn_rv$EN_port1__write; writeIn_rv$EN_port1__write;
// register byteAlignerReader_buffer // register byteAlignerReader_buffer
...@@ -861,16 +816,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -861,16 +816,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
reg byteAlignerReader_fetchedDatum; reg byteAlignerReader_fetchedDatum;
wire byteAlignerReader_fetchedDatum$D_IN, byteAlignerReader_fetchedDatum$EN; wire byteAlignerReader_fetchedDatum$D_IN, byteAlignerReader_fetchedDatum$EN;
// register byteAlignerReader_incoming_rv
reg [256 : 0] byteAlignerReader_incoming_rv;
wire [256 : 0] byteAlignerReader_incoming_rv$D_IN;
wire byteAlignerReader_incoming_rv$EN;
// register byteAlignerReader_outgoing_rv
reg [256 : 0] byteAlignerReader_outgoing_rv;
wire [256 : 0] byteAlignerReader_outgoing_rv$D_IN;
wire byteAlignerReader_outgoing_rv$EN;
// register byteAlignerWriter_buffer // register byteAlignerWriter_buffer
reg [511 : 0] byteAlignerWriter_buffer; reg [511 : 0] byteAlignerWriter_buffer;
wire [511 : 0] byteAlignerWriter_buffer$D_IN; wire [511 : 0] byteAlignerWriter_buffer$D_IN;
...@@ -905,16 +850,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -905,16 +850,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
reg byteAlignerWriter_fetchedDatum; reg byteAlignerWriter_fetchedDatum;
wire byteAlignerWriter_fetchedDatum$D_IN, byteAlignerWriter_fetchedDatum$EN; wire byteAlignerWriter_fetchedDatum$D_IN, byteAlignerWriter_fetchedDatum$EN;
// register byteAlignerWriter_incoming_rv
reg [256 : 0] byteAlignerWriter_incoming_rv;
wire [256 : 0] byteAlignerWriter_incoming_rv$D_IN;
wire byteAlignerWriter_incoming_rv$EN;
// register byteAlignerWriter_outgoing_rv
reg [256 : 0] byteAlignerWriter_outgoing_rv;
wire [256 : 0] byteAlignerWriter_outgoing_rv$D_IN;
wire byteAlignerWriter_outgoing_rv$EN;
// register doneInterruptReg // register doneInterruptReg
reg doneInterruptReg; reg doneInterruptReg;
wire doneInterruptReg$D_IN, doneInterruptReg$EN; wire doneInterruptReg$D_IN, doneInterruptReg$EN;
...@@ -958,16 +893,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -958,16 +893,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [31 : 0] m_fpga_rd_lastPut$D_IN; wire [31 : 0] m_fpga_rd_lastPut$D_IN;
wire m_fpga_rd_lastPut$EN; wire m_fpga_rd_lastPut$EN;
// register m_fpga_rd_master_rd_out_1_rv
reg [517 : 0] m_fpga_rd_master_rd_out_1_rv;
wire [517 : 0] m_fpga_rd_master_rd_out_1_rv$D_IN;
wire m_fpga_rd_master_rd_out_1_rv$EN;
// register m_fpga_rd_outgoingBuffer_rv
reg [512 : 0] m_fpga_rd_outgoingBuffer_rv;
wire [512 : 0] m_fpga_rd_outgoingBuffer_rv$D_IN;
wire m_fpga_rd_outgoingBuffer_rv$EN;
// register m_fpga_rd_putDelay // register m_fpga_rd_putDelay
reg [31 : 0] m_fpga_rd_putDelay; reg [31 : 0] m_fpga_rd_putDelay;
wire [31 : 0] m_fpga_rd_putDelay$D_IN; wire [31 : 0] m_fpga_rd_putDelay$D_IN;
...@@ -998,21 +923,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -998,21 +923,11 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [31 : 0] m_fpga_wr_clkCntr$D_IN; wire [31 : 0] m_fpga_wr_clkCntr$D_IN;
wire m_fpga_wr_clkCntr$EN; wire m_fpga_wr_clkCntr$EN;
// register m_fpga_wr_incomingBuffer_rv
reg [512 : 0] m_fpga_wr_incomingBuffer_rv;
wire [512 : 0] m_fpga_wr_incomingBuffer_rv$D_IN;
wire m_fpga_wr_incomingBuffer_rv$EN;
// register m_fpga_wr_lastPut // register m_fpga_wr_lastPut
reg [31 : 0] m_fpga_wr_lastPut; reg [31 : 0] m_fpga_wr_lastPut;
wire [31 : 0] m_fpga_wr_lastPut$D_IN; wire [31 : 0] m_fpga_wr_lastPut$D_IN;
wire m_fpga_wr_lastPut$EN; wire m_fpga_wr_lastPut$EN;
// register m_fpga_wr_master_wr_in_data_1_rv
reg [578 : 0] m_fpga_wr_master_wr_in_data_1_rv;
wire [578 : 0] m_fpga_wr_master_wr_in_data_1_rv$D_IN;
wire m_fpga_wr_master_wr_in_data_1_rv$EN;
// register m_fpga_wr_putDelay // register m_fpga_wr_putDelay
reg [31 : 0] m_fpga_wr_putDelay; reg [31 : 0] m_fpga_wr_putDelay;
wire [31 : 0] m_fpga_wr_putDelay$D_IN; wire [31 : 0] m_fpga_wr_putDelay$D_IN;
...@@ -1043,16 +958,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -1043,16 +958,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [31 : 0] m_pcie_rd_lastPut$D_IN; wire [31 : 0] m_pcie_rd_lastPut$D_IN;
wire m_pcie_rd_lastPut$EN; wire m_pcie_rd_lastPut$EN;
// register m_pcie_rd_master_rd_out_1_rv
reg [261 : 0] m_pcie_rd_master_rd_out_1_rv;
wire [261 : 0] m_pcie_rd_master_rd_out_1_rv$D_IN;
wire m_pcie_rd_master_rd_out_1_rv$EN;
// register m_pcie_rd_outgoingBuffer_rv
reg [256 : 0] m_pcie_rd_outgoingBuffer_rv;
wire [256 : 0] m_pcie_rd_outgoingBuffer_rv$D_IN;
wire m_pcie_rd_outgoingBuffer_rv$EN;
// register m_pcie_rd_putDelay // register m_pcie_rd_putDelay
reg [31 : 0] m_pcie_rd_putDelay; reg [31 : 0] m_pcie_rd_putDelay;
wire [31 : 0] m_pcie_rd_putDelay$D_IN; wire [31 : 0] m_pcie_rd_putDelay$D_IN;
...@@ -1083,21 +988,11 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -1083,21 +988,11 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [31 : 0] m_pcie_wr_clkCntr$D_IN; wire [31 : 0] m_pcie_wr_clkCntr$D_IN;
wire m_pcie_wr_clkCntr$EN; wire m_pcie_wr_clkCntr$EN;
// register m_pcie_wr_incomingBuffer_rv
reg [256 : 0] m_pcie_wr_incomingBuffer_rv;
wire [256 : 0] m_pcie_wr_incomingBuffer_rv$D_IN;
wire m_pcie_wr_incomingBuffer_rv$EN;
// register m_pcie_wr_lastPut // register m_pcie_wr_lastPut
reg [31 : 0] m_pcie_wr_lastPut; reg [31 : 0] m_pcie_wr_lastPut;
wire [31 : 0] m_pcie_wr_lastPut$D_IN; wire [31 : 0] m_pcie_wr_lastPut$D_IN;
wire m_pcie_wr_lastPut$EN; wire m_pcie_wr_lastPut$EN;
// register m_pcie_wr_master_wr_in_data_1_rv
reg [290 : 0] m_pcie_wr_master_wr_in_data_1_rv;
wire [290 : 0] m_pcie_wr_master_wr_in_data_1_rv$D_IN;
wire m_pcie_wr_master_wr_in_data_1_rv$EN;
// register m_pcie_wr_putDelay // register m_pcie_wr_putDelay
reg [31 : 0] m_pcie_wr_putDelay; reg [31 : 0] m_pcie_wr_putDelay;
wire [31 : 0] m_pcie_wr_putDelay$D_IN; wire [31 : 0] m_pcie_wr_putDelay$D_IN;
...@@ -1188,11 +1083,6 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -1188,11 +1083,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [63 : 0] writeConverter_byteCntr$D_IN; wire [63 : 0] writeConverter_byteCntr$D_IN;
wire writeConverter_byteCntr$EN; wire writeConverter_byteCntr$EN;
// register writeConverter_dataSync_rv
reg [512 : 0] writeConverter_dataSync_rv;
wire [512 : 0] writeConverter_dataSync_rv$D_IN;
wire writeConverter_dataSync_rv$EN;
// register writeConverter_wordInCntr // register writeConverter_wordInCntr
reg [1 : 0] writeConverter_wordInCntr; reg [1 : 0] writeConverter_wordInCntr;
wire [1 : 0] writeConverter_wordInCntr$D_IN; wire [1 : 0] writeConverter_wordInCntr$D_IN;
...@@ -1220,6 +1110,21 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -1220,6 +1110,21 @@ module mkBlueDMA(CLK_m32_axi_aclk,
byteAlignerReader_addr_ff$dEMPTY_N, byteAlignerReader_addr_ff$dEMPTY_N,
byteAlignerReader_addr_ff$sENQ; byteAlignerReader_addr_ff$sENQ;
// ports of submodule byteAlignerReader_incoming
wire [255 : 0] byteAlignerReader_incoming$D_IN,
byteAlignerReader_incoming$D_OUT;
wire byteAlignerReader_incoming$CLR,
byteAlignerReader_incoming$DEQ,
byteAlignerReader_incoming$EMPTY_N,
byteAlignerReader_incoming$ENQ;
// ports of submodule byteAlignerReader_outgoing
wire [255 : 0] byteAlignerReader_outgoing$D_IN;
wire byteAlignerReader_outgoing$CLR,
byteAlignerReader_outgoing$DEQ,
byteAlignerReader_outgoing$ENQ,
byteAlignerReader_outgoing$FULL_N;
// ports of submodule byteAlignerWriter_addr_ff // ports of submodule byteAlignerWriter_addr_ff
wire [191 : 0] byteAlignerWriter_addr_ff$dD_OUT, wire [191 : 0] byteAlignerWriter_addr_ff$dD_OUT,
byteAlignerWriter_addr_ff$sD_IN; byteAlignerWriter_addr_ff$sD_IN;
...@@ -1227,6 +1132,21 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -1227,6 +1132,21 @@ module mkBlueDMA(CLK_m32_axi_aclk,
byteAlignerWriter_addr_ff$dEMPTY_N, byteAlignerWriter_addr_ff$dEMPTY_N,
byteAlignerWriter_addr_ff$sENQ; byteAlignerWriter_addr_ff$sENQ;
// ports of submodule byteAlignerWriter_incoming
wire [255 : 0] byteAlignerWriter_incoming$D_IN,
byteAlignerWriter_incoming$D_OUT;
wire byteAlignerWriter_incoming$CLR,
byteAlignerWriter_incoming$DEQ,
byteAlignerWriter_incoming$EMPTY_N,
byteAlignerWriter_incoming$ENQ;
// ports of submodule byteAlignerWriter_outgoing
wire [255 : 0] byteAlignerWriter_outgoing$D_IN;
wire byteAlignerWriter_outgoing$CLR,
byteAlignerWriter_outgoing$DEQ,
byteAlignerWriter_outgoing$ENQ,
byteAlignerWriter_outgoing$FULL_N;
// ports of submodule cmdsIn // ports of submodule cmdsIn
wire cmdsIn$CLR, wire cmdsIn$CLR,
cmdsIn$DEQ, cmdsIn$DEQ,
...@@ -1287,10 +1207,21 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -1287,10 +1207,21 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_fpga_rd_master_rd_in$FULL_N; m_fpga_rd_master_rd_in$FULL_N;
// ports of submodule m_fpga_rd_master_rd_out // ports of submodule m_fpga_rd_master_rd_out
wire [516 : 0] m_fpga_rd_master_rd_out$D_IN; wire [516 : 0] m_fpga_rd_master_rd_out$D_IN, m_fpga_rd_master_rd_out$D_OUT;
wire m_fpga_rd_master_rd_out$CLR, wire m_fpga_rd_master_rd_out$CLR,
m_fpga_rd_master_rd_out$DEQ, m_fpga_rd_master_rd_out$DEQ,
m_fpga_rd_master_rd_out$ENQ; m_fpga_rd_master_rd_out$EMPTY_N,
m_fpga_rd_master_rd_out$ENQ,
m_fpga_rd_master_rd_out$FULL_N;
// ports of submodule m_fpga_rd_outgoingBuffer
wire [511 : 0] m_fpga_rd_outgoingBuffer$D_IN,
m_fpga_rd_outgoingBuffer$D_OUT;
wire m_fpga_rd_outgoingBuffer$CLR,
m_fpga_rd_outgoingBuffer$DEQ,
m_fpga_rd_outgoingBuffer$EMPTY_N,
m_fpga_rd_outgoingBuffer$ENQ,
m_fpga_rd_outgoingBuffer$FULL_N;
// ports of submodule m_fpga_rd_reqGen_incomingBuffer // ports of submodule m_fpga_rd_reqGen_incomingBuffer
wire [131 : 0] m_fpga_rd_reqGen_incomingBuffer$D_IN, wire [131 : 0] m_fpga_rd_reqGen_incomingBuffer$D_IN,
...@@ -1337,6 +1268,15 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -1337,6 +1268,15 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_fpga_wr_beatsPerRequestFIFO$ENQ, m_fpga_wr_beatsPerRequestFIFO$ENQ,
m_fpga_wr_beatsPerRequestFIFO$FULL_N; m_fpga_wr_beatsPerRequestFIFO$FULL_N;
// ports of submodule m_fpga_wr_incomingBuffer
wire [511 : 0] m_fpga_wr_incomingBuffer$D_IN,
m_fpga_wr_incomingBuffer$D_OUT;
wire m_fpga_wr_incomingBuffer$CLR,
m_fpga_wr_incomingBuffer$DEQ,
m_fpga_wr_incomingBuffer$EMPTY_N,
m_fpga_wr_incomingBuffer$ENQ,
m_fpga_wr_incomingBuffer$FULL_N;
// ports of submodule m_fpga_wr_master_wr_in_addr // ports of submodule m_fpga_wr_master_wr_in_addr
wire [94 : 0] m_fpga_wr_master_wr_in_addr$D_IN, wire [94 : 0] m_fpga_wr_master_wr_in_addr$D_IN,
m_fpga_wr_master_wr_in_addr$D_OUT; m_fpga_wr_master_wr_in_addr$D_OUT;
...@@ -1347,10 +1287,13 @@ module mkBlueDMA(CLK_m32_axi_aclk, ...@@ -1347,10 +1287,13 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_fpga_wr_master_wr_in_addr$FULL_N; m_fpga_wr_master_wr_in_addr$FULL_N;
// ports of submodule m_fpga_wr_master_wr_in_data // ports of submodule m_fpga_wr_master_wr_in_data
wire [577 : 0] m_fpga_wr_master_wr_in_data$D_IN; wire [577 : 0] m_fpga_wr_master_wr_in_data$D_IN,
m_fpga_wr_master_wr_in_data$D_OUT;
wire m_fpga_wr_master_wr_in_data$CLR, wire m_fpga_wr_master_wr_in_data$CLR,
m_fpga_wr_master_wr_in_data$DEQ, m_fpga_wr_master_wr_in_data$DEQ,
m_fpga_wr_master_wr_in_data$ENQ; m_fpga_wr_master_wr_in_data$EMPTY_N,
m_fpga_wr_master_wr_in_data$ENQ,
m_fpga_wr_master_wr_in_data$FULL_N;