Commit 0608e988 authored by Jaco Hofmann's avatar Jaco Hofmann

Adds newest BlueDMA version

    - PCIE Burst Length 64
    - FPGA Burst Length 256
    - Alignment 32 Bytes
    - Fixes SUPPORTS_NARROW_BURST parameters
    - Adds NUM_READ_OUTSTANDING and NUM_WRITE_OUTSTANDING to help
    interconnects decide on the DMA features
parent 2785e65e
...@@ -528,6 +528,20 @@ ...@@ -528,6 +528,20 @@
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
</spirit:portMaps> </spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>m64_axi</spirit:name> <spirit:name>m64_axi</spirit:name>
...@@ -890,6 +904,20 @@ ...@@ -890,6 +904,20 @@
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
</spirit:portMaps> </spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>s_axi_aresetn</spirit:name> <spirit:name>s_axi_aresetn</spirit:name>
...@@ -1096,7 +1124,7 @@ ...@@ -1096,7 +1124,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>ded3be7f</spirit:value> <spirit:value>6dca3063</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -1112,7 +1140,7 @@ ...@@ -1112,7 +1140,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>ded3be7f</spirit:value> <spirit:value>6dca3063</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -2983,7 +3011,7 @@ ...@@ -2983,7 +3011,7 @@
<spirit:file> <spirit:file>
<spirit:name>src/mkBlueDMAVivado.v</spirit:name> <spirit:name>src/mkBlueDMAVivado.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType> <spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_578878b6</spirit:userFileType> <spirit:userFileType>CHECKSUM_031e6e27</spirit:userFileType>
</spirit:file> </spirit:file>
</spirit:fileSet> </spirit:fileSet>
<spirit:fileSet> <spirit:fileSet>
...@@ -3055,17 +3083,17 @@ ...@@ -3055,17 +3083,17 @@
<xilinx:displayName>BlueDMA</xilinx:displayName> <xilinx:displayName>BlueDMA</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource> <xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision> <xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-06T11:01:37Z</xilinx:coreCreationDateTime> <xilinx:coreCreationDateTime>2017-07-07T08:39:29Z</xilinx:coreCreationDateTime>
<xilinx:tags> <xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/> <xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags> </xilinx:tags>
</xilinx:coreExtensions> </xilinx:coreExtensions>
<xilinx:packagingInfo> <xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion> <xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="4abcc88b"/> <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9aa6aa20"/>
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/> <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/> <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d8fab998"/> <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f4bc37ca"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="8523f8a5"/> <xilinx:checksum xilinx:scope="ports" xilinx:value="8523f8a5"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1bb46e31"/> <xilinx:checksum xilinx:scope="parameters" xilinx:value="1bb46e31"/>
</xilinx:packagingInfo> </xilinx:packagingInfo>
......
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// //
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
// //
// On Thu Jul 6 13:00:49 CEST 2017 // On Fri Jul 7 10:38:51 CEST 2017
// //
// //
// Ports: // Ports:
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
// m64_axi_arqos O 4 // m64_axi_arqos O 4
// m64_axi_arregion O 4 // m64_axi_arregion O 4
// m64_axi_aruser O 1 // m64_axi_aruser O 1
// m64_axi_rready O 1 // m64_axi_rready O 1 reg
// m64_axi_awvalid O 1 reg // m64_axi_awvalid O 1 reg
// m64_axi_awid O 1 // m64_axi_awid O 1
// m64_axi_awaddr O 64 // m64_axi_awaddr O 64
...@@ -39,7 +39,7 @@ ...@@ -39,7 +39,7 @@
// m64_axi_awqos O 4 // m64_axi_awqos O 4
// m64_axi_awregion O 4 // m64_axi_awregion O 4
// m64_axi_awuser O 1 // m64_axi_awuser O 1
// m64_axi_wvalid O 1 // m64_axi_wvalid O 1 reg
// m64_axi_wdata O 256 // m64_axi_wdata O 256
// m64_axi_wstrb O 32 // m64_axi_wstrb O 32
// m64_axi_wlast O 1 // m64_axi_wlast O 1
...@@ -57,7 +57,7 @@ ...@@ -57,7 +57,7 @@
// m32_axi_arqos O 4 // m32_axi_arqos O 4
// m32_axi_arregion O 4 // m32_axi_arregion O 4
// m32_axi_aruser O 1 // m32_axi_aruser O 1
// m32_axi_rready O 1 // m32_axi_rready O 1 reg
// m32_axi_awvalid O 1 reg // m32_axi_awvalid O 1 reg
// m32_axi_awid O 1 // m32_axi_awid O 1
// m32_axi_awaddr O 64 // m32_axi_awaddr O 64
...@@ -70,7 +70,7 @@ ...@@ -70,7 +70,7 @@
// m32_axi_awqos O 4 // m32_axi_awqos O 4
// m32_axi_awregion O 4 // m32_axi_awregion O 4
// m32_axi_awuser O 1 // m32_axi_awuser O 1
// m32_axi_wvalid O 1 // m32_axi_wvalid O 1 reg
// m32_axi_wdata O 512 // m32_axi_wdata O 512
// m32_axi_wstrb O 64 // m32_axi_wstrb O 64
// m32_axi_wlast O 1 // m32_axi_wlast O 1
...@@ -96,11 +96,11 @@ ...@@ -96,11 +96,11 @@
// S_AXI_bready I 1 // S_AXI_bready I 1
// m64_axi_arready I 1 // m64_axi_arready I 1
// m64_axi_rvalid I 1 // m64_axi_rvalid I 1
// m64_axi_rid I 1 // m64_axi_rid I 1 reg
// m64_axi_rdata I 256 // m64_axi_rdata I 256 reg
// m64_axi_rresp I 2 // m64_axi_rresp I 2 reg
// m64_axi_rlast I 1 // m64_axi_rlast I 1 reg
// m64_axi_ruser I 1 // m64_axi_ruser I 1 reg
// m64_axi_awready I 1 // m64_axi_awready I 1
// m64_axi_wready I 1 // m64_axi_wready I 1
// m64_axi_bvalid I 1 // m64_axi_bvalid I 1
...@@ -109,11 +109,11 @@ ...@@ -109,11 +109,11 @@
// m64_axi_buser I 1 reg // m64_axi_buser I 1 reg
// m32_axi_arready I 1 // m32_axi_arready I 1
// m32_axi_rvalid I 1 // m32_axi_rvalid I 1
// m32_axi_rid I 1 // m32_axi_rid I 1 reg
// m32_axi_rdata I 512 // m32_axi_rdata I 512 reg
// m32_axi_rresp I 2 // m32_axi_rresp I 2 reg
// m32_axi_rlast I 1 // m32_axi_rlast I 1 reg
// m32_axi_ruser I 1 // m32_axi_ruser I 1 reg
// m32_axi_awready I 1 // m32_axi_awready I 1
// m32_axi_wready I 1 // m32_axi_wready I 1
// m32_axi_bvalid I 1 // m32_axi_bvalid I 1
......
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