Commit 095f9417 authored by Jens Korinth's avatar Jens Korinth
Browse files

Remove clock pinning and time limit for opt 42

parent 061d43bb
Pipeline #284 failed with stage
in 3 minutes and 35 seconds
......@@ -104,7 +104,6 @@ if {@@OPTIMIZATION@@ == 42} {
set clock_ports [get_ports -filter {DIRECTION == IN && (NAME =~ *clk* || NAME =~ *CLK* || NAME =~ clock)}]
puts "clock_ports = $clock_ports"
create_clock -name clk -period $period $clock_ports
set_property HD.CLK_SRC BUFGCTRL_X0Y0 $clock_ports
set pnr_start [clock seconds]
# place and route
......
......@@ -147,7 +147,7 @@ object EvaluateIP {
// execute Vivado (max runtime: 1d)
val r = InterruptibleProcess(Process(vivadoCmd, files.baseDir.toFile),
waitMillis = Some(24 * 60 * 60 * 1000)).!(io)
waitMillis = Some((if (optimization == 42) 14 else 1) * 24 * 60 * 60 * 1000)).!(io)
if (r == InterruptibleProcess.TIMEOUT_RETCODE) {
logger.error("%s: Vivado timeout error".format(runPrefix))
......
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