Commit 09a55e7e authored by Carsten Heinz's avatar Carsten Heinz
Browse files

Add support for prodesign HAWK versal board

parent da6b13be
# Copyright (c) 2014-2022 Embedded Systems and Applications, TU Darmstadt.
#
# This file is part of TaPaSCo
# (see https://github.com/esa-tu-darmstadt/tapasco).
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
namespace eval platform {
set platform_dirname "HAWK"
source $::env(TAPASCO_HOME_TCL)/platform/versal/versal_base.tcl
# give configuration for NoC MCs
proc get_number_mc {} {
return 4
}
proc get_mc_config {} {
return [list CONFIG.CONTROLLERTYPE {DDR4_SDRAM} \
CONFIG.MC0_CONFIG_NUM {config17} \
CONFIG.MC1_CONFIG_NUM {config17} \
CONFIG.MC2_CONFIG_NUM {config17} \
CONFIG.MC3_CONFIG_NUM {config17} \
CONFIG.MC_CASLATENCY {15} \
CONFIG.MC_CASWRITELATENCY {11} \
CONFIG.MC_CA_MIRROR {true} \
CONFIG.MC_CHAN_REGION0 {DDR_LOW3} \
CONFIG.MC_CHAN_REGION1 {DDR_LOW3} \
CONFIG.MC_COMPONENT_DENSITY {16Gb} \
CONFIG.MC_CONFIG_NUM {config17} \
CONFIG.MC_CS_WIDTH {2} \
CONFIG.MC_DDR4_2T {Disable} \
CONFIG.MC_DDR_INIT_TIMEOUT {0x002E3BF0} \
CONFIG.MC_ECC_SCRUB_PERIOD {0x002710} \
CONFIG.MC_ECC_SCRUB_SIZE {32768} \
CONFIG.MC_F1_CASLATENCY {22} \
CONFIG.MC_F1_LPDDR4_MR1 {0x0000} \
CONFIG.MC_F1_LPDDR4_MR2 {0x0000} \
CONFIG.MC_F1_LPDDR4_MR3 {0x0000} \
CONFIG.MC_F1_LPDDR4_MR13 {0x0000} \
CONFIG.MC_F1_TRCD {12960} \
CONFIG.MC_F1_TRCDMIN {12960} \
CONFIG.MC_INPUTCLK0_PERIOD {10000} \
CONFIG.MC_INPUT_FREQUENCY0 {100.000} \
CONFIG.MC_MEMORY_DENSITY {32GB} \
CONFIG.MC_MEMORY_DEVICETYPE {SODIMMs} \
CONFIG.MC_MEMORY_DEVICE_DENSITY {16Gb} \
CONFIG.MC_MEMORY_SPEEDGRADE {DDR4-2933V(19-19-19)} \
CONFIG.MC_MEMORY_TIMEPERIOD0 {1000} \
CONFIG.MC_MEMORY_TIMEPERIOD1 {690} \
CONFIG.MC_RANK {2} \
CONFIG.MC_ROWADDRESSWIDTH {17} \
CONFIG.MC_TCCD_L {5} \
CONFIG.MC_TCKE {5} \
CONFIG.MC_TCKEMIN {5} \
CONFIG.MC_TPAR_ALERT_ON {6} \
CONFIG.MC_TPAR_ALERT_PW_MAX {128} \
CONFIG.MC_TRC {44960} \
CONFIG.MC_TRCD {12960} \
CONFIG.MC_TRFC {550000} \
CONFIG.MC_TRFCMIN {550000} \
CONFIG.MC_TRP {12960} \
CONFIG.MC_TRPMIN {12960} \
CONFIG.MC_TRRD_L {5} \
CONFIG.MC_TRTP_nCK {8} \
CONFIG.MC_TXP {6} \
CONFIG.MC_TXPMIN {6} \
CONFIG.MC_TXPR {560} \
CONFIG.MC_USER_DEFINED_ADDRESS_MAP {1CS-17RA-2BA-2BG-10CA} \
CONFIG.MC_XPLL_CLKOUT1_PERIOD {2000} \
CONFIG.MC_XPLL_DIV4_CLKOUT12 {FALSE}]
}
# give PCIe configuration
# TODO
proc add_constraints {args} {
set constraints_fn "$::env(TAPASCO_HOME_TCL)/platform/HAWK/hawk.xdc"
read_xdc $constraints_fn
set_property PROCESSING_ORDER EARLY [get_files $constraints_fn]
return $args
}
tapasco::register_plugin "platform::add_constraints" "post-platform"
}
# constrain clock inputs
create_clock -period 10.000 -name sys_clk [get_ports pcie_refclk_clk_p]
set_property IOSTANDARD LVCMOS18 [get_ports sys_reset]
set_property PACKAGE_PIN K35 [get_ports sys_reset]
set_property PULLUP true [get_ports sys_reset]
set_property PACKAGE_PIN AB46 [get_ports {pcie_mgt_grx_p[0]}]
set_property PACKAGE_PIN AB47 [get_ports {pcie_mgt_grx_n[0]}]
set_property PACKAGE_PIN AB41 [get_ports {pcie_mgt_gtx_p[0]}]
set_property PACKAGE_PIN AB42 [get_ports {pcie_mgt_gtx_n[0]}]
set_property PACKAGE_PIN AA44 [get_ports {pcie_mgt_grx_p[1]}]
set_property PACKAGE_PIN AA45 [get_ports {pcie_mgt_grx_n[1]}]
set_property PACKAGE_PIN Y41 [get_ports {pcie_mgt_gtx_p[1]}]
set_property PACKAGE_PIN Y42 [get_ports {pcie_mgt_gtx_n[1]}]
set_property PACKAGE_PIN Y46 [get_ports {pcie_mgt_grx_p[2]}]
set_property PACKAGE_PIN Y47 [get_ports {pcie_mgt_grx_n[2]}]
set_property PACKAGE_PIN V41 [get_ports {pcie_mgt_gtx_p[2]}]
set_property PACKAGE_PIN V42 [get_ports {pcie_mgt_gtx_n[2]}]
set_property PACKAGE_PIN W44 [get_ports {pcie_mgt_grx_p[3]}]
set_property PACKAGE_PIN W45 [get_ports {pcie_mgt_grx_n[3]}]
set_property PACKAGE_PIN U43 [get_ports {pcie_mgt_gtx_p[3]}]
set_property PACKAGE_PIN U44 [get_ports {pcie_mgt_gtx_n[3]}]
set_property PACKAGE_PIN V46 [get_ports {pcie_mgt_grx_p[4]}]
set_property PACKAGE_PIN V47 [get_ports {pcie_mgt_grx_n[4]}]
set_property PACKAGE_PIN T41 [get_ports {pcie_mgt_gtx_p[4]}]
set_property PACKAGE_PIN T42 [get_ports {pcie_mgt_gtx_n[4]}]
set_property PACKAGE_PIN T46 [get_ports {pcie_mgt_grx_p[5]}]
set_property PACKAGE_PIN T47 [get_ports {pcie_mgt_grx_n[5]}]
set_property PACKAGE_PIN R43 [get_ports {pcie_mgt_gtx_p[5]}]
set_property PACKAGE_PIN R44 [get_ports {pcie_mgt_gtx_n[5]}]
set_property PACKAGE_PIN P46 [get_ports {pcie_mgt_grx_p[6]}]
set_property PACKAGE_PIN P47 [get_ports {pcie_mgt_grx_n[6]}]
set_property PACKAGE_PIN P41 [get_ports {pcie_mgt_gtx_p[6]}]
set_property PACKAGE_PIN P42 [get_ports {pcie_mgt_gtx_n[6]}]
set_property PACKAGE_PIN N44 [get_ports {pcie_mgt_grx_p[7]}]
set_property PACKAGE_PIN N45 [get_ports {pcie_mgt_grx_n[7]}]
set_property PACKAGE_PIN M41 [get_ports {pcie_mgt_gtx_p[7]}]
set_property PACKAGE_PIN M42 [get_ports {pcie_mgt_gtx_n[7]}]
set_property PACKAGE_PIN M46 [get_ports {pcie_mgt_grx_p[8]}]
set_property PACKAGE_PIN M47 [get_ports {pcie_mgt_grx_n[8]}]
set_property PACKAGE_PIN K41 [get_ports {pcie_mgt_gtx_p[8]}]
set_property PACKAGE_PIN K42 [get_ports {pcie_mgt_gtx_n[8]}]
set_property PACKAGE_PIN L44 [get_ports {pcie_mgt_grx_p[9]}]
set_property PACKAGE_PIN L45 [get_ports {pcie_mgt_grx_n[9]}]
set_property PACKAGE_PIN J43 [get_ports {pcie_mgt_gtx_p[9]}]
set_property PACKAGE_PIN J44 [get_ports {pcie_mgt_gtx_n[9]}]
set_property PACKAGE_PIN K46 [get_ports {pcie_mgt_grx_p[10]}]
set_property PACKAGE_PIN K47 [get_ports {pcie_mgt_grx_n[10]}]
set_property PACKAGE_PIN H41 [get_ports {pcie_mgt_gtx_p[10]}]
set_property PACKAGE_PIN H42 [get_ports {pcie_mgt_gtx_n[10]}]
set_property PACKAGE_PIN H46 [get_ports {pcie_mgt_grx_p[11]}]
set_property PACKAGE_PIN H47 [get_ports {pcie_mgt_grx_n[11]}]
set_property PACKAGE_PIN G43 [get_ports {pcie_mgt_gtx_p[11]}]
set_property PACKAGE_PIN G44 [get_ports {pcie_mgt_gtx_n[11]}]
set_property PACKAGE_PIN F46 [get_ports {pcie_mgt_grx_p[12]}]
set_property PACKAGE_PIN F47 [get_ports {pcie_mgt_grx_n[12]}]
set_property PACKAGE_PIN F41 [get_ports {pcie_mgt_gtx_p[12]}]
set_property PACKAGE_PIN F42 [get_ports {pcie_mgt_gtx_n[12]}]
set_property PACKAGE_PIN E44 [get_ports {pcie_mgt_grx_p[13]}]
set_property PACKAGE_PIN E45 [get_ports {pcie_mgt_grx_n[13]}]
set_property PACKAGE_PIN D41 [get_ports {pcie_mgt_gtx_p[13]}]
set_property PACKAGE_PIN D42 [get_ports {pcie_mgt_gtx_n[13]}]
set_property PACKAGE_PIN D46 [get_ports {pcie_mgt_grx_p[14]}]
set_property PACKAGE_PIN D47 [get_ports {pcie_mgt_grx_n[14]}]
set_property PACKAGE_PIN B41 [get_ports {pcie_mgt_gtx_p[14]}]
set_property PACKAGE_PIN B42 [get_ports {pcie_mgt_gtx_n[14]}]
set_property PACKAGE_PIN C44 [get_ports {pcie_mgt_grx_p[15]}]
set_property PACKAGE_PIN C45 [get_ports {pcie_mgt_grx_n[15]}]
set_property PACKAGE_PIN A43 [get_ports {pcie_mgt_gtx_p[15]}]
set_property PACKAGE_PIN A44 [get_ports {pcie_mgt_gtx_n[15]}]
set_property PACKAGE_PIN L39 [get_ports {pcie_refclk_clk_p[0]}]
set_property PACKAGE_PIN L40 [get_ports {pcie_refclk_clk_n[0]}]
#set_property PACKAGE_PIN N39 [get_ports sys_clk_p]
#set_property PACKAGE_PIN N40 [get_ports sys_clk_n]
#set_property PACKAGE_PIN E39 [get_ports sys_clk_p]
#set_property PACKAGE_PIN E40 [get_ports sys_clk_n]
########################################################################
# Make sure that tool gets the correct DIV value for pipe_clock
# during synthesis as these DIV pins are dynamic.
########################################################################
# PHY CLOCK FREQUENCY
########################################################################
# Set Divide By 2
set_case_analysis 1 [get_pins -filter {REF_PIN_NAME=~DIV[0]} -of_objects [get_cells -hierarchical bufg_gt_pclk]]
set_case_analysis 0 [get_pins -filter {REF_PIN_NAME=~DIV[1]} -of_objects [get_cells -hierarchical bufg_gt_pclk]]
set_case_analysis 0 [get_pins -filter {REF_PIN_NAME=~DIV[2]} -of_objects [get_cells -hierarchical bufg_gt_pclk]]
#
########################################################################
# PHY CORE CLOCK should be same as GT QUAD's TXOUTCLK
########################################################################
set_case_analysis 0 [get_pins -filter {REF_PIN_NAME=~DIV[0]} -of_objects [get_cells -hierarchical bufg_gt_coreclk]]
set_case_analysis 0 [get_pins -filter {REF_PIN_NAME=~DIV[1]} -of_objects [get_cells -hierarchical bufg_gt_coreclk]]
set_case_analysis 0 [get_pins -filter {REF_PIN_NAME=~DIV[2]} -of_objects [get_cells -hierarchical bufg_gt_coreclk]]
########################################################################
#
########################################################################
# PHY USER CLOCK FREQUENCY
########################################################################
set_case_analysis 1 [get_pins -filter {REF_PIN_NAME=~DIV[0]} -of_objects [get_cells -hierarchical bufg_gt_userclk]]
set_case_analysis 0 [get_pins -filter {REF_PIN_NAME=~DIV[1]} -of_objects [get_cells -hierarchical bufg_gt_userclk]]
set_case_analysis 0 [get_pins -filter {REF_PIN_NAME=~DIV[2]} -of_objects [get_cells -hierarchical bufg_gt_userclk]]
##########################################################################################################################
set_multicycle_path -setup -through [get_pins -hierarchical -filter {NAME =~ *phy_pipeline/pcie_ltssm_state_chain/with_ff_chain.ff_chain_gen[0].sync_rst.ff_chain_reg[1][*]/Q}] 2
set_multicycle_path -hold -through [get_pins -hierarchical -filter {NAME =~ *phy_pipeline/pcie_ltssm_state_chain/with_ff_chain.ff_chain_gen[0].sync_rst.ff_chain_reg[1][*]/Q}] 1
##########################################################################################################################
## DDR
#The following constraints were created by using version 0.15 of the schematic.
# define i/o standards
set_property IOSTANDARD LVDS15 [get_ports sys_clk*_0_clk_* ]
set_property IOSTANDARD LVCMOS12 [get_ports {CH0_DDR4_*_0_reset_n}]
## SO-DIMM 1
set_property PACKAGE_PIN AL46 [get_ports CH0_DDR4_0_0_adr[0]]
set_property PACKAGE_PIN AU44 [get_ports CH0_DDR4_0_0_adr[1]]
set_property PACKAGE_PIN AL42 [get_ports CH0_DDR4_0_0_adr[10]]
set_property PACKAGE_PIN AK38 [get_ports CH0_DDR4_0_0_adr[11]]
set_property PACKAGE_PIN AN42 [get_ports CH0_DDR4_0_0_adr[12]]
set_property PACKAGE_PIN AU45 [get_ports CH0_DDR4_0_0_adr[13]]
set_property PACKAGE_PIN AK39 [get_ports CH0_DDR4_0_0_adr[14]]
set_property PACKAGE_PIN AK40 [get_ports CH0_DDR4_0_0_adr[15]]
set_property PACKAGE_PIN AL44 [get_ports CH0_DDR4_0_0_adr[16]]
set_property PACKAGE_PIN AR44 [get_ports CH0_DDR4_0_0_adr[2]]
set_property PACKAGE_PIN AM41 [get_ports CH0_DDR4_0_0_adr[3]]
set_property PACKAGE_PIN AL41 [get_ports CH0_DDR4_0_0_adr[4]]
set_property PACKAGE_PIN AL37 [get_ports CH0_DDR4_0_0_adr[5]]
set_property PACKAGE_PIN AM38 [get_ports CH0_DDR4_0_0_adr[6]]
set_property PACKAGE_PIN AP43 [get_ports CH0_DDR4_0_0_adr[7]]
set_property PACKAGE_PIN AN47 [get_ports CH0_DDR4_0_0_adr[8]]
set_property PACKAGE_PIN AT44 [get_ports CH0_DDR4_0_0_adr[9]]
set_property PACKAGE_PIN AR47 [get_ports CH0_DDR4_0_0_act_n]
set_property PACKAGE_PIN AD43 [get_ports CH0_DDR4_0_0_alert_n]
set_property PACKAGE_PIN AN43 [get_ports CH0_DDR4_0_0_ba[0]]
set_property PACKAGE_PIN AL47 [get_ports CH0_DDR4_0_0_ba[1]]
set_property PACKAGE_PIN AP42 [get_ports CH0_DDR4_0_0_bg[0]]
set_property PACKAGE_PIN AT47 [get_ports CH0_DDR4_0_0_bg[1]]
set_property PACKAGE_PIN AR45 [get_ports CH0_DDR4_0_0_cke[0]]
set_property PACKAGE_PIN AU46 [get_ports CH0_DDR4_0_0_cke[1]]
set_property PACKAGE_PIN AT46 [get_ports CH0_DDR4_0_0_ck_c[0]]
set_property PACKAGE_PIN AR46 [get_ports CH0_DDR4_0_0_ck_t[0]]
set_property PACKAGE_PIN AN45 [get_ports CH0_DDR4_0_0_ck_c[1]]
set_property PACKAGE_PIN AP45 [get_ports CH0_DDR4_0_0_ck_t[1]]
set_property PACKAGE_PIN AF43 [get_ports sys_clk0_0_clk_n]
set_property PACKAGE_PIN AE42 [get_ports sys_clk0_0_clk_p]
set_property PACKAGE_PIN AL43 [get_ports CH0_DDR4_0_0_cs_n[0]]
set_property PACKAGE_PIN AM40 [get_ports CH0_DDR4_0_0_cs_n[1]]
set_property PACKAGE_PIN BC41 [get_ports CH0_DDR4_0_0_dm_n[0]]
set_property PACKAGE_PIN BB43 [get_ports CH0_DDR4_0_0_dm_n[1]]
set_property PACKAGE_PIN BB44 [get_ports CH0_DDR4_0_0_dm_n[2]]
set_property PACKAGE_PIN AR42 [get_ports CH0_DDR4_0_0_dm_n[3]]
set_property PACKAGE_PIN AH46 [get_ports CH0_DDR4_0_0_dm_n[4]]
set_property PACKAGE_PIN AH45 [get_ports CH0_DDR4_0_0_dm_n[5]]
set_property PACKAGE_PIN AG41 [get_ports CH0_DDR4_0_0_dm_n[6]]
set_property PACKAGE_PIN AG39 [get_ports CH0_DDR4_0_0_dm_n[7]]
set_property PACKAGE_PIN BB46 [get_ports CH0_DDR4_0_0_dm_n[8]]
set_property PACKAGE_PIN AU41 [get_ports CH0_DDR4_0_0_dq[0]]
set_property PACKAGE_PIN BC42 [get_ports CH0_DDR4_0_0_dq[10]]
set_property PACKAGE_PIN BC43 [get_ports CH0_DDR4_0_0_dq[11]]
set_property PACKAGE_PIN BD42 [get_ports CH0_DDR4_0_0_dq[12]]
set_property PACKAGE_PIN BE42 [get_ports CH0_DDR4_0_0_dq[13]]
set_property PACKAGE_PIN AW42 [get_ports CH0_DDR4_0_0_dq[14]]
set_property PACKAGE_PIN AW43 [get_ports CH0_DDR4_0_0_dq[15]]
set_property PACKAGE_PIN AW44 [get_ports CH0_DDR4_0_0_dq[16]]
set_property PACKAGE_PIN AV45 [get_ports CH0_DDR4_0_0_dq[17]]
set_property PACKAGE_PIN BC45 [get_ports CH0_DDR4_0_0_dq[18]]
set_property PACKAGE_PIN BD45 [get_ports CH0_DDR4_0_0_dq[19]]
set_property PACKAGE_PIN AV41 [get_ports CH0_DDR4_0_0_dq[1]]
set_property PACKAGE_PIN BD44 [get_ports CH0_DDR4_0_0_dq[20]]
set_property PACKAGE_PIN BE45 [get_ports CH0_DDR4_0_0_dq[21]]
set_property PACKAGE_PIN AY44 [get_ports CH0_DDR4_0_0_dq[22]]
set_property PACKAGE_PIN AW45 [get_ports CH0_DDR4_0_0_dq[23]]
set_property PACKAGE_PIN AM37 [get_ports CH0_DDR4_0_0_dq[24]]
set_property PACKAGE_PIN AN38 [get_ports CH0_DDR4_0_0_dq[25]]
set_property PACKAGE_PIN AR39 [get_ports CH0_DDR4_0_0_dq[26]]
set_property PACKAGE_PIN AT39 [get_ports CH0_DDR4_0_0_dq[27]]
set_property PACKAGE_PIN AT40 [get_ports CH0_DDR4_0_0_dq[28]]
set_property PACKAGE_PIN AT41 [get_ports CH0_DDR4_0_0_dq[29]]
set_property PACKAGE_PIN BE41 [get_ports CH0_DDR4_0_0_dq[2]]
set_property PACKAGE_PIN AP39 [get_ports CH0_DDR4_0_0_dq[30]]
set_property PACKAGE_PIN AN40 [get_ports CH0_DDR4_0_0_dq[31]]
set_property PACKAGE_PIN AD45 [get_ports CH0_DDR4_0_0_dq[32]]
set_property PACKAGE_PIN AE46 [get_ports CH0_DDR4_0_0_dq[33]]
set_property PACKAGE_PIN AH47 [get_ports CH0_DDR4_0_0_dq[34]]
set_property PACKAGE_PIN AJ47 [get_ports CH0_DDR4_0_0_dq[35]]
set_property PACKAGE_PIN AK46 [get_ports CH0_DDR4_0_0_dq[36]]
set_property PACKAGE_PIN AK47 [get_ports CH0_DDR4_0_0_dq[37]]
set_property PACKAGE_PIN AD47 [get_ports CH0_DDR4_0_0_dq[38]]
set_property PACKAGE_PIN AE47 [get_ports CH0_DDR4_0_0_dq[39]]
set_property PACKAGE_PIN BF41 [get_ports CH0_DDR4_0_0_dq[3]]
set_property PACKAGE_PIN AD44 [get_ports CH0_DDR4_0_0_dq[40]]
set_property PACKAGE_PIN AE44 [get_ports CH0_DDR4_0_0_dq[41]]
set_property PACKAGE_PIN AJ44 [get_ports CH0_DDR4_0_0_dq[42]]
set_property PACKAGE_PIN AJ45 [get_ports CH0_DDR4_0_0_dq[43]]
set_property PACKAGE_PIN AK44 [get_ports CH0_DDR4_0_0_dq[44]]
set_property PACKAGE_PIN AK45 [get_ports CH0_DDR4_0_0_dq[45]]
set_property PACKAGE_PIN AF44 [get_ports CH0_DDR4_0_0_dq[46]]
set_property PACKAGE_PIN AE45 [get_ports CH0_DDR4_0_0_dq[47]]
set_property PACKAGE_PIN AC39 [get_ports CH0_DDR4_0_0_dq[48]]
set_property PACKAGE_PIN AD40 [get_ports CH0_DDR4_0_0_dq[49]]
set_property PACKAGE_PIN BG41 [get_ports CH0_DDR4_0_0_dq[4]]
set_property PACKAGE_PIN AH40 [get_ports CH0_DDR4_0_0_dq[50]]
set_property PACKAGE_PIN AH41 [get_ports CH0_DDR4_0_0_dq[51]]
set_property PACKAGE_PIN AH39 [get_ports CH0_DDR4_0_0_dq[52]]
set_property PACKAGE_PIN AJ40 [get_ports CH0_DDR4_0_0_dq[53]]
set_property PACKAGE_PIN AE40 [get_ports CH0_DDR4_0_0_dq[54]]
set_property PACKAGE_PIN AD41 [get_ports CH0_DDR4_0_0_dq[55]]
set_property PACKAGE_PIN AC37 [get_ports CH0_DDR4_0_0_dq[56]]
set_property PACKAGE_PIN AD37 [get_ports CH0_DDR4_0_0_dq[57]]
set_property PACKAGE_PIN AG37 [get_ports CH0_DDR4_0_0_dq[58]]
set_property PACKAGE_PIN AH38 [get_ports CH0_DDR4_0_0_dq[59]]
set_property PACKAGE_PIN BF42 [get_ports CH0_DDR4_0_0_dq[5]]
set_property PACKAGE_PIN AH37 [get_ports CH0_DDR4_0_0_dq[60]]
set_property PACKAGE_PIN AJ38 [get_ports CH0_DDR4_0_0_dq[61]]
set_property PACKAGE_PIN AD38 [get_ports CH0_DDR4_0_0_dq[62]]
set_property PACKAGE_PIN AD39 [get_ports CH0_DDR4_0_0_dq[63]]
set_property PACKAGE_PIN AV46 [get_ports CH0_DDR4_0_0_dq[64]]
set_property PACKAGE_PIN AV47 [get_ports CH0_DDR4_0_0_dq[65]]
set_property PACKAGE_PIN BC46 [get_ports CH0_DDR4_0_0_dq[66]]
set_property PACKAGE_PIN BC47 [get_ports CH0_DDR4_0_0_dq[67]]
set_property PACKAGE_PIN BE46 [get_ports CH0_DDR4_0_0_dq[68]]
set_property PACKAGE_PIN BD47 [get_ports CH0_DDR4_0_0_dq[69]]
set_property PACKAGE_PIN AW40 [get_ports CH0_DDR4_0_0_dq[6]]
set_property PACKAGE_PIN AY46 [get_ports CH0_DDR4_0_0_dq[70]]
set_property PACKAGE_PIN AW47 [get_ports CH0_DDR4_0_0_dq[71]]
set_property PACKAGE_PIN AW41 [get_ports CH0_DDR4_0_0_dq[7]]
set_property PACKAGE_PIN AV42 [get_ports CH0_DDR4_0_0_dq[8]]
set_property PACKAGE_PIN AV43 [get_ports CH0_DDR4_0_0_dq[9]]
set_property PACKAGE_PIN BA41 [get_ports CH0_DDR4_0_0_dqs_c[0]]
set_property PACKAGE_PIN BA43 [get_ports CH0_DDR4_0_0_dqs_c[1]]
set_property PACKAGE_PIN BA44 [get_ports CH0_DDR4_0_0_dqs_c[2]]
set_property PACKAGE_PIN AP41 [get_ports CH0_DDR4_0_0_dqs_c[3]]
set_property PACKAGE_PIN AF46 [get_ports CH0_DDR4_0_0_dqs_c[4]]
set_property PACKAGE_PIN AG44 [get_ports CH0_DDR4_0_0_dqs_c[5]]
set_property PACKAGE_PIN AF40 [get_ports CH0_DDR4_0_0_dqs_c[6]]
set_property PACKAGE_PIN AF37 [get_ports CH0_DDR4_0_0_dqs_c[7]]
set_property PACKAGE_PIN BA46 [get_ports CH0_DDR4_0_0_dqs_c[8]]
set_property PACKAGE_PIN AY41 [get_ports CH0_DDR4_0_0_dqs_t[0]]
set_property PACKAGE_PIN AY42 [get_ports CH0_DDR4_0_0_dqs_t[1]]
set_property PACKAGE_PIN AY45 [get_ports CH0_DDR4_0_0_dqs_t[2]]
set_property PACKAGE_PIN AP40 [get_ports CH0_DDR4_0_0_dqs_t[3]]
set_property PACKAGE_PIN AF47 [get_ports CH0_DDR4_0_0_dqs_t[4]]
set_property PACKAGE_PIN AH43 [get_ports CH0_DDR4_0_0_dqs_t[5]]
set_property PACKAGE_PIN AF39 [get_ports CH0_DDR4_0_0_dqs_t[6]]
set_property PACKAGE_PIN AE38 [get_ports CH0_DDR4_0_0_dqs_t[7]]
set_property PACKAGE_PIN AY47 [get_ports CH0_DDR4_0_0_dqs_t[8]]
set_property PACKAGE_PIN AM39 [get_ports CH0_DDR4_0_0_odt[0]]
set_property PACKAGE_PIN AP47 [get_ports CH0_DDR4_0_0_odt[1]]
set_property PACKAGE_PIN AM43 [get_ports CH0_DDR4_0_0_par]
set_property PACKAGE_PIN AD42 [get_ports CH0_DDR4_0_0_reset_n]
## SO-DIMM 2
set_property PACKAGE_PIN BE35 [get_ports CH0_DDR4_1_0_adr[0]]
set_property PACKAGE_PIN BF32 [get_ports CH0_DDR4_1_0_adr[1]]
set_property PACKAGE_PIN BA32 [get_ports CH0_DDR4_1_0_adr[10]]
set_property PACKAGE_PIN AP34 [get_ports CH0_DDR4_1_0_adr[11]]
set_property PACKAGE_PIN AW31 [get_ports CH0_DDR4_1_0_adr[12]]
set_property PACKAGE_PIN BF31 [get_ports CH0_DDR4_1_0_adr[13]]
set_property PACKAGE_PIN AT32 [get_ports CH0_DDR4_1_0_adr[14]]
set_property PACKAGE_PIN AR33 [get_ports CH0_DDR4_1_0_adr[15]]
set_property PACKAGE_PIN BC33 [get_ports CH0_DDR4_1_0_adr[16]]
set_property PACKAGE_PIN BB33 [get_ports CH0_DDR4_1_0_adr[2]]
set_property PACKAGE_PIN AV34 [get_ports CH0_DDR4_1_0_adr[3]]
set_property PACKAGE_PIN AU33 [get_ports CH0_DDR4_1_0_adr[4]]
set_property PACKAGE_PIN AP33 [get_ports CH0_DDR4_1_0_adr[5]]
set_property PACKAGE_PIN AR32 [get_ports CH0_DDR4_1_0_adr[6]]
set_property PACKAGE_PIN BB31 [get_ports CH0_DDR4_1_0_adr[7]]
set_property PACKAGE_PIN BG34 [get_ports CH0_DDR4_1_0_adr[8]]
set_property PACKAGE_PIN BE32 [get_ports CH0_DDR4_1_0_adr[9]]
set_property PACKAGE_PIN BD32 [get_ports CH0_DDR4_1_0_act_n]
set_property PACKAGE_PIN BA39 [get_ports CH0_DDR4_1_0_alert_n]
set_property PACKAGE_PIN BA31 [get_ports CH0_DDR4_1_0_ba[0]]
set_property PACKAGE_PIN BF34 [get_ports CH0_DDR4_1_0_ba[1]]
set_property PACKAGE_PIN AY30 [get_ports CH0_DDR4_1_0_bg[0]]
set_property PACKAGE_PIN BE31 [get_ports CH0_DDR4_1_0_bg[1]]
set_property PACKAGE_PIN BC32 [get_ports CH0_DDR4_1_0_cke[0]]
set_property PACKAGE_PIN BG31 [get_ports CH0_DDR4_1_0_cke[1]]
set_property PACKAGE_PIN BC30 [get_ports CH0_DDR4_1_0_ck_c[0]]
set_property PACKAGE_PIN BC31 [get_ports CH0_DDR4_1_0_ck_t[0]]
set_property PACKAGE_PIN BE34 [get_ports CH0_DDR4_1_0_ck_c[1]]
set_property PACKAGE_PIN BD33 [get_ports CH0_DDR4_1_0_ck_t[1]]
set_property PACKAGE_PIN BA37 [get_ports sys_clk1_0_clk_n]
set_property PACKAGE_PIN AY37 [get_ports sys_clk1_0_clk_p]
set_property PACKAGE_PIN BB34 [get_ports CH0_DDR4_1_0_cs_n[0]]
set_property PACKAGE_PIN AW33 [get_ports CH0_DDR4_1_0_cs_n[1]]
set_property PACKAGE_PIN AR26 [get_ports CH0_DDR4_1_0_dm_n[0]]
set_property PACKAGE_PIN AV26 [get_ports CH0_DDR4_1_0_dm_n[1]]
set_property PACKAGE_PIN BD27 [get_ports CH0_DDR4_1_0_dm_n[2]]
set_property PACKAGE_PIN AR30 [get_ports CH0_DDR4_1_0_dm_n[3]]
set_property PACKAGE_PIN BE37 [get_ports CH0_DDR4_1_0_dm_n[4]]
set_property PACKAGE_PIN BD37 [get_ports CH0_DDR4_1_0_dm_n[5]]
set_property PACKAGE_PIN AW36 [get_ports CH0_DDR4_1_0_dm_n[6]]
set_property PACKAGE_PIN AR36 [get_ports CH0_DDR4_1_0_dm_n[7]]
set_property PACKAGE_PIN BE27 [get_ports CH0_DDR4_1_0_dm_n[8]]
set_property PACKAGE_PIN AM29 [get_ports CH0_DDR4_1_0_dq[0]]
set_property PACKAGE_PIN AT26 [get_ports CH0_DDR4_1_0_dq[10]]
set_property PACKAGE_PIN AT25 [get_ports CH0_DDR4_1_0_dq[11]]
set_property PACKAGE_PIN AU25 [get_ports CH0_DDR4_1_0_dq[12]]
set_property PACKAGE_PIN AV25 [get_ports CH0_DDR4_1_0_dq[13]]
set_property PACKAGE_PIN AR29 [get_ports CH0_DDR4_1_0_dq[14]]
set_property PACKAGE_PIN AT28 [get_ports CH0_DDR4_1_0_dq[15]]
set_property PACKAGE_PIN BB29 [get_ports CH0_DDR4_1_0_dq[16]]
set_property PACKAGE_PIN BB28 [get_ports CH0_DDR4_1_0_dq[17]]
set_property PACKAGE_PIN BB26 [get_ports CH0_DDR4_1_0_dq[18]]
set_property PACKAGE_PIN BC26 [get_ports CH0_DDR4_1_0_dq[19]]
set_property PACKAGE_PIN AN29 [get_ports CH0_DDR4_1_0_dq[1]]
set_property PACKAGE_PIN BA28 [get_ports CH0_DDR4_1_0_dq[20]]
set_property PACKAGE_PIN BA27 [get_ports CH0_DDR4_1_0_dq[21]]
set_property PACKAGE_PIN BD30 [get_ports CH0_DDR4_1_0_dq[22]]
set_property PACKAGE_PIN BD29 [get_ports CH0_DDR4_1_0_dq[23]]
set_property PACKAGE_PIN AM33 [get_ports CH0_DDR4_1_0_dq[24]]
set_property PACKAGE_PIN AM32 [get_ports CH0_DDR4_1_0_dq[25]]
set_property PACKAGE_PIN AV31 [get_ports CH0_DDR4_1_0_dq[26]]
set_property PACKAGE_PIN AV30 [get_ports CH0_DDR4_1_0_dq[27]]
set_property PACKAGE_PIN AT31 [get_ports CH0_DDR4_1_0_dq[28]]
set_property PACKAGE_PIN AU31 [get_ports CH0_DDR4_1_0_dq[29]]
set_property PACKAGE_PIN AM26 [get_ports CH0_DDR4_1_0_dq[2]]
set_property PACKAGE_PIN AM30 [get_ports CH0_DDR4_1_0_dq[30]]
set_property PACKAGE_PIN AN31 [get_ports CH0_DDR4_1_0_dq[31]]
set_property PACKAGE_PIN BE40 [get_ports CH0_DDR4_1_0_dq[32]]
set_property PACKAGE_PIN BE39 [get_ports CH0_DDR4_1_0_dq[33]]
set_property PACKAGE_PIN BF37 [get_ports CH0_DDR4_1_0_dq[34]]
set_property PACKAGE_PIN BG36 [get_ports CH0_DDR4_1_0_dq[35]]
set_property PACKAGE_PIN BE36 [get_ports CH0_DDR4_1_0_dq[36]]
set_property PACKAGE_PIN BF36 [get_ports CH0_DDR4_1_0_dq[37]]
set_property PACKAGE_PIN BG40 [get_ports CH0_DDR4_1_0_dq[38]]
set_property PACKAGE_PIN BG39 [get_ports CH0_DDR4_1_0_dq[39]]
set_property PACKAGE_PIN AN26 [get_ports CH0_DDR4_1_0_dq[3]]
set_property PACKAGE_PIN BC40 [get_ports CH0_DDR4_1_0_dq[40]]
set_property PACKAGE_PIN BD40 [get_ports CH0_DDR4_1_0_dq[41]]
set_property PACKAGE_PIN BB36 [get_ports CH0_DDR4_1_0_dq[42]]
set_property PACKAGE_PIN BC36 [get_ports CH0_DDR4_1_0_dq[43]]
set_property PACKAGE_PIN BB35 [get_ports CH0_DDR4_1_0_dq[44]]
set_property PACKAGE_PIN BC35 [get_ports CH0_DDR4_1_0_dq[45]]
set_property PACKAGE_PIN BB38 [get_ports CH0_DDR4_1_0_dq[46]]
set_property PACKAGE_PIN BC38 [get_ports CH0_DDR4_1_0_dq[47]]
set_property PACKAGE_PIN AW39 [get_ports CH0_DDR4_1_0_dq[48]]
set_property PACKAGE_PIN AY39 [get_ports CH0_DDR4_1_0_dq[49]]
set_property PACKAGE_PIN AN25 [get_ports CH0_DDR4_1_0_dq[4]]
set_property PACKAGE_PIN AW35 [get_ports CH0_DDR4_1_0_dq[50]]
set_property PACKAGE_PIN AY35 [get_ports CH0_DDR4_1_0_dq[51]]
set_property PACKAGE_PIN AU35 [get_ports CH0_DDR4_1_0_dq[52]]
set_property PACKAGE_PIN AV35 [get_ports CH0_DDR4_1_0_dq[53]]
set_property PACKAGE_PIN AU37 [get_ports CH0_DDR4_1_0_dq[54]]
set_property PACKAGE_PIN AU36 [get_ports CH0_DDR4_1_0_dq[55]]
set_property PACKAGE_PIN AM36 [get_ports CH0_DDR4_1_0_dq[56]]
set_property PACKAGE_PIN AM35 [get_ports CH0_DDR4_1_0_dq[57]]
set_property PACKAGE_PIN AR35 [get_ports CH0_DDR4_1_0_dq[58]]
set_property PACKAGE_PIN AT35 [get_ports CH0_DDR4_1_0_dq[59]]
set_property PACKAGE_PIN AP25 [get_ports CH0_DDR4_1_0_dq[5]]
set_property PACKAGE_PIN AN35 [get_ports CH0_DDR4_1_0_dq[60]]
set_property PACKAGE_PIN AP36 [get_ports CH0_DDR4_1_0_dq[61]]
set_property PACKAGE_PIN AP38 [get_ports CH0_DDR4_1_0_dq[62]]
set_property PACKAGE_PIN AR37 [get_ports CH0_DDR4_1_0_dq[63]]
set_property PACKAGE_PIN BE30 [get_ports CH0_DDR4_1_0_dq[64]]
set_property PACKAGE_PIN BE29 [get_ports CH0_DDR4_1_0_dq[65]]
set_property PACKAGE_PIN BE26 [get_ports CH0_DDR4_1_0_dq[66]]
set_property PACKAGE_PIN BF27 [get_ports CH0_DDR4_1_0_dq[67]]
set_property PACKAGE_PIN BF26 [get_ports CH0_DDR4_1_0_dq[68]]
set_property PACKAGE_PIN BG26 [get_ports CH0_DDR4_1_0_dq[69]]
set_property PACKAGE_PIN AM27 [get_ports CH0_DDR4_1_0_dq[6]]
set_property PACKAGE_PIN BG30 [get_ports CH0_DDR4_1_0_dq[70]]
set_property PACKAGE_PIN BG29 [get_ports CH0_DDR4_1_0_dq[71]]
set_property PACKAGE_PIN AN28 [get_ports CH0_DDR4_1_0_dq[7]]
set_property PACKAGE_PIN AT29 [get_ports CH0_DDR4_1_0_dq[8]]
set_property PACKAGE_PIN AU29 [get_ports CH0_DDR4_1_0_dq[9]]
set_property PACKAGE_PIN AR27 [get_ports CH0_DDR4_1_0_dqs_c[0]]
set_property PACKAGE_PIN AV27 [get_ports CH0_DDR4_1_0_dqs_c[1]]
set_property PACKAGE_PIN BD28 [get_ports CH0_DDR4_1_0_dqs_c[2]]
set_property PACKAGE_PIN AP31 [get_ports CH0_DDR4_1_0_dqs_c[3]]
set_property PACKAGE_PIN BG38 [get_ports CH0_DDR4_1_0_dqs_c[4]]
set_property PACKAGE_PIN BD38 [get_ports CH0_DDR4_1_0_dqs_c[5]]
set_property PACKAGE_PIN AW37 [get_ports CH0_DDR4_1_0_dqs_c[6]]
set_property PACKAGE_PIN AT37 [get_ports CH0_DDR4_1_0_dqs_c[7]]
set_property PACKAGE_PIN BG28 [get_ports CH0_DDR4_1_0_dqs_c[8]]
set_property PACKAGE_PIN AP28 [get_ports CH0_DDR4_1_0_dqs_t[0]]
set_property PACKAGE_PIN AU28 [get_ports CH0_DDR4_1_0_dqs_t[1]]
set_property PACKAGE_PIN BC28 [get_ports CH0_DDR4_1_0_dqs_t[2]]
set_property PACKAGE_PIN AN32 [get_ports CH0_DDR4_1_0_dqs_t[3]]
set_property PACKAGE_PIN BF39 [get_ports CH0_DDR4_1_0_dqs_t[4]]
set_property PACKAGE_PIN BD39 [get_ports CH0_DDR4_1_0_dqs_t[5]]
set_property PACKAGE_PIN AV38 [get_ports CH0_DDR4_1_0_dqs_t[6]]
set_property PACKAGE_PIN AT38 [get_ports CH0_DDR4_1_0_dqs_t[7]]
set_property PACKAGE_PIN BF29 [get_ports CH0_DDR4_1_0_dqs_t[8]]
set_property PACKAGE_PIN AV33 [get_ports CH0_DDR4_1_0_odt[0]]
set_property PACKAGE_PIN BG33 [get_ports CH0_DDR4_1_0_odt[1]]
set_property PACKAGE_PIN AY31 [get_ports CH0_DDR4_1_0_par]
set_property PACKAGE_PIN AY38 [get_ports CH0_DDR4_1_0_reset_n]
## SO-DIMM 3
set_property PACKAGE_PIN BB20 [get_ports CH0_DDR4_2_0_adr[0]]
set_property PACKAGE_PIN BF17 [get_ports CH0_DDR4_2_0_adr[1]]
set_property PACKAGE_PIN AY19 [get_ports CH0_DDR4_2_0_adr[10]]
set_property PACKAGE_PIN AM20 [get_ports CH0_DDR4_2_0_adr[11]]
set_property PACKAGE_PIN AV19 [get_ports CH0_DDR4_2_0_adr[12]]
set_property PACKAGE_PIN BF16 [get_ports CH0_DDR4_2_0_adr[13]]
set_property PACKAGE_PIN AR20 [get_ports CH0_DDR4_2_0_adr[14]]
set_property PACKAGE_PIN AP19 [get_ports CH0_DDR4_2_0_adr[15]]
set_property PACKAGE_PIN BG18 [get_ports CH0_DDR4_2_0_adr[16]]
set_property PACKAGE_PIN BB18 [get_ports CH0_DDR4_2_0_adr[2]]
set_property PACKAGE_PIN AT19 [get_ports CH0_DDR4_2_0_adr[3]]
set_property PACKAGE_PIN AR18 [get_ports CH0_DDR4_2_0_adr[4]]
set_property PACKAGE_PIN AN20 [get_ports CH0_DDR4_2_0_adr[5]]
set_property PACKAGE_PIN AN19 [get_ports CH0_DDR4_2_0_adr[6]]
set_property PACKAGE_PIN BA17 [get_ports CH0_DDR4_2_0_adr[7]]
set_property PACKAGE_PIN BA19 [get_ports CH0_DDR4_2_0_adr[8]]
set_property PACKAGE_PIN BE16 [get_ports CH0_DDR4_2_0_adr[9]]
set_property PACKAGE_PIN BD17 [get_ports CH0_DDR4_2_0_act_n]
set_property PACKAGE_PIN BB25 [get_ports CH0_DDR4_2_0_alert_n]
set_property PACKAGE_PIN AY18 [get_ports CH0_DDR4_2_0_ba[0]]
set_property PACKAGE_PIN BB19 [get_ports CH0_DDR4_2_0_ba[1]]
set_property PACKAGE_PIN AV18 [get_ports CH0_DDR4_2_0_bg[0]]
set_property PACKAGE_PIN BE17 [get_ports CH0_DDR4_2_0_bg[1]]
set_property PACKAGE_PIN BC17 [get_ports CH0_DDR4_2_0_cke[0]]
set_property PACKAGE_PIN BG16 [get_ports CH0_DDR4_2_0_cke[1]]
set_property PACKAGE_PIN BC16 [get_ports CH0_DDR4_2_0_ck_c[0]]
set_property PACKAGE_PIN BB16 [get_ports CH0_DDR4_2_0_ck_t[0]]
set_property PACKAGE_PIN BD18 [get_ports CH0_DDR4_2_0_ck_c[1]]
set_property PACKAGE_PIN BC18 [get_ports CH0_DDR4_2_0_ck_t[1]]
set_property PACKAGE_PIN BB24 [get_ports sys_clk2_0_clk_n]
set_property PACKAGE_PIN BA24 [get_ports sys_clk2_0_clk_p]
set_property PACKAGE_PIN BF18 [get_ports CH0_DDR4_2_0_cs_n[0]]
set_property PACKAGE_PIN AU19 [get_ports CH0_DDR4_2_0_cs_n[1]]
set_property PACKAGE_PIN AP12 [get_ports CH0_DDR4_2_0_dm_n[0]]
set_property PACKAGE_PIN AW12 [get_ports CH0_DDR4_2_0_dm_n[1]]
set_property PACKAGE_PIN BC13 [get_ports CH0_DDR4_2_0_dm_n[2]]
set_property PACKAGE_PIN AN16 [get_ports CH0_DDR4_2_0_dm_n[3]]
set_property PACKAGE_PIN BG21 [get_ports CH0_DDR4_2_0_dm_n[4]]
set_property PACKAGE_PIN BC23 [get_ports CH0_DDR4_2_0_dm_n[5]]
set_property PACKAGE_PIN AY22 [get_ports CH0_DDR4_2_0_dm_n[6]]
set_property PACKAGE_PIN AR21 [get_ports CH0_DDR4_2_0_dm_n[7]]
set_property PACKAGE_PIN BE12 [get_ports CH0_DDR4_2_0_dm_n[8]]
set_property PACKAGE_PIN AP15 [get_ports CH0_DDR4_2_0_dq[0]]
set_property PACKAGE_PIN AU12 [get_ports CH0_DDR4_2_0_dq[10]]
set_property PACKAGE_PIN AU11 [get_ports CH0_DDR4_2_0_dq[11]]
set_property PACKAGE_PIN AV11 [get_ports CH0_DDR4_2_0_dq[12]]
set_property PACKAGE_PIN AW11 [get_ports CH0_DDR4_2_0_dq[13]]
set_property PACKAGE_PIN AV15 [get_ports CH0_DDR4_2_0_dq[14]]
set_property PACKAGE_PIN AV14 [get_ports CH0_DDR4_2_0_dq[15]]
set_property PACKAGE_PIN BB15 [get_ports CH0_DDR4_2_0_dq[16]]
set_property PACKAGE_PIN BC15 [get_ports CH0_DDR4_2_0_dq[17]]
set_property PACKAGE_PIN BC12 [get_ports CH0_DDR4_2_0_dq[18]]
set_property PACKAGE_PIN BD12 [get_ports CH0_DDR4_2_0_dq[19]]
set_property PACKAGE_PIN AR15 [get_ports CH0_DDR4_2_0_dq[1]]
set_property PACKAGE_PIN BB11 [get_ports CH0_DDR4_2_0_dq[20]]
set_property PACKAGE_PIN BC11 [get_ports CH0_DDR4_2_0_dq[21]]
set_property PACKAGE_PIN BD15 [get_ports CH0_DDR4_2_0_dq[22]]
set_property PACKAGE_PIN BD14 [get_ports CH0_DDR4_2_0_dq[23]]
set_property PACKAGE_PIN AM18 [get_ports CH0_DDR4_2_0_dq[24]]
set_property PACKAGE_PIN AN17 [get_ports CH0_DDR4_2_0_dq[25]]
set_property PACKAGE_PIN AU17 [get_ports CH0_DDR4_2_0_dq[26]]
set_property PACKAGE_PIN AV17 [get_ports CH0_DDR4_2_0_dq[27]]
set_property PACKAGE_PIN AT17 [get_ports CH0_DDR4_2_0_dq[28]]
set_property PACKAGE_PIN AU16 [get_ports CH0_DDR4_2_0_dq[29]]
set_property PACKAGE_PIN AP11 [get_ports CH0_DDR4_2_0_dq[2]]
set_property PACKAGE_PIN AL16 [get_ports CH0_DDR4_2_0_dq[30]]
set_property PACKAGE_PIN AM17 [get_ports CH0_DDR4_2_0_dq[31]]
set_property PACKAGE_PIN BG25 [get_ports CH0_DDR4_2_0_dq[32]]
set_property PACKAGE_PIN BG24 [get_ports CH0_DDR4_2_0_dq[33]]
set_property PACKAGE_PIN BF21 [get_ports CH0_DDR4_2_0_dq[34]]
set_property PACKAGE_PIN BG20 [get_ports CH0_DDR4_2_0_dq[35]]
set_property PACKAGE_PIN BE21 [get_ports CH0_DDR4_2_0_dq[36]]
set_property PACKAGE_PIN BE20 [get_ports CH0_DDR4_2_0_dq[37]]
set_property PACKAGE_PIN BF24 [get_ports CH0_DDR4_2_0_dq[38]]
set_property PACKAGE_PIN BG23 [get_ports CH0_DDR4_2_0_dq[39]]
set_property PACKAGE_PIN AR12 [get_ports CH0_DDR4_2_0_dq[3]]
set_property PACKAGE_PIN BE25 [get_ports CH0_DDR4_2_0_dq[40]]
set_property PACKAGE_PIN BE24 [get_ports CH0_DDR4_2_0_dq[41]]
set_property PACKAGE_PIN BC22 [get_ports CH0_DDR4_2_0_dq[42]]
set_property PACKAGE_PIN BC21 [get_ports CH0_DDR4_2_0_dq[43]]
set_property PACKAGE_PIN BC20 [get_ports CH0_DDR4_2_0_dq[44]]
set_property PACKAGE_PIN BD20 [get_ports CH0_DDR4_2_0_dq[45]]
set_property PACKAGE_PIN BC25 [get_ports CH0_DDR4_2_0_dq[46]]
set_property PACKAGE_PIN BD25 [get_ports CH0_DDR4_2_0_dq[47]]
set_property PACKAGE_PIN AU24 [get_ports CH0_DDR4_2_0_dq[48]]
set_property PACKAGE_PIN AU23 [get_ports CH0_DDR4_2_0_dq[49]]
set_property PACKAGE_PIN AR11 [get_ports CH0_DDR4_2_0_dq[4]]
set_property PACKAGE_PIN AV22 [get_ports CH0_DDR4_2_0_dq[50]]
set_property PACKAGE_PIN AW21 [get_ports CH0_DDR4_2_0_dq[51]]
set_property PACKAGE_PIN AU21 [get_ports CH0_DDR4_2_0_dq[52]]
set_property PACKAGE_PIN AV21 [get_ports CH0_DDR4_2_0_dq[53]]
set_property PACKAGE_PIN AW24 [get_ports CH0_DDR4_2_0_dq[54]]
set_property PACKAGE_PIN AY25 [get_ports CH0_DDR4_2_0_dq[55]]
set_property PACKAGE_PIN AM24 [get_ports CH0_DDR4_2_0_dq[56]]
set_property PACKAGE_PIN AM23 [get_ports CH0_DDR4_2_0_dq[57]]
set_property PACKAGE_PIN AP22 [get_ports CH0_DDR4_2_0_dq[58]]
set_property PACKAGE_PIN AP21 [get_ports CH0_DDR4_2_0_dq[59]]
set_property PACKAGE_PIN AT11 [get_ports CH0_DDR4_2_0_dq[5]]
set_property PACKAGE_PIN AN23 [get_ports CH0_DDR4_2_0_dq[60]]
set_property PACKAGE_PIN AN22 [get_ports CH0_DDR4_2_0_dq[61]]
set_property PACKAGE_PIN AP24 [get_ports CH0_DDR4_2_0_dq[62]]
set_property PACKAGE_PIN AR24 [get_ports CH0_DDR4_2_0_dq[63]]
set_property PACKAGE_PIN BE15 [get_ports CH0_DDR4_2_0_dq[64]]
set_property PACKAGE_PIN BE14 [get_ports CH0_DDR4_2_0_dq[65]]
set_property PACKAGE_PIN BE11 [get_ports CH0_DDR4_2_0_dq[66]]
set_property PACKAGE_PIN BF12 [get_ports CH0_DDR4_2_0_dq[67]]
set_property PACKAGE_PIN BF11 [get_ports CH0_DDR4_2_0_dq[68]]
set_property PACKAGE_PIN BG11 [get_ports CH0_DDR4_2_0_dq[69]]
set_property PACKAGE_PIN AN14 [get_ports CH0_DDR4_2_0_dq[6]]
set_property PACKAGE_PIN BG15 [get_ports CH0_DDR4_2_0_dq[70]]
set_property PACKAGE_PIN BG14 [get_ports CH0_DDR4_2_0_dq[71]]
set_property PACKAGE_PIN AP13 [get_ports CH0_DDR4_2_0_dq[7]]
set_property PACKAGE_PIN AT14 [get_ports CH0_DDR4_2_0_dq[8]]
set_property PACKAGE_PIN AU15 [get_ports CH0_DDR4_2_0_dq[9]]
set_property PACKAGE_PIN AT13 [get_ports CH0_DDR4_2_0_dqs_c[0]]
set_property PACKAGE_PIN AV13 [get_ports CH0_DDR4_2_0_dqs_c[1]]
set_property PACKAGE_PIN BB13 [get_ports CH0_DDR4_2_0_dqs_c[2]]
set_property PACKAGE_PIN AR17 [get_ports CH0_DDR4_2_0_dqs_c[3]]
set_property PACKAGE_PIN BE22 [get_ports CH0_DDR4_2_0_dqs_c[4]]
set_property PACKAGE_PIN BD24 [get_ports CH0_DDR4_2_0_dqs_c[5]]
set_property PACKAGE_PIN AW23 [get_ports CH0_DDR4_2_0_dqs_c[6]]
set_property PACKAGE_PIN AR23 [get_ports CH0_DDR4_2_0_dqs_c[7]]
set_property PACKAGE_PIN BG13 [get_ports CH0_DDR4_2_0_dqs_c[8]]
set_property PACKAGE_PIN AR14 [get_ports CH0_DDR4_2_0_dqs_t[0]]
set_property PACKAGE_PIN AU13 [get_ports CH0_DDR4_2_0_dqs_t[1]]
set_property PACKAGE_PIN BB14 [get_ports CH0_DDR4_2_0_dqs_t[2]]
set_property PACKAGE_PIN AT16 [get_ports CH0_DDR4_2_0_dqs_t[3]]
set_property PACKAGE_PIN BF23 [get_ports CH0_DDR4_2_0_dqs_t[4]]
set_property PACKAGE_PIN BD23 [get_ports CH0_DDR4_2_0_dqs_t[5]]
set_property PACKAGE_PIN AV23 [get_ports CH0_DDR4_2_0_dqs_t[6]]
set_property PACKAGE_PIN AT23 [get_ports CH0_DDR4_2_0_dqs_t[7]]
set_property PACKAGE_PIN BF14 [get_ports CH0_DDR4_2_0_dqs_t[8]]
set_property PACKAGE_PIN AU20 [get_ports CH0_DDR4_2_0_odt[0]]
set_property PACKAGE_PIN BD19 [get_ports CH0_DDR4_2_0_odt[1]]
set_property PACKAGE_PIN AW19 [get_ports CH0_DDR4_2_0_par]
set_property PACKAGE_PIN BA25 [get_ports CH0_DDR4_2_0_reset_n]
## SO-DIMM 4
set_property PACKAGE_PIN AW2 [get_ports CH0_DDR4_3_0_adr[0]]
set_property PACKAGE_PIN AN1 [get_ports CH0_DDR4_3_0_adr[1]]
set_property PACKAGE_PIN AR6 [get_ports CH0_DDR4_3_0_adr[10]]
set_property PACKAGE_PIN AW9 [get_ports CH0_DDR4_3_0_adr[11]]
set_property PACKAGE_PIN AN6 [get_ports CH0_DDR4_3_0_adr[12]]
set_property PACKAGE_PIN AN2 [get_ports CH0_DDR4_3_0_adr[13]]
set_property PACKAGE_PIN AU9 [get_ports CH0_DDR4_3_0_adr[14]]
set_property PACKAGE_PIN AV9 [get_ports CH0_DDR4_3_0_adr[15]]