Commit 10d61812 authored by Torben Kalkhof's avatar Torben Kalkhof Committed by Carsten Heinz
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Add additional IPs for QDMA support

parent 09a55e7e
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//
// Generated by Bluespec Compiler, version 2022.01 (build 066c7a8)
//
// On Sat Apr 9 17:38:37 UTC 2022
//
//
// Ports:
// Name I/O size props
// drp_addr O 11 const
// drp_en O 1 reg
// drp_do O 16 const
// drp_we O 1 reg
// msix_vectors_per_pf0 O 32 const
// msix_vectors_per_pf1 O 32 const
// msix_vectors_per_pf2 O 32 const
// msix_vectors_per_pf3 O 32 const
// msix_vectors_per_vfg0 O 32 const
// msix_vectors_per_vfg1 O 32 const
// msix_vectors_per_vfg2 O 32 const
// msix_vectors_per_vfg3 O 32 const
// numvec_valid O 1 reg
// clk I 1 clock
// resetn I 1 reset
// drp_rdy I 1 reg
// drp_di I 16 unused
// numvec_done I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkQDMAConfigurator(clk,
resetn,
drp_addr,
drp_en,
drp_do,
drp_we,
drp_rdy,
drp_di,
msix_vectors_per_pf0,
msix_vectors_per_pf1,
msix_vectors_per_pf2,
msix_vectors_per_pf3,
msix_vectors_per_vfg0,
msix_vectors_per_vfg1,
msix_vectors_per_vfg2,
msix_vectors_per_vfg3,
numvec_valid,
numvec_done);
input clk;
input resetn;
// value method drp_drp_addr
output [10 : 0] drp_addr;
// value method drp_drp_en
output drp_en;
// value method drp_drp_do
output [15 : 0] drp_do;
// value method drp_drp_we
output drp_we;
// action method drp_get_rdy
input drp_rdy;
// action method drp_get_di
input [15 : 0] drp_di;
// value method msix_vec_ctrl_msix_vectors_per_pf0
output [31 : 0] msix_vectors_per_pf0;
// value method msix_vec_ctrl_msix_vectors_per_pf1
output [31 : 0] msix_vectors_per_pf1;
// value method msix_vec_ctrl_msix_vectors_per_pf2
output [31 : 0] msix_vectors_per_pf2;
// value method msix_vec_ctrl_msix_vectors_per_pf3
output [31 : 0] msix_vectors_per_pf3;
// value method msix_vec_ctrl_msix_vectors_per_vfg0
output [31 : 0] msix_vectors_per_vfg0;
// value method msix_vec_ctrl_msix_vectors_per_vfg1
output [31 : 0] msix_vectors_per_vfg1;
// value method msix_vec_ctrl_msix_vectors_per_vfg2
output [31 : 0] msix_vectors_per_vfg2;
// value method msix_vec_ctrl_msix_vectors_per_vfg3
output [31 : 0] msix_vectors_per_vfg3;
// value method msix_vec_ctrl_numvec_valid
output numvec_valid;
// action method msix_vec_ctrl_acceptDone
input numvec_done;
// signals for module outputs
wire [31 : 0] msix_vectors_per_pf0,
msix_vectors_per_pf1,
msix_vectors_per_pf2,
msix_vectors_per_pf3,
msix_vectors_per_vfg0,
msix_vectors_per_vfg1,
msix_vectors_per_vfg2,
msix_vectors_per_vfg3;
wire [15 : 0] drp_do;
wire [10 : 0] drp_addr;
wire drp_en, drp_we, numvec_valid;
// register drpEn
reg drpEn;
wire drpEn$D_IN, drpEn$EN;
// register drpRdy
reg drpRdy;
wire drpRdy$D_IN, drpRdy$EN;
// register drpWE
reg drpWE;
wire drpWE$D_IN, drpWE$EN;
// register numvecDone
reg numvecDone;
wire numvecDone$D_IN, numvecDone$EN;
// register numvecValid
reg numvecValid;
wire numvecValid$D_IN, numvecValid$EN;
// register state
reg [2 : 0] state;
reg [2 : 0] state$D_IN;
wire state$EN;
// rule scheduling signals
wire WILL_FIRE_RL_finishDrpWrite, WILL_FIRE_RL_startDrp;
// value method drp_drp_addr
assign drp_addr = 11'd213 ;
// value method drp_drp_en
assign drp_en = drpEn ;
// value method drp_drp_do
assign drp_do = 16'd255 ;
// value method drp_drp_we
assign drp_we = drpWE ;
// value method msix_vec_ctrl_msix_vectors_per_pf0
assign msix_vectors_per_pf0 = 32'd256 ;
// value method msix_vec_ctrl_msix_vectors_per_pf1
assign msix_vectors_per_pf1 = 32'd0 ;
// value method msix_vec_ctrl_msix_vectors_per_pf2
assign msix_vectors_per_pf2 = 32'd0 ;
// value method msix_vec_ctrl_msix_vectors_per_pf3
assign msix_vectors_per_pf3 = 32'd0 ;
// value method msix_vec_ctrl_msix_vectors_per_vfg0
assign msix_vectors_per_vfg0 = 32'd0 ;
// value method msix_vec_ctrl_msix_vectors_per_vfg1
assign msix_vectors_per_vfg1 = 32'd0 ;
// value method msix_vec_ctrl_msix_vectors_per_vfg2
assign msix_vectors_per_vfg2 = 32'd0 ;
// value method msix_vec_ctrl_msix_vectors_per_vfg3
assign msix_vectors_per_vfg3 = 32'd0 ;
// value method msix_vec_ctrl_numvec_valid
assign numvec_valid = numvecValid ;
// rule RL_startDrp
assign WILL_FIRE_RL_startDrp = state == 3'd3 && numvecDone ;
// rule RL_finishDrpWrite
assign WILL_FIRE_RL_finishDrpWrite = state == 3'd2 && drpRdy ;
// register drpEn
assign drpEn$D_IN = state != 3'd1 ;
assign drpEn$EN = state == 3'd1 || WILL_FIRE_RL_startDrp ;
// register drpRdy
assign drpRdy$D_IN = drp_rdy ;
assign drpRdy$EN = 1'd1 ;
// register drpWE
assign drpWE$D_IN = state != 3'd1 ;
assign drpWE$EN = state == 3'd1 || WILL_FIRE_RL_startDrp ;
// register numvecDone
assign numvecDone$D_IN = numvec_done ;
assign numvecDone$EN = 1'd1 ;
// register numvecValid
assign numvecValid$D_IN = !WILL_FIRE_RL_startDrp ;
assign numvecValid$EN = WILL_FIRE_RL_startDrp || state == 3'd0 ;
// register state
always@(WILL_FIRE_RL_startDrp or state or WILL_FIRE_RL_finishDrpWrite)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_startDrp: state$D_IN = 3'd1;
state == 3'd1: state$D_IN = 3'd2;
state == 3'd0: state$D_IN = 3'd3;
WILL_FIRE_RL_finishDrpWrite: state$D_IN = 3'd4;
default: state$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign state$EN =
WILL_FIRE_RL_startDrp || state == 3'd1 || state == 3'd0 ||
WILL_FIRE_RL_finishDrpWrite ;
// handling of inlined registers
always@(posedge clk)
begin
if (resetn == `BSV_RESET_VALUE)
begin
drpEn <= `BSV_ASSIGNMENT_DELAY 1'd0;
drpRdy <= `BSV_ASSIGNMENT_DELAY 1'd0;
drpWE <= `BSV_ASSIGNMENT_DELAY 1'd0;
numvecDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
numvecValid <= `BSV_ASSIGNMENT_DELAY 1'd0;
state <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (drpEn$EN) drpEn <= `BSV_ASSIGNMENT_DELAY drpEn$D_IN;
if (drpRdy$EN) drpRdy <= `BSV_ASSIGNMENT_DELAY drpRdy$D_IN;
if (drpWE$EN) drpWE <= `BSV_ASSIGNMENT_DELAY drpWE$D_IN;
if (numvecDone$EN)
numvecDone <= `BSV_ASSIGNMENT_DELAY numvecDone$D_IN;
if (numvecValid$EN)
numvecValid <= `BSV_ASSIGNMENT_DELAY numvecValid$D_IN;
if (state$EN) state <= `BSV_ASSIGNMENT_DELAY state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
drpEn = 1'h0;
drpRdy = 1'h0;
drpWE = 1'h0;
numvecDone = 1'h0;
numvecValid = 1'h0;
state = 3'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkQDMAConfigurator
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 2 FIFO
module FIFO2(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
parameter guarded = 1'b1;
input CLK ;
input RST ;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg full_reg;
reg empty_reg;
reg [width - 1 : 0] data0_reg;
reg [width - 1 : 0] data1_reg;
assign FULL_N = full_reg ;
assign EMPTY_N = empty_reg ;
assign D_OUT = data0_reg ;
// Optimize the loading logic since state encoding is not power of 2!
wire d0di = (ENQ && ! empty_reg ) || ( ENQ && DEQ && full_reg ) ;
wire d0d1 = DEQ && ! full_reg ;
wire d0h = ((! DEQ) && (! ENQ )) || (!DEQ && empty_reg ) || ( ! ENQ &&full_reg) ;
wire d1di = ENQ & empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
data0_reg = {((width + 1)/2) {2'b10}} ;
data1_reg = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0;
full_reg = 1'b1;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (CLR)
else if ( ENQ && ! DEQ ) // just enq
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg ;
end
else if ( DEQ && ! ENQ )
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if ( DEQ && ! ENQ )
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
data1_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY
{width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ;
data1_reg <= `BSV_ASSIGNMENT_DELAY
d1di ? D_IN : data1_reg ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1;
$display( "Warning: FIFO2: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && (!DEQ || guarded) )
begin
enqerror = 1;
$display( "Warning: FIFO2: %m -- Enqueuing to a full fifo" ) ;
end
end
end // always@ (posedge CLK)
// synopsys translate_on
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1'b1;
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
(* RAM_STYLE = "DISTRIBUTED" *)
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)