Commit 1221cbdc authored by Jaco Hofmann's avatar Jaco Hofmann
Browse files

Adds ID signals back in to avoid Vivado errors

parent e495ff21
......@@ -175,6 +175,14 @@
<spirit:addressSpaceRef spirit:addressSpaceRef="m32_axi"/>
</spirit:master>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m32_axi_awid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
......@@ -319,6 +327,14 @@
<spirit:name>m32_axi_wready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m32_axi_bid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
......@@ -351,6 +367,14 @@
<spirit:name>m32_axi_bready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m32_axi_arid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
......@@ -447,6 +471,14 @@
<spirit:name>m32_axi_arready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m32_axi_rid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
......@@ -519,6 +551,14 @@
<spirit:addressSpaceRef spirit:addressSpaceRef="m64_axi"/>
</spirit:master>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m64_axi_awid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
......@@ -663,6 +703,14 @@
<spirit:name>m64_axi_wready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m64_axi_bid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
......@@ -695,6 +743,14 @@
<spirit:name>m64_axi_bready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m64_axi_arid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
......@@ -791,6 +847,14 @@
<spirit:name>m64_axi_arready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m64_axi_rid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
......@@ -1060,7 +1124,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>d8bbcf6d</spirit:value>
<spirit:value>069857fc</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -1076,7 +1140,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>d8bbcf6d</spirit:value>
<spirit:value>069857fc</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -1519,6 +1583,19 @@
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m64_axi_arid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m64_axi_araddr</spirit:name>
<spirit:wire>
......@@ -1710,6 +1787,22 @@
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m64_axi_rid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m64_axi_rdata</spirit:name>
<spirit:wire>
......@@ -1811,6 +1904,19 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m64_axi_awid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m64_axi_awaddr</spirit:name>
<spirit:wire>
......@@ -2111,6 +2217,22 @@
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m64_axi_bid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m64_axi_buser</spirit:name>
<spirit:wire>
......@@ -2156,6 +2278,19 @@
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m32_axi_arid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m32_axi_araddr</spirit:name>
<spirit:wire>
......@@ -2347,6 +2482,22 @@
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m32_axi_rid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m32_axi_rdata</spirit:name>
<spirit:wire>
......@@ -2448,6 +2599,19 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m32_axi_awid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m32_axi_awaddr</spirit:name>
<spirit:wire>
......@@ -2748,6 +2912,22 @@
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m32_axi_bid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>m32_axi_buser</spirit:name>
<spirit:wire>
......@@ -2823,7 +3003,7 @@
<spirit:file>
<spirit:name>src/mkBlueDMAVivado.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_ded56ed9</spirit:userFileType>
<spirit:userFileType>CHECKSUM_abab4df6</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
......@@ -2887,18 +3067,18 @@
<xilinx:displayName>BlueDMA</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-07T14:29:44Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2017-07-10T16:46:33Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="37c8a920"/>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9aa6aa20"/>
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7dca891b"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="434bb713"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c93d048c"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="8523f8a5"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1bb46e31"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
......
This diff is collapsed.
//
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
//
// On Fri Jul 7 14:37:18 CEST 2017
// On Mon Jul 10 18:45:54 CEST 2017
//
//
// Ports:
......@@ -15,6 +15,7 @@
// S_AXI_bvalid O 1 reg
// S_AXI_bresp O 2
// m64_axi_arvalid O 1 reg
// m64_axi_arid O 1
// m64_axi_araddr O 64
// m64_axi_arlen O 8
// m64_axi_arsize O 3
......@@ -27,6 +28,7 @@
// m64_axi_aruser O 1
// m64_axi_rready O 1 reg
// m64_axi_awvalid O 1 reg
// m64_axi_awid O 1
// m64_axi_awaddr O 64
// m64_axi_awlen O 8
// m64_axi_awsize O 3
......@@ -44,6 +46,7 @@
// m64_axi_wuser O 1
// m64_axi_bready O 1 reg
// m32_axi_arvalid O 1 reg
// m32_axi_arid O 1
// m32_axi_araddr O 64
// m32_axi_arlen O 8
// m32_axi_arsize O 3
......@@ -56,6 +59,7 @@
// m32_axi_aruser O 1
// m32_axi_rready O 1 reg
// m32_axi_awvalid O 1 reg
// m32_axi_awid O 1
// m32_axi_awaddr O 64
// m32_axi_awlen O 8
// m32_axi_awsize O 3
......@@ -92,6 +96,7 @@
// S_AXI_bready I 1
// m64_axi_arready I 1
// m64_axi_rvalid I 1
// m64_axi_rid I 1 reg
// m64_axi_rdata I 256 reg
// m64_axi_rresp I 2 reg
// m64_axi_rlast I 1 reg
......@@ -100,9 +105,11 @@
// m64_axi_wready I 1
// m64_axi_bvalid I 1
// m64_axi_bresp I 2 reg
// m64_axi_bid I 1 reg
// m64_axi_buser I 1 reg
// m32_axi_arready I 1
// m32_axi_rvalid I 1
// m32_axi_rid I 1 reg
// m32_axi_rdata I 512 reg
// m32_axi_rresp I 2 reg
// m32_axi_rlast I 1 reg
......@@ -111,6 +118,7 @@
// m32_axi_wready I 1
// m32_axi_bvalid I 1
// m32_axi_bresp I 2 reg
// m32_axi_bid I 1 reg
// m32_axi_buser I 1 reg
//
// No combinational paths from inputs to outputs
......@@ -179,6 +187,8 @@ module mkBlueDMAVivado(m32_axi_aclk,
m64_axi_arready,
m64_axi_arid,
m64_axi_araddr,
m64_axi_arlen,
......@@ -203,6 +213,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
m64_axi_rvalid,
m64_axi_rid,
m64_axi_rdata,
m64_axi_rresp,
m64_axi_rlast,
......@@ -212,6 +223,8 @@ module mkBlueDMAVivado(m32_axi_aclk,
m64_axi_awvalid,
m64_axi_awid,
m64_axi_awaddr,
m64_axi_awlen,
......@@ -249,12 +262,15 @@ module mkBlueDMAVivado(m32_axi_aclk,
m64_axi_bready,
m64_axi_bresp,
m64_axi_bid,
m64_axi_buser,
m32_axi_arvalid,
m32_axi_arready,
m32_axi_arid,
m32_axi_araddr,
m32_axi_arlen,
......@@ -279,6 +295,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
m32_axi_rvalid,
m32_axi_rid,
m32_axi_rdata,
m32_axi_rresp,
m32_axi_rlast,
......@@ -288,6 +305,8 @@ module mkBlueDMAVivado(m32_axi_aclk,
m32_axi_awvalid,
m32_axi_awid,
m32_axi_awaddr,
m32_axi_awlen,
......@@ -325,6 +344,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
m32_axi_bready,
m32_axi_bresp,
m32_axi_bid,
m32_axi_buser,
IRQ);
......@@ -399,6 +419,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
input m64_axi_arready;
// value method pcie_rd_arid
output m64_axi_arid;
// value method pcie_rd_araddr
output [63 : 0] m64_axi_araddr;
......@@ -437,6 +458,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
input m64_axi_rvalid;
// action method pcie_rd_prchannel
input m64_axi_rid;
input [255 : 0] m64_axi_rdata;
input [1 : 0] m64_axi_rresp;
input m64_axi_rlast;
......@@ -449,6 +471,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
output m64_axi_awvalid;
// value method pcie_wr_awid
output m64_axi_awid;
// value method pcie_wr_awaddr
output [63 : 0] m64_axi_awaddr;
......@@ -506,6 +529,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
// action method pcie_wr_bin
input [1 : 0] m64_axi_bresp;
input m64_axi_bid;
input m64_axi_buser;
// value method fpga_rd_arvalid
......@@ -515,6 +539,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
input m32_axi_arready;
// value method fpga_rd_arid
output m32_axi_arid;
// value method fpga_rd_araddr
output [63 : 0] m32_axi_araddr;
......@@ -553,6 +578,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
input m32_axi_rvalid;
// action method fpga_rd_prchannel
input m32_axi_rid;
input [511 : 0] m32_axi_rdata;
input [1 : 0] m32_axi_rresp;
input m32_axi_rlast;
......@@ -565,6 +591,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
output m32_axi_awvalid;
// value method fpga_wr_awid
output m32_axi_awid;
// value method fpga_wr_awaddr
output [63 : 0] m32_axi_awaddr;
......@@ -622,6 +649,7 @@ module mkBlueDMAVivado(m32_axi_aclk,
// action method fpga_wr_bin
input [1 : 0] m32_axi_bresp;
input m32_axi_bid;
input m32_axi_buser;
// value method interrupt
......@@ -670,9 +698,11 @@ module mkBlueDMAVivado(m32_axi_aclk,
S_AXI_bvalid,
S_AXI_rvalid,
S_AXI_wready,
m32_axi_arid,
m32_axi_arlock,
m32_axi_aruser,
m32_axi_arvalid,
m32_axi_awid,
m32_axi_awlock,
m32_axi_awuser,
m32_axi_awvalid,
......@@ -681,9 +711,11 @@ module mkBlueDMAVivado(m32_axi_aclk,
m32_axi_wlast,
m32_axi_wuser,
m32_axi_wvalid,
m64_axi_arid,
m64_axi_arlock,
m64_axi_aruser,
m64_axi_arvalid,
m64_axi_awid,
m64_axi_awlock,
m64_axi_awuser,
m64_axi_awvalid,
......@@ -753,18 +785,22 @@ module mkBlueDMAVivado(m32_axi_aclk,
blueDMA$S_AXI_rvalid,
blueDMA$S_AXI_wready,
blueDMA$S_AXI_wvalid,
blueDMA$fpga_rd_arid,
blueDMA$fpga_rd_arlock,
blueDMA$fpga_rd_arready,
blueDMA$fpga_rd_aruser,
blueDMA$fpga_rd_arvalid,
blueDMA$fpga_rd_rid,
blueDMA$fpga_rd_rlast,
blueDMA$fpga_rd_rready,
blueDMA$fpga_rd_ruser,
blueDMA$fpga_rd_rvalid,
blueDMA$fpga_wr_awid,
blueDMA$fpga_wr_awlock,
blueDMA$fpga_wr_awready,
blueDMA$fpga_wr_awuser,
blueDMA$fpga_wr_awvalid,
blueDMA$fpga_wr_bid,
blueDMA$fpga_wr_bready,
blueDMA$fpga_wr_buser,
blueDMA$fpga_wr_bvalid,
......@@ -773,18 +809,22 @@ module mkBlueDMAVivado(m32_axi_aclk,
blueDMA$fpga_wr_wuser,
blueDMA$fpga_wr_wvalid,
blueDMA$interrupt,
blueDMA$pcie_rd_arid,
blueDMA$pcie_rd_arlock,
blueDMA$pcie_rd_arready,
blueDMA$pcie_rd_aruser,
blueDMA$pcie_rd_arvalid,
blueDMA$pcie_rd_rid,
blueDMA$pcie_rd_rlast,
blueDMA$pcie_rd_rready,
blueDMA$pcie_rd_ruser,
blueDMA$pcie_rd_rvalid,
blueDMA$pcie_wr_awid,
blueDMA$pcie_wr_awlock,
blueDMA$pcie_wr_awready,
blueDMA$pcie_wr_awuser,
blueDMA$pcie_wr_awvalid,
blueDMA$pcie_wr_bid,
blueDMA$pcie_wr_bready,
blueDMA$pcie_wr_buser,
blueDMA$pcie_wr_bvalid,
......@@ -820,6 +860,9 @@ module mkBlueDMAVivado(m32_axi_aclk,
// value method pcie_rd_arvalid
assign m64_axi_arvalid = blueDMA$pcie_rd_arvalid ;
// value method pcie_rd_arid
assign m64_axi_arid = blueDMA$pcie_rd_arid ;
// value method pcie_rd_araddr
assign m64_axi_araddr = blueDMA$pcie_rd_araddr ;
......@@ -863,6 +906,9 @@ module mkBlueDMAVivado(m32_axi_aclk,
// value method pcie_wr_awvalid
assign m64_axi_awvalid = blueDMA$pcie_wr_awvalid ;
// value method pcie_wr_awid
assign m64_axi_awid = blueDMA$pcie_wr_awid ;
// value method pcie_wr_awaddr
assign m64_axi_awaddr = blueDMA$pcie_wr_awaddr ;
......@@ -921,6 +967,9 @@ module mkBlueDMAVivado(m32_axi_aclk,
// value method fpga_rd_arvalid
assign m32_axi_arvalid = blueDMA$fpga_rd_arvalid ;
// value method fpga_rd_arid
assign m32_axi_arid = blueDMA$fpga_rd_arid ;
// value method fpga_rd_araddr
assign m32_axi_araddr = blueDMA$fpga_rd_araddr ;
......@@ -964,6 +1013,9 @@ module mkBlueDMAVivado(m32_axi_aclk,
// value method fpga_wr_awvalid
assign m32_axi_awvalid = blueDMA$fpga_wr_awvalid ;
// value method fpga_wr_awid
assign m32_axi_awid = blueDMA$fpga_wr_awid ;
// value method fpga_wr_awaddr
assign m32_axi_awaddr = blueDMA$fpga_wr_awaddr ;
......@@ -1042,22 +1094,26 @@ module mkBlueDMAVivado(m32_axi_aclk,
.S_AXI_wvalid(blueDMA$S_AXI_wvalid),
.fpga_rd_arready(blueDMA$fpga_rd_arready),
.fpga_rd_rdata(blueDMA$fpga_rd_rdata),
.fpga_rd_rid(blueDMA$fpga_rd_rid),
.fpga_rd_rlast(blueDMA$fpga_rd_rlast),
.fpga_rd_rresp(blueDMA$fpga_rd_rresp),
.fpga_rd_ruser(blueDMA$fpga_rd_ruser),
.fpga_rd_rvalid(blueDMA$fpga_rd_rvalid),
.fpga_wr_awready(blueDMA$fpga_wr_awready),
.fpga_wr_bid(blueDMA$fpga_wr_bid),
.fpga_wr_bresp(blueDMA$fpga_wr_bresp),
.fpga_wr_buser(blueDMA$fpga_wr_buser),
.fpga_wr_bvalid(blueDMA$fpga_wr_bvalid),
.fpga_wr_wready(blueDMA$fpga_wr_wready),
.pcie_rd_arready(blueDMA$pcie_rd_arready),
.pcie_rd_rdata(blueDMA$pcie_rd_rdata),
.pcie_rd_rid(blueDMA$pcie_rd_rid),