Commit 1466aa9c authored by Jaco Hofmann's avatar Jaco Hofmann
Browse files

Updates BlueDMA and MSIx Interrupt Controller to newest versions

parent 8040311c
......@@ -1063,28 +1063,6 @@
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>IRQ</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>INTERRUPT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>IRQ</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SENSITIVITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.IRQ.SENSITIVITY" spirit:choiceRef="choice_list_99a1d2b9">LEVEL_HIGH</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:addressSpaces>
<spirit:addressSpace>
......@@ -1104,7 +1082,7 @@
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
<spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
<spirit:range spirit:format="long" spirit:resolve="user" spirit:minimum="4096" spirit:rangeType="long">16777216T</spirit:range>
<spirit:range spirit:format="long" spirit:resolve="user" spirit:minimum="4096" spirit:rangeType="long">4096</spirit:range>
<spirit:width spirit:format="long" spirit:resolve="user">64</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
......@@ -1124,7 +1102,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>069857fc</spirit:value>
<spirit:value>ff8a092a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -1140,7 +1118,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>069857fc</spirit:value>
<spirit:value>81bd05da</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -1687,7 +1665,7 @@
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
......@@ -2008,7 +1986,7 @@
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
......@@ -2382,7 +2360,7 @@
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
......@@ -2703,7 +2681,7 @@
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
......@@ -2945,7 +2923,20 @@
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>IRQ</spirit:name>
<spirit:name>IRQ_write</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>IRQ_read</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
......@@ -2960,13 +2951,6 @@
</spirit:ports>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_99a1d2b9</spirit:name>
<spirit:enumeration>LEVEL_HIGH</spirit:enumeration>
<spirit:enumeration>LEVEL_LOW</spirit:enumeration>
<spirit:enumeration>EDGE_RISING</spirit:enumeration>
<spirit:enumeration>EDGE_FALLING</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_list_9d8b0d81</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
......@@ -2977,8 +2961,25 @@
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/SyncFIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:name>constraints/bluedma.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:define>
<spirit:name>processing_order</spirit:name>
<spirit:value>late</spirit:value>
</spirit:define>
</spirit:file>
<spirit:file>
<spirit:name>constraints/bluedma.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:define>
<spirit:name>processing_order</spirit:name>
<spirit:value>late</spirit:value>
</spirit:define>
</spirit:file>
<spirit:file>
<spirit:name>src/FIFO1.v</spirit:name>
......@@ -2997,21 +2998,17 @@
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/mkBlueDMA.v</spirit:name>
<spirit:name>src/SyncFIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/mkBlueDMAVivado.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_abab4df6</spirit:userFileType>
<spirit:userFileType>CHECKSUM_f4b809fa</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/SyncFIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/FIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
......@@ -3029,7 +3026,7 @@
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/mkBlueDMA.v</spirit:name>
<spirit:name>src/SyncFIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
......@@ -3057,9 +3054,25 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
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<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Pre-Production">kintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Pre-Production">qzynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Pre-Production">kintexu</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
......@@ -3067,19 +3080,19 @@
<xilinx:displayName>BlueDMA</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-10T16:46:33Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2018-01-30T15:28:45Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
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<xilinx:xilinxVersion>2017.2</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="d0fc19af"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="4a3aac11"/>
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</spirit:vendorExtensions>
</spirit:component>
##
## set properties to help out clock domain crossing analysis
##
foreach pat {"reset_hold_reg[*]" "sGEnqPtr*_reg[*]" "dGDeqPtr*_reg[*]" "sSyncReg*_reg[*]" "dSyncReg*_reg[*]" "dEnqPtr*_reg[*]"} {
set cells [get_cells -hier $pat]
if {[llength $cells] > 0} {
puts "ASYNC_REG $cells"
set_property ASYNC_REG 1 $cells
}
}
##
## set properties to help out clock domain crossing analysis
##
set s_clk [get_clocks -of_objects [get_ports -scoped_to_current_instance m32_axi_aclk]]
set m_clk [get_clocks -of_object [get_ports -scoped_to_current_instance m64_axi_aclk]]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance m32_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance m64_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $s_clk]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance m64_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance m32_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $m_clk]
set g_clk [get_clocks -of_objects [get_ports -scoped_to_current_instance s_axi_aclk]]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance m32_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $s_clk]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance m32_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $g_clk]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance m64_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $m_clk]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance m64_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $g_clk]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *reset_hold_reg*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *sGEnqPtr*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dGDeqPtr*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *sSyncReg*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dSyncReg*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dEnqPtr*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dEnqToggle*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dDeqToggle*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dNotEmpty*}] {IS_SEQUENTIAL}]
\ No newline at end of file
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 33367 $
// $Date: 2014-02-18 17:46:14 +0000 (Tue, 18 Feb 2014) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
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......@@ -427,7 +427,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>e07e9e3a</spirit:value>
<spirit:value>ba3c4982</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -443,7 +443,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>e07e9e3a</spirit:value>
<spirit:value>062ac467</spirit:value>
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......@@ -1248,6 +1248,16 @@
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>constraints/msix_intr_ctrl.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:define>
<spirit:name>processing_order</spirit:name>
<spirit:value>late</spirit:value>
</spirit:define>
</spirit:file>
<spirit:file>
<spirit:name>src/BRAM2BE.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
......@@ -1267,7 +1277,7 @@
<spirit:file>
<spirit:name>src/mkMSIXIntrCtrl.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_f02cbad3</spirit:userFileType>
<spirit:userFileType>CHECKSUM_8ffb020d</spirit:userFileType>
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......@@ -1313,9 +1323,25 @@
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......@@ -1323,19 +1349,19 @@
<xilinx:displayName>MSIXIntrCtrl</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-07T08:36:48Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2018-01-30T15:21:42Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
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<xilinx:xilinxVersion>2017.2</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f94240"/>
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set_false_path -through [get_ports -scoped_to_current_instance interrupt*]
set_false_path -through [get_pins system_i/InterruptControl/msix_intr_ctrl/interrupt*]
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
//
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
// Generated by Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21)
//
// On Fri Jul 7 10:35:33 CEST 2017
// On Tue Jan 30 16:19:24 CET 2018
//
//
// Ports:
......@@ -352,6 +352,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
msixTable_serverAdapterB_writeWithResp$whas,
nextInterrupt_rv$EN_port1__write,
s_config_readIsHandled$whas,
s_config_writeIsHandled$whas,
s_config_writeSlave_addrIn_rv$EN_port0__write,
s_config_writeSlave_addrIn_rv$EN_port1__write,
s_config_writeSlave_dataIn_rv$EN_port0__write,
......@@ -2676,6 +2677,10 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
reg s_config_readBusy;
wire s_config_readBusy$D_IN, s_config_readBusy$EN;
 
// register s_config_writeBusy
reg s_config_writeBusy;
wire s_config_writeBusy$D_IN, s_config_writeBusy$EN;
// register s_config_writeSlave_addrIn_rv
reg [19 : 0] s_config_writeSlave_addrIn_rv;
wire [19 : 0] s_config_writeSlave_addrIn_rv$D_IN;
......@@ -3338,7 +3343,8 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
writeMaster_out$FULL_N;
 
// rule scheduling signals
wire WILL_FIRE_RL_catchInterrupt,
wire CAN_FIRE_RL_s_config_1_axiWriteSpecialRange,
WILL_FIRE_RL_catchInterrupt,
WILL_FIRE_RL_catchInterrupt_1,
WILL_FIRE_RL_catchInterrupt_10,
WILL_FIRE_RL_catchInterrupt_100,
......@@ -3641,140 +3647,141 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
MUX_send_pending$write_1__SEL_2;
 
// remaining internal signals
reg [31 : 0] v__h28373;
reg [31 : 0] v__h28313;
reg SEL_ARR_vector_control_0_81_vector_control_1_8_ETC___d315;
wire [63 : 0] x_addr__h93468;
wire [31 : 0] r__h28538;
wire [15 : 0] addr__h28721, i__h28618, i__h54994;
wire [7 : 0] IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1830,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1832,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1833,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1835,
wire [63 : 0] x_addr__h93507;
wire [31 : 0] r__h28478;
wire [15 : 0] addr__h28657, i__h28558, i__h60164;
wire [7 : 0] IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1834,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1836,
IF_vector_control_100_81_OR_NOT_pba_vector_100_ETC___d1733,
IF_vector_control_104_85_OR_NOT_pba_vector_104_ETC___d1729,
IF_vector_control_108_89_OR_NOT_pba_vector_108_ETC___d1726,
IF_vector_control_112_93_OR_NOT_pba_vector_112_ETC___d1721,
IF_vector_control_112_93_OR_NOT_pba_vector_112_ETC___d1723,
IF_vector_control_116_97_OR_NOT_pba_vector_116_ETC___d1718,
IF_vector_control_120_01_OR_NOT_pba_vector_120_ETC___d1714,
IF_vector_control_124_05_OR_NOT_pba_vector_124_ETC___d1711,
IF_vector_control_128_09_OR_NOT_pba_vector_128_ETC___d1708,
IF_vector_control_12_93_OR_NOT_pba_vector_12_9_ETC___d1820,
IF_vector_control_16_97_OR_NOT_pba_vector_16_8_ETC___d1815,
IF_vector_control_16_97_OR_NOT_pba_vector_16_8_ETC___d1817,
IF_vector_control_20_01_OR_NOT_pba_vector_20_8_ETC___d1812,
IF_vector_control_24_05_OR_NOT_pba_vector_24_7_ETC___d1808,
IF_vector_control_28_09_OR_NOT_pba_vector_28_7_ETC___d1805,
IF_vector_control_32_13_OR_NOT_pba_vector_32_6_ETC___d1799,
IF_vector_control_32_13_OR_NOT_pba_vector_32_6_ETC___d1801,
IF_vector_control_32_13_OR_NOT_pba_vector_32_6_ETC___d1802,
IF_vector_control_36_17_OR_NOT_pba_vector_36_5_ETC___d1796,
IF_vector_control_40_21_OR_NOT_pba_vector_40_4_ETC___d1792,
IF_vector_control_44_25_OR_NOT_pba_vector_44_4_ETC___d1789,
IF_vector_control_48_29_OR_NOT_pba_vector_48_3_ETC___d1784,
IF_vector_control_48_29_OR_NOT_pba_vector_48_3_ETC___d1786,
IF_vector_control_4_85_OR_NOT_pba_vector_4_06__ETC___d1827,
IF_vector_control_52_33_OR_NOT_pba_vector_52_3_ETC___d1781,
IF_vector_control_56_37_OR_NOT_pba_vector_56_2_ETC___d1777,
IF_vector_control_60_41_OR_NOT_pba_vector_60_1_ETC___d1774,
IF_vector_control_64_45_OR_NOT_pba_vector_64_0_ETC___d1767,
IF_vector_control_64_45_OR_NOT_pba_vector_64_0_ETC___d1769,
IF_vector_control_64_45_OR_NOT_pba_vector_64_0_ETC___d1770,
IF_vector_control_68_49_OR_NOT_pba_vector_68_0_ETC___d1764,
IF_vector_control_72_53_OR_NOT_pba_vector_72_9_ETC___d1760,
IF_vector_control_76_57_OR_NOT_pba_vector_76_9_ETC___d1757,
IF_vector_control_80_61_OR_NOT_pba_vector_80_8_ETC___d1752,
IF_vector_control_80_61_OR_NOT_pba_vector_80_8_ETC___d1754,
IF_vector_control_84_65_OR_NOT_pba_vector_84_7_ETC___d1749,
IF_vector_control_88_69_OR_NOT_pba_vector_88_7_ETC___d1745,
IF_vector_control_8_89_OR_NOT_pba_vector_8_00__ETC___d1823,
IF_vector_control_92_73_OR_NOT_pba_vector_92_6_ETC___d1742,
IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1736,
IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1738,
IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1739;
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1837,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1839,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1840,
IF_vector_control_100_81_OR_NOT_pba_vector_100_ETC___d1737,
IF_vector_control_104_85_OR_NOT_pba_vector_104_ETC___d1733,
IF_vector_control_108_89_OR_NOT_pba_vector_108_ETC___d1730,
IF_vector_control_112_93_OR_NOT_pba_vector_112_ETC___d1725,
IF_vector_control_112_93_OR_NOT_pba_vector_112_ETC___d1727,
IF_vector_control_116_97_OR_NOT_pba_vector_116_ETC___d1722,
IF_vector_control_120_01_OR_NOT_pba_vector_120_ETC___d1718,
IF_vector_control_124_05_OR_NOT_pba_vector_124_ETC___d1715,
IF_vector_control_128_09_OR_NOT_pba_vector_128_ETC___d1712,
IF_vector_control_12_93_OR_NOT_pba_vector_12_9_ETC___d1824,
IF_vector_control_16_97_OR_NOT_pba_vector_16_8_ETC___d1819,
IF_vector_control_16_97_OR_NOT_pba_vector_16_8_ETC___d1821,
IF_vector_control_20_01_OR_NOT_pba_vector_20_8_ETC___d1816,
IF_vector_control_24_05_OR_NOT_pba_vector_24_7_ETC___d1812,
IF_vector_control_28_09_OR_NOT_pba_vector_28_7_ETC___d1809,
IF_vector_control_32_13_OR_NOT_pba_vector_32_6_ETC___d1803,
IF_vector_control_32_13_OR_NOT_pba_vector_32_6_ETC___d1805,
IF_vector_control_32_13_OR_NOT_pba_vector_32_6_ETC___d1806,
IF_vector_control_36_17_OR_NOT_pba_vector_36_5_ETC___d1800,
IF_vector_control_40_21_OR_NOT_pba_vector_40_4_ETC___d1796,
IF_vector_control_44_25_OR_NOT_pba_vector_44_4_ETC___d1793,
IF_vector_control_48_29_OR_NOT_pba_vector_48_3_ETC___d1788,
IF_vector_control_48_29_OR_NOT_pba_vector_48_3_ETC___d1790,
IF_vector_control_4_85_OR_NOT_pba_vector_4_06__ETC___d1831,
IF_vector_control_52_33_OR_NOT_pba_vector_52_3_ETC___d1785,
IF_vector_control_56_37_OR_NOT_pba_vector_56_2_ETC___d1781,
IF_vector_control_60_41_OR_NOT_pba_vector_60_1_ETC___d1778,
IF_vector_control_64_45_OR_NOT_pba_vector_64_0_ETC___d1771,
IF_vector_control_64_45_OR_NOT_pba_vector_64_0_ETC___d1773,
IF_vector_control_64_45_OR_NOT_pba_vector_64_0_ETC___d1774,
IF_vector_control_68_49_OR_NOT_pba_vector_68_0_ETC___d1768,
IF_vector_control_72_53_OR_NOT_pba_vector_72_9_ETC___d1764,
IF_vector_control_76_57_OR_NOT_pba_vector_76_9_ETC___d1761,
IF_vector_control_80_61_OR_NOT_pba_vector_80_8_ETC___d1756,
IF_vector_control_80_61_OR_NOT_pba_vector_80_8_ETC___d1758,
IF_vector_control_84_65_OR_NOT_pba_vector_84_7_ETC___d1753,
IF_vector_control_88_69_OR_NOT_pba_vector_88_7_ETC___d1749,
IF_vector_control_8_89_OR_NOT_pba_vector_8_00__ETC___d1827,
IF_vector_control_92_73_OR_NOT_pba_vector_92_6_ETC___d1746,
IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1740,
IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1742,
IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1743;
wire [2 : 0] msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32,
msixTable_serverAdapterB_cnt_3_PLUS_IF_msixTab_ETC___d89;
wire [1 : 0] ab__h18813;
wire NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1015,
NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1315,
NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d931,
NOT_vector_control_100_81_218_AND_pba_vector_1_ETC___d1228,
NOT_vector_control_104_85_230_AND_pba_vector_1_ETC___d1240,
NOT_vector_control_108_89_241_AND_pba_vector_1_ETC___d1251,
NOT_vector_control_112_93_254_AND_pba_vector_1_ETC___d1264,
NOT_vector_control_116_97_265_AND_pba_vector_1_ETC___d1275,
NOT_vector_control_120_01_277_AND_pba_vector_1_ETC___d1287,
NOT_vector_control_124_05_288_AND_pba_vector_1_ETC___d1298,
NOT_vector_control_128_09_304_AND_pba_vector_1_ETC___d1314,
NOT_vector_control_12_93_55_AND_pba_vector_12__ETC___d965,
NOT_vector_control_16_97_68_AND_pba_vector_16__ETC___d978,
NOT_vector_control_20_01_79_AND_pba_vector_20__ETC___d989,
NOT_vector_control_24_05_91_AND_pba_vector_24__ETC___d1001,
NOT_vector_control_28_09_002_AND_pba_vector_28_ETC___d1012,
NOT_vector_control_32_13_016_AND_pba_vector_32_ETC___d1026,