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Commit 1466aa9c authored by Jaco Hofmann's avatar Jaco Hofmann
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Updates BlueDMA and MSIx Interrupt Controller to newest versions

parent 8040311c
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common/ip/BlueDMA/component.xml
View file @ 1466aa9c
......@@ -1063,28 +1063,6 @@
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>IRQ</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>INTERRUPT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>IRQ</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SENSITIVITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.IRQ.SENSITIVITY" spirit:choiceRef="choice_list_99a1d2b9">LEVEL_HIGH</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:addressSpaces>
<spirit:addressSpace>
......@@ -1104,7 +1082,7 @@
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
<spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
<spirit:range spirit:format="long" spirit:resolve="user" spirit:minimum="4096" spirit:rangeType="long">16777216T</spirit:range>
<spirit:range spirit:format="long" spirit:resolve="user" spirit:minimum="4096" spirit:rangeType="long">4096</spirit:range>
<spirit:width spirit:format="long" spirit:resolve="user">64</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
......@@ -1124,7 +1102,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>069857fc</spirit:value>
<spirit:value>ff8a092a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -1140,7 +1118,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>069857fc</spirit:value>
<spirit:value>81bd05da</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -1687,7 +1665,7 @@
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
......@@ -2008,7 +1986,7 @@
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
......@@ -2382,7 +2360,7 @@
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
......@@ -2703,7 +2681,7 @@
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
......@@ -2945,7 +2923,20 @@
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>IRQ</spirit:name>
<spirit:name>IRQ_write</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>IRQ_read</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
......@@ -2960,13 +2951,6 @@
</spirit:ports>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_99a1d2b9</spirit:name>
<spirit:enumeration>LEVEL_HIGH</spirit:enumeration>
<spirit:enumeration>LEVEL_LOW</spirit:enumeration>
<spirit:enumeration>EDGE_RISING</spirit:enumeration>
<spirit:enumeration>EDGE_FALLING</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_list_9d8b0d81</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
......@@ -2977,8 +2961,25 @@
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/SyncFIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:name>constraints/bluedma.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:define>
<spirit:name>processing_order</spirit:name>
<spirit:value>late</spirit:value>
</spirit:define>
</spirit:file>
<spirit:file>
<spirit:name>constraints/bluedma.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:define>
<spirit:name>processing_order</spirit:name>
<spirit:value>late</spirit:value>
</spirit:define>
</spirit:file>
<spirit:file>
<spirit:name>src/FIFO1.v</spirit:name>
......@@ -2997,21 +2998,17 @@
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/mkBlueDMA.v</spirit:name>
<spirit:name>src/SyncFIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/mkBlueDMAVivado.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_abab4df6</spirit:userFileType>
<spirit:userFileType>CHECKSUM_f4b809fa</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/SyncFIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/FIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
......@@ -3029,7 +3026,7 @@
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/mkBlueDMA.v</spirit:name>
<spirit:name>src/SyncFIFO1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
......@@ -3057,9 +3054,25 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">virtex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">qvirtex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">qkintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">qkintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">aartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">qartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">qzynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">azynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">spartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">virtexu</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">virtexuplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintexuplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintexu</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
......@@ -3067,19 +3080,19 @@
<xilinx:displayName>BlueDMA</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-10T16:46:33Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2018-01-30T15:28:45Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9aa6aa20"/>
<xilinx:xilinxVersion>2017.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="00a31e8a"/>
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c93d048c"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="8523f8a5"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1bb46e31"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="0f1ff220"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5e367912"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="d0fc19af"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="4a3aac11"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
common/ip/BlueDMA/constraints/bluedma.tcl 0 → 100644
View file @ 1466aa9c
##
## set properties to help out clock domain crossing analysis
##
foreach pat {"reset_hold_reg[*]" "sGEnqPtr*_reg[*]" "dGDeqPtr*_reg[*]" "sSyncReg*_reg[*]" "dSyncReg*_reg[*]" "dEnqPtr*_reg[*]"} {
set cells [get_cells -hier $pat]
if {[llength $cells] > 0} {
puts "ASYNC_REG $cells"
set_property ASYNC_REG 1 $cells
}
}
common/ip/BlueDMA/constraints/bluedma.xdc 0 → 100644
View file @ 1466aa9c
##
## set properties to help out clock domain crossing analysis
##
set s_clk [get_clocks -of_objects [get_ports -scoped_to_current_instance m32_axi_aclk]]
set m_clk [get_clocks -of_object [get_ports -scoped_to_current_instance m64_axi_aclk]]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance m32_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance m64_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $s_clk]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance m64_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance m32_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $m_clk]
set g_clk [get_clocks -of_objects [get_ports -scoped_to_current_instance s_axi_aclk]]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance m32_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $s_clk]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance m32_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $g_clk]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance m64_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $m_clk]
set_max_delay -from [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports -scoped_to_current_instance m64_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $g_clk]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *reset_hold_reg*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *sGEnqPtr*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dGDeqPtr*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *sSyncReg*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dSyncReg*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dEnqPtr*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dEnqToggle*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dDeqToggle*}] {IS_SEQUENTIAL}]
set_false_path -through [get_ports -scoped_to_current_instance -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hier -filter {NAME =~ *dNotEmpty*}] {IS_SEQUENTIAL}]
\ No newline at end of file
common/ip/BlueDMA/src/FIFO1.v
View file @ 1466aa9c
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
common/ip/BlueDMA/src/FIFO2.v
View file @ 1466aa9c
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
common/ip/BlueDMA/src/SyncFIFO.v
View file @ 1466aa9c
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 33367 $
// $Date: 2014-02-18 17:46:14 +0000 (Tue, 18 Feb 2014) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
common/ip/BlueDMA/src/SyncFIFO1.v
View file @ 1466aa9c
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
common/ip/BlueDMA/src/mkBlueDMA.v deleted 100644 → 0
View file @ 8040311c
This diff is collapsed.
common/ip/BlueDMA/src/mkBlueDMAVivado.v
View file @ 1466aa9c
This diff is collapsed.
common/ip/MSIXIntrCtrl/component.xml
View file @ 1466aa9c
......@@ -427,7 +427,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>e07e9e3a</spirit:value>
<spirit:value>ba3c4982</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -443,7 +443,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>e07e9e3a</spirit:value>
<spirit:value>062ac467</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -1248,6 +1248,16 @@
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>constraints/msix_intr_ctrl.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:define>
<spirit:name>processing_order</spirit:name>
<spirit:value>late</spirit:value>
</spirit:define>
</spirit:file>
<spirit:file>
<spirit:name>src/BRAM2BE.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
......@@ -1267,7 +1277,7 @@
<spirit:file>
<spirit:name>src/mkMSIXIntrCtrl.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_f02cbad3</spirit:userFileType>
<spirit:userFileType>CHECKSUM_8ffb020d</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
......@@ -1313,9 +1323,25 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
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<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Pre-Production">kintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">qkintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">qkintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">aartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">qartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">qzynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">azynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">spartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">virtexu</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">virtexuplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintexuplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintexu</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
......@@ -1323,19 +1349,19 @@
<xilinx:displayName>MSIXIntrCtrl</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-07T08:36:48Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2018-01-30T15:21:42Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="a9103989"/>
<xilinx:xilinxVersion>2017.2</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f94240"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="2b2da2c0"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ecf6481e"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5de90130"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="19368f77"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="4b2b81b7"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1be99b86"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
common/ip/MSIXIntrCtrl/constraints/msix_intr_ctrl.xdc 0 → 100644
View file @ 1466aa9c
set_false_path -through [get_ports -scoped_to_current_instance interrupt*]
common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc deleted 100644 → 0
View file @ 8040311c
set_false_path -through [get_pins system_i/InterruptControl/msix_intr_ctrl/interrupt*]
common/ip/MSIXIntrCtrl/src/FIFO1.v
View file @ 1466aa9c
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
common/ip/MSIXIntrCtrl/src/FIFO2.v
View file @ 1466aa9c
......@@ -19,8 +19,8 @@
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
......
common/ip/MSIXIntrCtrl/src/mkMSIXIntrCtrl.v
View file @ 1466aa9c
This diff is collapsed.
platform/vc709/module/pcie_device.c
View file @ 1466aa9c
......@@ -137,7 +137,11 @@ static int register_intr_handler(struct pci_dev *pdev, int c)
err = request_irq(pci_irq_vector(pdev, c), intr_handler_dma, IRQF_EARLY_RESUME, FFLINK_PCI_NAME, pdev);
}
if (c == 1 || c == 2 || c == 3) err = -2;
if (c == 1) {
err = request_irq(pci_irq_vector(pdev, c), intr_handler_dma, IRQF_EARLY_RESUME, FFLINK_PCI_NAME, pdev);
}
if (c == 2 || c == 3) err = -2;
switch (c) {
case 4: err = request_irq(pci_irq_vector(pdev, c), intr_handler_user_0, IRQF_EARLY_RESUME, FFLINK_PCI_NAME, pdev); break;
......
platform/vc709/plugins/blue-dma.tcl
View file @ 1466aa9c
......@@ -11,24 +11,6 @@ namespace eval blue_dma {
dict set tapasco::ip::stdcomps dualdma vlnv $vlnv
}
}
proc set_constraints {{args {}}} {
if {[tapasco::is_feature_enabled "BlueDMA"]} {
puts "Adding false path constraints for BlueDMA"
set constraints_fn "[get_property DIRECTORY [current_project]]/bluedma.xdc"
set constraints_file [open $constraints_fn w+]
puts $constraints_file {set s_clk [get_clocks -of_objects [get_ports m32_axi_aclk]]}
puts $constraints_file {set m_clk [get_clocks -of_objects [get_ports m64_axi_aclk]]}
puts $constraints_file {set g_clk [get_clocks -of_objects [get_ports s_axi_aclk]]}
puts $constraints_file {set_clock_groups -asynchronous -group $g_clk -group $s_clk}
puts $constraints_file {set_clock_groups -asynchronous -group $g_clk -group $m_clk}
puts $constraints_file {set_clock_groups -asynchronous -group $m_clk -group $s_clk}
close $constraints_file
read_xdc -cells {system_i/Memory/dual_dma} $constraints_fn
}
return {}
}
}
tapasco::register_plugin "platform::blue_dma::blue_dma" "post-init"
tapasco::register_plugin "platform::blue_dma::set_constraints" "post-synth"
platform/vc709/plugins/msix-intr-ctrl.tcl deleted 100644 → 0
View file @ 8040311c
namespace eval msix_intr_ctrl {
proc simplify_routing {} {
read_xdc -unmanaged "$::env(TAPASCO_HOME)/common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc"
}
}
tapasco::register_plugin "platform::msix_intr_ctrl::simplify_routing" "post-synth"
platform/vc709/vc709.tcl
View file @ 1466aa9c
......@@ -81,7 +81,8 @@ namespace eval platform {
set aclk [tapasco::subsystem::get_port "host" "clk"]
set ic_aresetn [tapasco::subsystem::get_port "host" "rst" "interconnect"]
set p_aresetn [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"]
set dma_irq [create_bd_pin -type "intr" -dir I "dma_irq"]
set dma_irq_read [create_bd_pin -type "intr" -dir I "dma_irq_read"]
set dma_irq_write [create_bd_pin -type "intr" -dir I "dma_irq_write"]
set msix_fail [create_bd_pin -dir "I" "msix_fail"]
set msix_sent [create_bd_pin -dir "I" "msix_sent"]
......@@ -111,8 +112,9 @@ namespace eval platform {
connect_bd_net $msix_enable [get_bd_pin -of_objects $msix_intr_ctrl -filter {NAME == "cfg_interrupt_msix_enable"}]
connect_bd_net $msix_mask [get_bd_pin -of_objects $msix_intr_ctrl -filter {NAME == "cfg_interrupt_msix_mask"}]
connect_bd_net $dma_irq [get_bd_pin -of_objects $irq_concat_ss -filter {NAME == "In0"}]
puts "Unused Interrupts: 1, 2, 3 are tied to 0"
connect_bd_net $dma_irq_read [get_bd_pin -of_objects $irq_concat_ss -filter {NAME == "In0"}]
connect_bd_net $dma_irq_write [get_bd_pin -of_objects $irq_concat_ss -filter {NAME == "In1"}]
puts "Unused Interrupts: 2, 3 are tied to 0"
connect_bd_net [get_bd_pin -of_object $irq_unused -filter {NAME == "dout"}] [get_bd_pin -of_objects $irq_concat_ss -filter {NAME == "In1"}]
for {set i 0} {$i < 4} {incr i} {
set port [create_bd_pin -from 127 -to 0 -dir I -type intr "intr_$i"]
......@@ -156,7 +158,8 @@ namespace eval platform {
set ddr_p_aresetn [tapasco::subsystem::get_port "mem" "rst" "peripheral" "resetn"]
set design_p_aresetn [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"]
set irq [create_bd_pin -type "intr" -dir "O" "dma_irq"]
set irq_read [create_bd_pin -type "intr" -dir "O" "dma_irq_read"]
set irq_write [create_bd_pin -type "intr" -dir "O" "dma_irq_write"]
# create instances of cores: MIG core, dual DMA, system cache
set mig [create_mig_core "mig"]
......@@ -236,7 +239,12 @@ namespace eval platform {
}
# connect IRQ
connect_bd_net [get_bd_pins dual_dma/IRQ] $irq
if {[tapasco::is_platform_feature_enabled "BlueDMA"]} {
connect_bd_net [get_bd_pins dual_dma/IRQ_read] $irq_read
connect_bd_net [get_bd_pins dual_dma/IRQ_write] $irq_write
} else {
connect_bd_net [get_bd_pins dual_dma/IRQ] $irq_read
}
}
proc create_subsystem_host {} {
......
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