Commit 1502a621 authored by Carsten Heinz's avatar Carsten Heinz
Browse files

Make status core compatible with Versal

parent 661fa246
......@@ -539,4 +539,8 @@ namespace eval tapasco {
puts "Number of slots is hard coded as 128 right now"
return 128
}
proc is_versal {} {
return [string match "versal*" [get_property FAMILY [get_parts -of_objects [current_project]]]]
}
}
......@@ -62,6 +62,7 @@ dict set stdcomps axis_arbiter vlnv "esa.informatik.tu-darmstadt.de:
dict set stdcomps aws_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:AWSIntrCtrl:1.0"
dict set stdcomps axi_bram_ctrl vlnv "xilinx.com:ip:axi_bram_ctrl"
dict set stdcomps bram_ctrl vlnv "xilinx.com:ip:blk_mem_gen"
dict set stdcomps versal_emb_mem_gen vlnv "xilinx.com:ip:emb_mem_gen"
dict set stdcomps axi_gpio vlnv "xilinx.com:ip:axi_gpio:2.0"
dict set stdcomps axioffset_hbm vlnv "esa.informatik.tu-darmstadt.de:user:AXIOffsetHBM:1.0"
dict set stdcomps sume_clock_prog vlnv "esa.informatik.tu-darmstadt.de:user:SumeClockProgrammer:1.0"
......
......@@ -430,7 +430,11 @@ namespace eval ::tapasco::ip {
puts " IDs : $ids"
# create the IP core
set base [tapasco::ip::create_bram_ctrl "${name}_base"]
if {[tapasco::is_versal]} {
set base [tapasco::ip::create_versal_emb_mem_gen "${name}_base"]
} else {
set base [tapasco::ip::create_bram_ctrl "${name}_base"]
}
set axi [tapasco::ip::create_axi_bram_ctrl $name]
set_property -dict [list CONFIG.DATA_WIDTH {64} \
......@@ -469,7 +473,12 @@ namespace eval ::tapasco::ip {
}
puts "Wrote COE file to ${outfile}"
set_property -dict [list CONFIG.Memory_Type {Single_Port_ROM} \
if {[tapasco::is_versal]} {
set mem_type {Single_Port_RAM}
} else {
set mem_type {Single_Port_ROM}
}
set_property -dict [list CONFIG.Memory_Type $mem_type \
CONFIG.Load_Init_File {true} \
CONFIG.EN_SAFETY_CKT {false} \
CONFIG.Coe_File $outfile] [get_bd_cells -filter "NAME == ${name}_base"]
......
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