Commit 153bcf07 authored by Jens Korinth's avatar Jens Korinth
Browse files

Implement --skipEvaluation option for imports

parent 68639fbe
......@@ -49,9 +49,11 @@ object Import {
* @param id Kernel ID.
* @param t Target Architecture + Platform combination to import for.
* @param acc Average clock cycle count for a job execution on the PE (optional).
* @param skipEval Do not perform out-of-context synthesis for resource estimation (optional).
* @param cfg Implicit [[base.Configuration]].
**/
def apply(zip: Path, id: Kernel.Id, t: Target, acc: Option[Int])(implicit cfg: Configuration): Boolean = {
def apply(zip: Path, id: Kernel.Id, t: Target, acc: Option[Int], skipEval: Option[Boolean])
(implicit cfg: Configuration): Boolean = {
// get VLNV from the file
val vlnv = VLNV.fromZip(zip)
logger.trace("found VLNV in zip " + zip + ": " + vlnv)
......@@ -68,18 +70,20 @@ object Import {
// write core.json to output directory (as per config)
val p = cfg.outputDir(c, t).resolve("ipcore").resolve("core.json")
importCore(c, t, p, vlnv)
importCore(c, t, p, vlnv, skipEval)
}
/**
* Imports the IP-XACT .zip to the default path structure (ipcore/) and performs
* out-of-context synthesis (if no report from HLS was found).
* out-of-context synthesis (if no report from HLS was found and skipEval was not set).
* @param c Core description.
* @param t Target platform and architecture.
* @param p Output path for core description file.
* @param skipEval Skip out-of-context synthesis step (optional).
* @param cfg Implicit [[Configuration]].
**/
private def importCore(c: Core, t: Target, p: Path, vlnv: VLNV)(implicit cfg: Configuration): Boolean = {
private def importCore(c: Core, t: Target, p: Path, vlnv: VLNV, skipEval: Option[Boolean])
(implicit cfg: Configuration): Boolean = {
Files.createDirectories(p.getParent)
logger.trace("created output directories: {}", p.getParent.toString)
......@@ -103,7 +107,7 @@ object Import {
}
// evaluate the ip core and store the report with the link
val res = evaluateCore(c, t)
val res = skipEval.getOrElse(false) || evaluateCore(c, t)
// write core.json
logger.debug("writing core description: {}", p.toString)
......
......@@ -50,7 +50,7 @@ class CorePanelController extends {
val path = java.nio.file.Paths.get(ImportFileChooser.selectedFile.toString)
val tasks = for {
t <- Job.job.targets
} yield new ImportTask(path, t, 1, None, b => cores.update())(Config.configuration) // FIXME missing ID, clock cycles
} yield new ImportTask(path, t, 1, b => cores.update())(Config.configuration) // FIXME missing ID, clock cycles, skip eval
tasks foreach (TaskScheduler.apply _)
}
}
......
......@@ -52,7 +52,7 @@ private object BulkImport extends Executor[BulkImportJob] {
a <- j.architectures
p <- j.platforms
t = Target(a, p)
} yield new ImportTask(j.zipFile, t, j.id, j.averageClockCycles, _ => signal.release())(cfg)
} yield new ImportTask(j.zipFile, t, j.id, _ => signal.release(), j.averageClockCycles)(cfg)
importTasks foreach { tsk.apply _ }
......
......@@ -52,7 +52,7 @@ protected object HighLevelSynthesis extends Executor[HighLevelSynthesisJob] {
if (avgCC.isEmpty && k.testbenchFiles.length > 0) {
logger.warn("executed HLS with co-sim for {}, but no co-simulation report was found", k)
}
Some(new ImportTask(zip, t, k.id, avgCC, _ => signal.release())(cfg))
Some(new ImportTask(zip, t, k.id, _ => signal.release(), avgCC)(cfg))
}
case _ => None
}
......
......@@ -51,7 +51,7 @@ object Import extends Executor[ImportJob] {
val tasks = jobs map { case (j, t) =>
val avgCC = FileAssetManager.reports.cosimReport(VLNV.fromZip(j.zipFile).name, t) map (_.latency.avg)
new ImportTask(j.zipFile, t, j.id, avgCC, _ => signal.release())(cfg)
new ImportTask(j.zipFile, t, j.id, _ => signal.release(), avgCC, j.skipEvaluation)(cfg)
}
tasks foreach { tsk.apply _ }
......
......@@ -36,12 +36,18 @@ import java.nio.file.Path
* @param zip Path to the .zip file.
* @param t Target to import core for.
* @param id Id of the kernel this core implements.
* @param averageClockCycles Clock cycle count in an average execution of the core (optional).
* @param onComplete Callback function on completion of the task.
* @param cfg TPC Configuration (implicit).
* @param averageClockCycles Clock cycle count in an average execution of the core (optional).
* @param skipEvaluation Do not perform out-of-context synthesis for resource estimates, if true (optional).
* @param cfg TaPaSCo [[Configuration]] (implicit).
**/
class ImportTask(val zip: Path, val t: Target, val id: Kernel.Id, val averageClockCycles: Option[Int],
val onComplete: Boolean => Unit)(implicit val cfg: Configuration) extends Task with LogTracking {
class ImportTask(val zip: Path,
val t: Target,
val id: Kernel.Id,
val onComplete: Boolean => Unit,
val averageClockCycles: Option[Int] = None,
val skipEvaluation: Option[Boolean] = None)
(implicit val cfg: Configuration) extends Task with LogTracking {
private implicit val logger = de.tu_darmstadt.cs.esa.tapasco.Logging.logger(getClass)
private val name = try { Some(VLNV.fromZip(zip).name) } catch { case _: Throwable => None }
private lazy val _logFile = cfg.outputDir(name.get, t).resolve("%s.%s.import.log".format(
......@@ -53,9 +59,7 @@ class ImportTask(val zip: Path, val t: Target, val id: Kernel.Id, val averageClo
val appender = LogFileTracker.setupLogFileAppender(_logFile.toString)
logger.trace("current thread name: {}", Thread.currentThread.getName())
logger.info(description)
logger.debug("debug: " + description)
logger.trace("trace: " + description)
val result = activity.Import(zip, id, t, averageClockCycles)
val result = activity.Import(zip, id, t, averageClockCycles, skipEvaluation)
LogFileTracker.stopLogFileAppender(appender)
result
}
......
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