Commit 17f0d672 authored by Jens Korinth's avatar Jens Korinth
Browse files

Squash-merge 'pe-local-memories' feature

Squashed commit of the following:

commit 13fdb518
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Mar 2 22:34:38 2018 +0100

    Recognize Tcl errors in Vivado logs

commit 90b74d7c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Mar 2 15:04:11 2018 +0100

    Make ILA debug feature generic for all platforms

    * only get_debug_nets depends on the platform
    * rest moved to platform/common/plugins
    * supporting platforms implement wrapper plugin, see
      platform/zynq/plugins/debug.tcl
    * fixed several other issues, e.g., clock selection
    * closes #132 - no master compositions

commit cc8a2df2
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Mar 2 10:57:10 2018 +0100

    Bugfixes in Debug feature

    * added ILA implementation feature on VC709
    * fixed SILA implementation feature on axi4mm
    * fixed renamed post-bd event to pre-wrapper in several plugins
    * fixed wrong VLNV for SILA in 2017.4

commit 11efaf52
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Mar 1 17:16:13 2018 +0100

    Added another limitation to pe-local-memories.md

commit c3fc21fa
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Mar 1 17:11:55 2018 +0100

    Typo

commit 78bf5409
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Mar 1 17:08:06 2018 +0100

    Software support for PE-local memories

    * alpha version of software API: supports PE-local memories in transfers
      and job executions
    * see documentation/pe-local-memories.md for more details

commit 7a8b1f16
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Mar 1 11:08:53 2018 +0100

    Implement ultra-primitive first-fit memory allocator

    * does not actually manage memory, only addresses
    * for use in pe local memories

commit 1b5c8286
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Feb 28 14:09:55 2018 +0100

    Implement top-level API for job-attached transfers

    * top-level API is tapasco_device_job_set_transfer, which in turn uses
      tapasco_job level functions

commit 277dd3dd
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Feb 28 14:09:55 2018 +0100

    Implement API for job-attached transfers

    * tapasco_jobs now define functions to attach memory transfers to jobs
      to be executed just-in-time before execution by the scheduler
    * scheduler supports new constructs: if transfer length is marked > 0
      for an argument, it will allocate memory, transfer the data and
      updated the argument with the corresponding handle, as well as copy
      back and free the memory after return
    * no top-level API is implemented yet, only tapasco_job level
    * no malloc for local memories is implemented yet

commit 37972c5a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 18:23:11 2018 +0100

    Bugfix in common_2017.4.tcl: Did not source common_ip

commit 1c136d11
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 18:17:46 2018 +0100

    Fix bug in O0 of evaluate

commit 8dc75212
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 18:08:33 2018 +0100

    Add common/ip to evaluate projects

commit 971e3874
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 17:37:07 2018 +0100

    Deactivate debug logging

commit ccd8a4f3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 17:32:23 2018 +0100

    Reactivate warnings in evaluate logs

commit d660cb7a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 15:19:11 2018 +0100

    Another fix for construct_address_map

    * must also query master for expected base address

commit d54ced58
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 15:11:17 2018 +0100

    Fix bug in construct_address_map

    * must take into account range of both slave and master, and only use
      lesser one
    * fix was necessary for MicroBlaze

commit 56b77300
Merge: a2ce13bb 76275656
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Feb 27 12:58:42 2018 +0100

    Merge branch '2018.1' into pe-local-memories

commit a2ce13bb
Merge: cd079c31 3d912101
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Feb 8 10:49:31 2018 +0100

    Merge branch '2018.1' of git:tapasco/tapasco into pe-local-memories

commit cd079c31
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Fri Feb 2 15:17:30 2018 +0100

    Revert "Recognize separate IAR status and IAR ACK registers"

        * Turns out Vivado changed the interrupt ack register back to 0x0c

    This reverts commit e63deaf5.

commit e63deaf5
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Fri Feb 2 10:57:58 2018 +0100

    Recognize separate IAR status and IAR ACK registers

commit 4f219431
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Thu Feb 1 15:51:22 2018 +0100

    Properly align interrupts for VC709

commit a39a13f8
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 21:31:18 2018 +0100

    Reverts back to old dual_dma.xdc to fix problems with new one

commit db7698aa
Merge: bb36af6d c04932d9
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 30 19:03:50 2018 +0100

    Merge remote-tracking branch 'origin/BlueDMA_Updates' into pe-local-memories

commit bb36af6d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 30 18:54:30 2018 +0100

    Updated PyNQ benchmark on 2017.4

commit c04932d9
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 18:29:29 2018 +0100

    Fixes MSIx address map

commit f75533a1
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 17:51:47 2018 +0100

    Fixes PCIe clock location constraint

commit 6416ab50
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 17:49:21 2018 +0100

    Fixes DualDMA constraint application

commit 153716a3
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 16:50:25 2018 +0100

    Fixes errors introduced by new connection scheme and new BlueDMA

commit 1466aa9c
Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
Date:   Tue Jan 30 16:39:44 2018 +0100

    Updates BlueDMA and MSIx Interrupt Controller to newest versions

commit 8040311c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 30 12:55:37 2018 +0100

    Zynq: Fix zero master PE compositions

commit b426ec6c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 19:39:45 2018 +0100

    Fix for zero masters on PEs

commit dcc6c418
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 17:04:51 2018 +0100

    Squashed commit of the following:

    commit 802a3eea
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:58:22 2018 +0100

        CI: Reactivate everything, with new compose-features stage

    commit d0fb3e37
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:55:43 2018 +0100

        F'in yml

    commit 6c8e648d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:53:22 2018 +0100

        YML debugging

    commit 155ed589
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:51:22 2018 +0100

        YML debugging

    commit 4a6408b6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:49:36 2018 +0100

        YML debugging

    commit 1b09ffb8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:47:22 2018 +0100

        Distinguish compose with and without features in jobs

    commit ec2af8ed
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:43:24 2018 +0100

        Reactivate compose jobs

    commit 09d289a8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 12:41:17 2018 +0100

        Deactivate all jobs but compose without features

    commit 40c7cba6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 11:34:15 2018 +0100

        Fix potential hanging LogTrackingFileWatcher in EvaluateIP

    commit f31d740c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 11:19:20 2018 +0100

        Temporarily increase logging of file watcher (again)

    commit f12a9074
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 10:45:05 2018 +0100

        Fix truncated log output in verbose mode

        * when an activity exits quickly with an error, verbose mode would often
          omit the most important last few lines of the log
        * reason: flushing the data to disk takes longer than for the Tapasco
          threads to die, thus LogTrackingFileWatcher exits before lines appear
        * workaround: when both waitingFor and files are empty, MultiFileWatcher
          now waits one more iteration before exiting, which seems to suffice

    commit f9148c81
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 10:22:09 2018 +0100

        Squashed commit of the following:

        commit d3245516
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:19:19 2018 +0100

            Closes #149 - Zedboard Synthesis fails for 2017.3 and 2017.4

            * improved sys clock detection by checking available interfaces via
              get_board_part_interfaces, instead of trying sys_diff_clock first
            * also removed second warning when get_bd_pins returns nothing
            * removed old, unused platform code

        commit 9a0fb9b0
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:18:03 2018 +0100

            Use Arty-Z7-20 board file from Digilent for PyNQ

            * contains the manually set top.xdc directives
            * identical to Pynq, except for peripheral components

        commit f6a25afc
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:16:28 2018 +0100

            Update board definition for zedboard

            * Digilent has newer def of ZedBoard, using that automatically now
            * imported via MYVIVADO / XILINX_PATH env vars

        commit a29aa6cc
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:14:39 2018 +0100

            Fix minor bug in PS7 instantiation routine

        commit c782eadc
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Thu Jan 25 10:13:58 2018 +0100

            Remove 2016.4 specific code from design.master.tcl.template

    commit f873c47b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 25 08:23:54 2018 +0100

        Closes #137 for HLS

    commit 88259aa0
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 17:01:44 2018 +0100

        Activate pipelines on branch gitlab-ci

    commit d09278de
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 16:58:38 2018 +0100

        Deactivate sbt-prepare on all except master and 20xx.x branches

    commit 9df2a6a6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 16:54:40 2018 +0100

        Another fix regarding precision_counter

    commit 30f9ac5b
    Merge: c0ed8ed6 fc930ec8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 16:53:33 2018 +0100

        Merge branch 'pe-local-memories' of git:tapasco/tapasco into gitlab-ci

    commit c0ed8ed6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 16:52:05 2018 +0100

        Remove precision_counter from composition

        * caches are not always available, so precision_counter is not
          available, causing runs to fail
        * annoying, removed precision_counter for now

    commit 35b46901
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 15:56:50 2018 +0100

        Restrict CI pipelines to master and 20xx.x branches

    commit 0a0dc675
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 15:45:13 2018 +0100

        Activate verbose output in CI HLS jobs

    commit 240ad939
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 15:33:48 2018 +0100

        Test of generated yml

    commit 4f684b2a
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 15:33:32 2018 +0100

        Remove support for Vivado 2016.4

    commit be0a4b94
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 14:54:25 2018 +0100

        Pull tapasco-status 1.21

        * Chisel-generated Verilog is flattened into single module to avoid
          Verilog name conflicts

    commit d668d82b
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 14:52:30 2018 +0100

        Fix bug in address map construction

        * internal master-slave connections do not appear in get_address_map
        * so their segments were not mapped, resulting in errors, e.g., for DMA
        * fix: when address map does not contain interfaces, it will try to
          deduce range and offset from properties of the segment instead of
          failing

    commit 86b53707
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 24 13:45:58 2018 +0100

        Squashed commit of the following:

        commit 39e7a1cb
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Wed Jan 24 13:44:20 2018 +0100

            Bugfix in ZC706 fancontrol plugin

        commit 6a06399b
        Author: Lukas Sommer <lukas.sommer.mail@gmail.com>
        Date:   Wed Jan 24 12:39:49 2018 +0100

            Moved filter condition for active-high resets to correct command;

        commit cba13f81
        Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
        Date:   Wed Jan 24 11:28:40 2018 +0100

            Arch: Fix bug in PE reset connections

    commit c830c899
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 09:00:20 2018 +0100

        Improve locking behavior of MultiFileWatcher

    commit 58542825
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 08:22:55 2018 +0100

        Reactivate verbose mode in compose

    commit b97700d3
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 06:31:23 2018 +0100

        Remove --maxTasks from HLS and Import

    commit 25c503b6
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 06:25:15 2018 +0100

        Deactivate resource logging, increase tasks for HLS and import

    commit ac61a13d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 06:19:29 2018 +0100

        Remove tapasco-status building from sbt-prepare job

    commit 4c6f2657
    Merge: 3691ea58 d1f36ab4
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Tue Jan 23 06:15:50 2018 +0100

        Merge branch 'pe-local-memories' of esagitlab:tapasco/tapasco into gitlab-ci

    commit 3691ea58
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Jan 22 14:33:00 2018 +0100

        Change .gitlab-ci.yml to use new maxTasks param

    commit ea7c3934
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Mon Jan 22 14:30:06 2018 +0100

        Closes #147 - Implement maxTasks option

        * now supports --maxTasks command line / JSON option to limit the number
          of parallel tasks executed by TaPaSCo

    commit f8d090ae
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Sun Jan 21 15:32:51 2018 +0100

        Temporarily increase logging to debug OOM problems

    commit 3cb861b2
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Sun Jan 21 12:46:13 2018 +0100

        Limit threads to 1 to remove oom errors

    commit c02630a5
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 18:36:37 2018 +0100

        Adds artifact passing between hls and compose

    commit e2c63695
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 18:02:27 2018 +0100

        Changes for shared caches

    commit 82d85c69
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 17:11:36 2018 +0100

        Try to cache as much as possible

    commit 36be0ac0
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 17:04:08 2018 +0100

        Removes /cache

    commit 6a046f78
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 17:03:27 2018 +0100

        Adds cache_global

    commit fce5833e
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 17:00:42 2018 +0100

        Adds /opt/cad ls for debugging

    commit 0bb7f526
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 16:52:50 2018 +0100

        Adds cache test

    commit 5e410f65
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 16:24:17 2018 +0100

        Removes -v so tapasco finishes

    commit 532b1ba1
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 16:10:45 2018 +0100

        Reverts changes to default image

    commit 25d70ece
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 16:09:42 2018 +0100

        Replaces _JAVA_OPTIONS with SBT_OPTS

            - _JAVA_OPTIONS seems to annoy Vivado HLS and results in random
            crashes

    commit b1bbfe5f
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 14:48:33 2018 +0100

        Compile only one platform for hls

    commit 90adf995
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 14:27:31 2018 +0100

        He said I should add an s

    commit 16664088
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 14:26:19 2018 +0100

        Adds artifact for hls builds

    commit 53f0ae16
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 13:18:53 2018 +0100

        Mkaes hls verbose for debugging

    commit 2becdf3c
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 13:03:15 2018 +0100

        Removes space (and time)

    commit 3a444c26
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 12:03:51 2018 +0100

        Adds check for cache success

    commit cd75f301
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 12:01:16 2018 +0100

        Checks if vivado is included properly

    commit 425b8e98
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 11:48:36 2018 +0100

        Changes sbt-prepare cache policy to push

    commit c2f3b5ac
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 11:47:09 2018 +0100

        Replaces artifacts with cache

            - For now only sbt-prepare is shared for further jobs
            - There should be further sharing between Import and Compose

    commit b2b2d9b6
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Fri Jan 19 10:52:51 2018 +0100

        Revert "Fixes #145 - Building status core fails"

        This reverts commit 32047b00.
        The error this commit fixes was already fixed in a new Dockerfile
        version.

    commit 32047b00
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Fri Jan 19 10:40:58 2018 +0100

        Fixes #145 - Building status core fails

    commit 55718f4f
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 17:42:33 2018 +0100

        Removes import as dependency for compose

    commit 89b6f957
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 17:23:25 2018 +0100

        Reduces artifact size by compressing them

    commit 17a28552
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 16:06:44 2018 +0100

        Source Vivado

            For whatever reason .bashrc is not evaluated...

    commit 2cd05d74
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 15:49:46 2018 +0100

        Revert back to targetted artifacts because of size constraints

    commit fb4284aa
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 15:36:41 2018 +0100

        Get all untracked files for prepare stage

    commit 2f87a5f7
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 15:25:29 2018 +0100

        Bin is needed as artifact as well

    commit 29b4cd38
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 15:07:22 2018 +0100

        Limit artifacts to .ivy2 and .sbt

    commit 5524d39a
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 14:55:06 2018 +0100

        Adapts import-template to new format

    commit c53313a0
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Thu Jan 18 14:52:57 2018 +0100

        Used tapasco image and artifact sbt

    commit 7fd62db1
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:58:10 2018 +0100

        Implement import task as pipeline stage

    commit 6e9c33a9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:51:34 2018 +0100

        Improve logging in Zynq platform Tcl

    commit e1758dbb
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:51:02 2018 +0100

        Improve logging in platform common Tcl

    commit 090f4481
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:50:32 2018 +0100

        Improve logging in tapasco::ip

    commit a6e9559d
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:49:58 2018 +0100

        Activate PE-local memory capability by default

    commit e3682565
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 13:49:40 2018 +0100

        Bugfix in Arch address map for unconnected masters

    commit b8b5dd0a
    Merge: dd6ac83b 8d677bb7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 07:59:19 2018 +0100

        Pull tapasco-status

        Merge commit '8d677bb7' into gitlab-ci

    commit 8d677bb7
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Thu Jan 18 07:58:18 2018 +0100

        Squashed 'common/ip/tapasco_status/' changes from e209f949..3fd53e7

        3fd53e7 Pull chisel-axi
        41e37e7 Squashed 'axi/' changes from b8f4c554..01fad68
        88624e0 Pull chisel-packaging
        872f551 Squashed 'packaging/' changes from 134b2f62..c22243b
        f94b6de3 Remove caching of ivy repo from pipeline
        43c331dc Pull chisel-axiutils
        5937e2aa Implement cap0 bitfield
        26d61dd6 Bugfix in pipeline
        1030ffe5 Cache ivy2 repo in pipeline builds
        14876b2e Implement support for capability field in Status Core
        2a3e6856 Fix removed '<<=' sbt operator
        bccc8a73 Run sbt test in GitLab pipeline
        17e1a3a7 Fix bug concerning empty slots
        5a089419 Ignore compiled python scripts in .gitignore
        0f0a2d84 Update packaging to GitHub-version of Chisel3
        a162cfae Update miscutils to GitHub-version of Chisel3
        f0265156 Remove ununsed Scalactic dep
        d146b992 Rename RegisterFile saxi port to s_axi

        git-subtree-dir: common/ip/tapasco_status
        git-subtree-split: 3fd53e7038ab7e1ff485eee94c3516f72b9604ea

    commit dd6ac83b
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 21:31:34 2018 +0100

        Adds verbose flag for compose debugging

    commit d5e9bc89
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 21:06:26 2018 +0100

        Fixes job naming in yaml

    commit 9b9304ee
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 21:04:59 2018 +0100

        Use artifacts to avoid reevaluation

    commit fd6843ad
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 20:45:10 2018 +0100

        Removes verbose flag to avoid lock ups

    commit 23f78ad7
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 20:12:12 2018 +0100

        Fixes gitlab-ci with Centos7

    commit 4c73c789
    Author: Jaco Hofmann <hofmann@esa.tu-darmstadt.de>
    Date:   Wed Jan 17 19:03:03 2018 +0100

        Change image type to centos

    commit 0b823caa
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 18:22:30 2018 +0100

        Implement stages and HLS

    commit 8e810c8c
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:33:51 2018 +0100

        Fix

    commit e34de5b8
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:32:18 2018 +0100

        Fix

    commit 0dbd2a57
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:23:07 2018 +0100

        Fix

    commit 408774c9
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:19:22 2018 +0100

        Fix setup script

    commit 38820724
    Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
    Date:   Wed Jan 17 16:16:08 2018 +0100

        Implement automated regression tests

commit d3245516
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:19:19 2018 +0100

    Closes #149 - Zedboard Synthesis fails for 2017.3 and 2017.4

    * improved sys clock detection by checking available interfaces via
      get_board_part_interfaces, instead of trying sys_diff_clock first
    * also removed second warning when get_bd_pins returns nothing
    * removed old, unused platform code

commit 9a0fb9b0
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:18:03 2018 +0100

    Use Arty-Z7-20 board file from Digilent for PyNQ

    * contains the manually set top.xdc directives
    * identical to Pynq, except for peripheral components

commit f6a25afc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:16:28 2018 +0100

    Update board definition for zedboard

    * Digilent has newer def of ZedBoard, using that automatically now
    * imported via MYVIVADO / XILINX_PATH env vars

commit a29aa6cc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:14:39 2018 +0100

    Fix minor bug in PS7 instantiation routine

commit c782eadc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:13:58 2018 +0100

    Remove 2016.4 specific code from design.master.tcl.template

commit fc930ec8
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 24 16:45:59 2018 +0100

    Fix bug in BlueDMA plugin

    * plugin could not change VLNV for dual_dma due to new location of
      stdcomps

commit 39e7a1cb
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 24 13:44:20 2018 +0100

    Bugfix in ZC706 fancontrol plugin

commit 6a06399b
Author: Lukas Sommer <lukas.sommer.mail@gmail.com>
Date:   Wed Jan 24 12:39:49 2018 +0100

    Moved filter condition for active-high resets to correct command;

commit cba13f81
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 24 11:28:40 2018 +0100

    Arch: Fix bug in PE reset connections

commit d1f36ab4
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 23 06:09:44 2018 +0100

    Closes #148 - Replace tapasco-status subtree by .jar

commit ee793881
Merge: bbae0376 82ce7119
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon Jan 22 18:58:46 2018 +0100

    Pull tapasco-status

    Merge commit '82ce7119' into pe-local-memories

commit 82ce7119
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon Jan 22 18:58:17 2018 +0100

    Squashed 'common/ip/tapasco_status/' changes from e209f949..5b218b0

    5b218b0 Pull chisel-axi
    7cecbce Squashed 'axi/' changes from 01fad68..ec8f7a2
    e56e93c Pull chisel-packaging
    0e3cc98 Squashed 'packaging/' changes from c22243b..e6a5a78
    4e421af Add assembly fatjar packaging, increase version to 1.0
    41e37e7 Squashed 'axi/' changes from b8f4c554..01fad68
    3fd53e7 Pull chisel-axi
    872f551 Squashed 'packaging/' changes from 134b2f62..c22243b
    88624e0 Pull chisel-packaging
    f94b6de3 Remove caching of ivy repo from pipeline
    43c331dc Pull chisel-axiutils
    5937e2aa Implement cap0 bitfield
    26d61dd6 Bugfix in pipeline
    1030ffe5 Cache ivy2 repo in pipeline builds
    14876b2e Implement support for capability field in Status Core
    2a3e6856 Fix removed '<<=' sbt operator
    bccc8a73 Run sbt test in GitLab pipeline
    17e1a3a7 Fix bug concerning empty slots
    5a089419 Ignore compiled python scripts in .gitignore
    0f0a2d84 Update packaging to GitHub-version of Chisel3
    a162cfae Update miscutils to GitHub-version of Chisel3
    f0265156 Remove ununsed Scalactic dep
    d146b992 Rename RegisterFile saxi port to s_axi

    git-subtree-dir: common/ip/tapasco_status
    git-subtree-split: 5b218b00f8f27f40c6cda836ddde5462f4296d33

commit bbae0376
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 19 18:52:52 2018 +0100

    Implement reading of status core regs for memories

commit 052a692a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:51:34 2018 +0100

    Improve logging in Zynq platform Tcl

commit 2d997d02
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:51:02 2018 +0100

    Improve logging in platform common Tcl

commit 0a48d743
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:50:32 2018 +0100

    Improve logging in tapasco::ip

commit 5c397f7d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:49:58 2018 +0100

    Activate PE-local memory capability by default

commit 44d4f975
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 18 13:49:40 2018 +0100

    Bugfix in Arch address map for unconnected masters

commit 6ea82dc4
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 16 15:16:27 2018 +0100

    Closes #137 - TaPaSCo is stuck after all jobs finished in verbose mode

commit 961d9bc6
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 12 16:38:09 2018 +0100

    Vivado/HLS: delete logfile before watching

commit b4311e00
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 12 16:37:19 2018 +0100

    Add temporary support for 2017.3/4

commit beb71c3d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 12 16:34:58 2018 +0100

    Rebuild all Platforms using new skeleton

    * rebuilt PyNQ, zedboard and ZC706 without features
    * expanded subsystem package: standard and custom subsystems can be
      fetched (as bd cells) and their names queried (incl. custom)
    * Zynqs adapt the memory system to bypass
    * need to run more tests, but looks good
    * timing problems in VC709, need to investigate

commit 6cb43d23
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 12 10:04:23 2018 +0100

    Improve libmpfr seeking

commit 8a660e3d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 11 16:30:57 2018 +0100

    Fix dual_dma constraints

commit 7ffe7520
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 11 15:34:51 2018 +0100

    Move all IP block related code into new namespace ip

    * tapasco::ip contains methods to instantiate common IP
    * common/ip.tcl automatically generates methods based on the stdcomps
      directory: every name has its own instantiation method called
      create_<name>, which takes only a name as an argument
    * specialized constructors go into common_ip.tcl and can override the
      auto-generated ones
    * removed all createXY procs in common.tcl and fixed all dependent
      scripts accordingly
    * removed ill-fated "clocks_and_resets" bundle - sad, but didn't work
      correctly in Vivado

commit 8d6b2d59
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 11 11:20:24 2018 +0100

    VC709: finish Platform refactoring

    * VC709 designs should build again
    * generalized address mapping, same method should be applicable to other
      Platforms like Zynq, too
    * still WIP, need to move a few bits between implementations

commit c4d81df5
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 10 17:38:57 2018 +0100

    WIP: started to work on generic address mapping

commit 2fba2589
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 10 12:55:15 2018 +0100

    VC709: Fix clock and reset wiring

commit 31e7a81c
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 10 10:01:38 2018 +0100

    Fix bug in setup.sh: locate may not be available

commit d675e2be
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 9 18:38:38 2018 +0100

    setup.sh: use locate instead of find

commit 944b8844
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 9 18:38:21 2018 +0100

    WIP: Continue work on new interfaces

commit b33fa803
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 9 18:30:14 2018 +0100

    Fix chiselSetup.sh, build.sbt

commit bd890015
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Mon Jan 8 16:51:08 2018 +0100

    WIP: remove Bundle interfaces, does not work :-(

    * will need to use individual pins
    * started to move subsystem code to subsystem.tcl

commit 3cdff64a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 20:14:10 2018 +0100

    WIP: reimagine basic Platform construction

    * need to simplify Platform scripts, move more code into a common base
    * will generalize and unify the basic structure of the project
    * does not work yet, but looks promising

commit d04440b0
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 20:12:37 2018 +0100

    Fix bug for Vivado HLS

    * Vivado HLS does not have a -notrace parameter for source command

commit d4c91637
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 20:12:10 2018 +0100

    Implement tapasco::get_vlnv method to get VLNVs

commit 0c33be87
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 20:10:35 2018 +0100

    Add common_ip.tcl as base catalog

    * common_ip.tcl will contain all basic ip VLNVs
    * only differences are recorded in the _20xx.tcl scripts

commit 8a43f455
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 19:56:17 2018 +0100

    Fix problems with clocks and resets bridges

    * found a way to express in IP-XACT that the interfaces are only bridged
      directly; there seems to be no way of doing this via Vivado, but since
      Xilinx is using it themselves (e.g., System Cache) I hope it'll work
    * also remove interconnect_reset port, since they do not exist on the
      reset generators

commit 84c35860
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Jan 5 10:19:42 2018 +0100

    Implement a bus abstraction for TaPaSCo clocks and resets

    * new interface:
      esa.cs.tu-darmstadt.de:tapasco:tapasco_clocks_resets:1.0
    * bundles host, design and mem clocks and all reset kinds for easier
      connection of the subsystems
    * each subsystem should instantiate a ClocksResetsSlaveBridge to access
      the ports
    * the clocks and resets subsystem uses a ClocksResetsMasterBridge to
      propagate the clocks and resets
    * both IPs are zero-logic direct wire thruputs; only used to allow
      bundling at interface leve

commit 15f96d39
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 16:08:35 2018 +0100

    Implement automatic build process for new Status Core

    * there is a subproject that is included as a subtree in
      common/ip/tapasco_status
    * subproject is standalone and can be run from Tcl
    * changed process in common.tcl: createTapascoStatus now generates a
      JSON configuration file and runs sbt in the subproject
    * each Composition gets its unique status core
    * status cores are cached in tapasco-status-cache in the main dir:
      when building the same composition a number of times, status cores can
      be reused; is removed automatically in sbt clean
    * required more API extensions: platform::get_address_map must be
      implemented by the Platform to communicate the address mapping to the
      status core creation
    * also added formal interface to capabilities in common.tcl:
      tapasco::add_capability_flag, tapasco::get_capability_flags and
      tapasco::set_capability_flags can be used by plugins to activate
      capability bits
    * whole process should be transparent to the user, everything is
      supposed to work as before
    * one exception: get_address_map is not yet implemented on VC709

commit decea9b9
Merge: d5704092 f94b6de3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:53:24 2018 +0100

    Pull tapasco-status-chisel

    Merge commit 'f94b6de3' into pe-local-memories

commit d5704092
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:52:36 2018 +0100

    Ignore tapasco-status-cache temp dir

commit f94b6de3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:46:52 2018 +0100

    Remove caching of ivy repo from pipeline

    * following an internal discussion, we'd rather be sure to build
      everything from scratch in the runner, or version hell ensues

commit 43c331dc
Merge: 5937e2aa 5a089419
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:39:09 2018 +0100

    Pull chisel-axiutils

    Merge commit '5a089419'

commit 5937e2aa
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:38:31 2018 +0100

    Implement cap0 bitfield

commit 26d61dd6
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:37:35 2018 +0100

    Bugfix in pipeline

commit 1030ffe5
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:34:11 2018 +0100

    Cache ivy2 repo in pipeline builds

commit 14876b2e
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 13:33:13 2018 +0100

    Implement support for capability field in Status Core

commit 2a3e6856
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 10:59:11 2018 +0100

    Fix removed '<<=' sbt operator

commit bccc8a73
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 10:41:06 2018 +0100

    Run sbt test in GitLab pipeline

commit 17e1a3a7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 4 10:29:56 2018 +0100

    Fix bug concerning empty slots

    * empty slots did not exist at all, resulting in reads/writes causing
      bus errors, crash
    * new Slot type Empty represents an empty slot
    * slots in status configuration are filled with empty slots to fix the
      problem
    * should not increase the size significantly; all empty slots are
      represented by the same ConstantRegister

commit 5a089419
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:02:42 2018 +0100

    Ignore compiled python scripts in .gitignore

commit 0f0a2d84
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:02:00 2018 +0100

    Update packaging to GitHub-version of Chisel3

commit a162cfae
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:01:32 2018 +0100

    Update miscutils to GitHub-version of Chisel3

commit f0265156
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:00:45 2018 +0100

    Remove ununsed Scalactic dep

commit d146b992
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jan 4 10:00:13 2018 +0100

    Rename RegisterFile saxi port to s_axi

commit a68c751e
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 15:40:04 2018 +0100

    Automatically use libmpfr.so workaround on Ubuntu

commit 56210a05
Merge: 225cfa31 e209f949
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:43:05 2018 +0100

    Add 'common/ip/tapasco_status/' from commit 'e209f949'

    git-subtree-dir: common/ip/tapasco_status
    git-subtree-mainline: 225cfa31
    git-subtree-split: e209f949

commit 225cfa31
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:42:28 2018 +0100

    Change Tapasco Status Core VLNV to new Chisel version

commit 944327d2
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:42:06 2018 +0100

    Remove Verilog implementation of Tapasco Status Core

commit e209f949
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:37:19 2018 +0100

    Ignore test and chisel3 directories at top level

commit 18559a40
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:35:21 2018 +0100

    Fix minor bug in chiselSetup.sh

commit 6194279d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:35:07 2018 +0100

    Remove chisel3 libs on sbt clean

commit dad7a067
Merge: b98b7616 a9f329c5
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:21:32 2018 +0100

    Pull chisel-axi updates

    Merge commit 'a9f329c5'

commit b98b7616
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 09:21:09 2018 +0100

    Automatically build Chisel3 dev libs

commit a9f329c5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jan 3 09:19:49 2018 +0100

    Bugfix for latest Chisel3

    * zero-width io ports must be assigned, or compilation will fail
    * fixed RegisterFileSpec accordingly
    * updated to Scala 2.11.12

commit 7adf7220
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 08:33:48 2018 +0100

    Ignore compiled python scripts

commit da655ea7
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 08:31:37 2018 +0100

    Implement spec tests for RTL behavior

    * re-used generic test from RegisterFile
    * status configuration is generated by spec gens

commit 5533df8a
Merge: 91193a3a 8d79675d
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Jan 3 08:19:26 2018 +0100

    Pull chisel-axi

    Merge commit '8d79675d'

commit 8d79675d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jan 3 08:16:17 2018 +0100

    Move generic test to companion for reusability

commit ce2bad61
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jan 3 08:10:04 2018 +0100

    Update play-json dependency

commit 91193a3a
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 19:50:03 2018 +0100

    Move to latest development versions of Chisel3

commit 3cf2bdac
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 19:49:47 2018 +0100

    Move to latest development versions of Chisel3

commit d928c364
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 19:49:22 2018 +0100

    Move to latest development versions of Chisel3

commit af6fc853
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 19:47:30 2018 +0100

    Implement Builder to generate IP core from JSON

    * Builder class main uses first argument as path to JSON config file
    * IP Core is generated under ip/ hierarchy: each configuration hash is
      unique and can be used to cache products
    * sbt clean removes this cache
    * example.json contains an example configuration

commit 10730b41
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 18:31:38 2018 +0100

    Structure JSON SerDes code

commit cc738039
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 18:17:11 2018 +0100

    Implement spec testing for Json SerDes

    * JsonSpec checks that roundtrips to and from Json preserve all data
    * generators package contains ScalaCheck generators

commit 6f821d5f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 18:13:07 2018 +0100

    Finish draft for TaPaSCo status core configurations

    * Status contains complete configuration, including kernel ids, memory
      slots and some basic sanity checking
    * json package contains JSON SerDes functionality

commit 0ddba2f3
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 12:32:45 2018 +0100

    Start to draft the IP core

    * started with external format (JSON)
    * noticed a problem: without Verilog module parameters Features cannot
      easily add capabilities etc.
    * postponing the project until later

commit 0ec5077d
Merge: 1846cfbe 134b2f62
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 10:24:25 2018 +0100

    Add 'packaging/' from commit '134b2f62'

    git-subtree-dir: packaging
    git-subtree-mainline: 1846cfbe
    git-subtree-split: 134b2f62

commit 1846cfbe
Merge: bea8ec99 b8f4c554
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 10:20:23 2018 +0100

    Add 'axi/' from commit 'b8f4c554'

    git-subtree-dir: axi
    git-subtree-mainline: bea8ec99
    git-subtree-split: b8f4c554

commit bea8ec99
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Tue Jan 2 10:20:02 2018 +0100

    README.md

commit cdc16d33
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Dec 29 19:32:20 2017 +0100

    Zynq: Fix address map

    * PE-local memory segments should be inserted after ctrls
    * needs fixing in VC709, too

commit 7936dadd
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Dec 29 18:54:40 2017 +0100

    Add registers to TaPaSCo status core for local mems

    * register after kernel id is reserved for memory size
    * 0xFFFFFFFF indicates no local memory available at the slot
    * smaller values are 0xFFFFFFFF - size
    * added capability flag in core, defaults to on from 2018.1

commit dcda2256
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Dec 29 15:52:33 2017 +0100

    Implement basic flags and errors for PE-local memories

commit b8f4c554
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 29 14:17:08 2017 +0100

    Fix bug in Register implementation

    * width would not be propagated correctly
    * fixed, also changed standard write test to increase by 1 from offset,
      making accidental correctness less likely

commit 886e04b9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 29 11:28:43 2017 +0100

    Change address base type to Long

    * addresses can be larger than 32bit, thus need to use Long
    * in fact, having the upper-most bit 1 already gave problems
    * fixed and updated all dependents

commit 70928314
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 29 10:36:59 2017 +0100

    Add restart input to ProgrammableMaster

    * while high, won't execute any actions, but reset its step counter

commit 0b91c23a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 29 10:36:45 2017 +0100

    Move ProgrammableMaster to main

commit cd96aee5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 28 11:25:28 2017 +0100

    Make ProgrammableMaster startable

    * if constructor argument is given, will start sequence only while
      io.start is high
    * default is false for startable

commit ed7185ff
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 27 17:23:54 2017 +0100

    Add default implementations for VirtualRegister

    * read returns None by default
    * write returns the write value by default, does nothing

commit 17e328ed
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 27 17:21:54 2017 +0100

    RegisterFile: Move behavior into method

    * behavior cannot be generated statically, because VirtualRegisters
      would then be unable to access values and regs of the module
    * behavior is now generated by RegisterFile.behavior and
      RegisterFile.resetBehavior instead
    * fixed definition of generic registerfile (no custom IO, regs, etc.)

commit 05b3795f
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 27 11:01:35 2017 +0100

    Remove accidental swap files

commit 930e85ba
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 20 18:28:12 2017 +0100

    Fix build.sbt

commit c8eea4e8
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Wed Dec 20 18:27:40 2017 +0100

    Implement short-hand for named bits

commit 134b2f62
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:30:09 2017 +0100

    Fix bugs in package.py regarding modules with interfaces

    * missing top-level import fixed
    * VLNVs for bus interfaces fixed
    * package.tcl is now written to disk, contains the script (for
      debugging)

commit 4a038ecf
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:30:09 2017 +0100

    Fix bugs in package.py regarding modules with interfaces

    * missing top-level import fixed
    * VLNVs for bus interfaces fixed
    * package.tcl is now written to disk, contains the script (for
      debugging)

commit 896634de
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:29:43 2017 +0100

    ModuleBuilder: add explicit top-level-module name

commit a5c36c57
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:29:43 2017 +0100

    ModuleBuilder: add explicit top-level-module name

commit 41fa107a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:29:16 2017 +0100

    Bugfix in CoreDefinition: Interfaces were not passed correctly

commit b93801d4
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:29:16 2017 +0100

    Bugfix in CoreDefinition: Interfaces were not passed correctly

commit 5b56956d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 14 21:26:44 2017 +0100

    Fix LargeRegisterFile example module

    * needs own class to change TLM name in Verilog
    * added AXI interface definition

commit 793c88df
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 20:11:41 2017 +0100

    Fix bug concerning too narrow address widths in RegisterFile

    * arbitrary configs would sometimes mandate less bits for the address
      than required by the register map
    * could be fixed in the register map generator, but I opted to fix it by
      permanently widening the address to 32 bits (sufficient for all cases)

commit 4286de8c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:58:07 2017 +0100

    Implement 256 register file r/w for testing purposes

    * manually tested with Xilinx AXI Verification IP, looks fine

commit 04dddcf9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:57:43 2017 +0100

    Fix renamed addrGranularity -> addressWordBits

commit 0039dd2f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:56:12 2017 +0100

    Fix BitRange overlap logic in RegisterFile and provide better errors

commit 325673de
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:52:23 2017 +0100

    Fix reset behavior in RegisterFile

    * AXI mandates that all ready signals be low during reset
    * unfortunately, not only is this not the case in Queues, but they
      actively start working while reset is high (insane)
    * fixed by manually pulling the signals low on reset
    * tested with Xilinx AXI Verification IP, all's well

commit 5db38ae2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:49:37 2017 +0100

    Fix uninitialized wires in FifoAxiAdapter

commit f93ae122
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:48:52 2017 +0100

    Simplify overlap logic in BitRange

commit 57c18b2b
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:46:01 2017 +0100

    Fix uninitialized wires in Mux

commit 9d650848
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:45:31 2017 +0100

    Fix uninitialized wires in AxiFifoAdapter

commit 99699663
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Dec 13 18:44:56 2017 +0100

    Implement wire defaults for AXI4 interfaces

commit f26ba638
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Dec 12 18:11:07 2017 +0100

    Finish streamlined implementation of RegisterFile

    * entirely based on Queues now, fixed firing logic
    * still with workaround for problem in Queue with optional fields
    * simplified ProgrammableMaster
    * changed Registers write method to return Response instead of Boolean
    * switched completely to Spec testing: register files are generated
      ad-hoc, corresponding master program and testing steps are
      automatically generated

commit effaef3e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Dec 12 17:10:53 2017 +0100

    Bugfix registerMapGen: always uses same instances

    * register map contained always the same instances for each kind
    * core problem: the new ... generators are implicitly converted to const
    * fixed by adding random Gen element to both generators

commit f175bf4e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:55:29 2017 +0100

    Move to dev versions of Chisel3 and iotesters

commit 3b80a251
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:55:06 2017 +0100

    Fix problems in ProgrammableMaster regarding uninits

commit c7de8149
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:53:35 2017 +0100

    RegisterFile: rewrite with Queues

    * replaced FSM approach with Queues; each channel has its own Queue, and
      all is handled using the handshakes
    * simple, because 1-cycle reads and writes can be guaranteed

commit c74b8a56
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:53:01 2017 +0100

    Implement wire defaults for Axi4Lite sub-bundles

commit ee598c83
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Dec 11 17:52:25 2017 +0100

    Add AnyVals from Scalactic

commit a24a7684
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Dec 10 01:59:40 2017 +0100

    Fixed naming issues in packages

    * new scheme: chisel.axi is the main package
    * chisel.axi.Axi4 contains the full axi defs
    * chisel.axi.Axi4Lite contains the lite defs
    * chisel.axi.axi4 contains full Axi4 impls
    * chisel.axi.axi4lite contains lite impls
    * same applies for the generators, matching structure

commit bb347461
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Dec 10 01:44:32 2017 +0100

    WIP: Implement generic spec testing for RegisterFile

    * moved DataWidth from top axi to Axi4/Axi4Lite objects
    * cleaned generators, adopted new naming structure
    * implemented generators for arbitrary register files
    * master actions improved, simpler constructors
    * master actions can be automatically generated from register file
    * need to clean up the namespaces etc. - gotten really messy

commit 318d789b
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Dec 8 16:21:25 2017 +0100

    Fix test problems in RegisterFileSpec

    * fixed some issues in ProgrammableMaster regarding wrong types of the
      response channels (was using old approach, direct UInt)
    * fixed some issues in the register file spec, regarding peek/poke of
      non-IO fields, tests are functional

commit 1de898c4
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 7 14:02:01 2017 +0100

    Fix compilation issues in ProgrammableMaster

commit 72ee604c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 7 14:01:10 2017 +0100

    Fix generators import in axi4lite.generators

commit af185bae
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Dec 7 14:00:04 2017 +0100

    Aggregate projects to make clean apply to all

commit 6394501a
Merge: e8e1cf67 1fee5bb1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Dec 2 07:48:50 2017 +0100

    Merge chisel-miscutils

    Merge commit 'e9ddda06381e35f203a5692dcd6395852424cb38'

commit e8e1cf67
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:36:46 2017 +0200

    Implement generators for ScalaCheck for AXI configurations

commit 7fa3b107
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:34:38 2017 +0200

    RegisterFile: remove reset logic

commit ceb82b5c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:33:22 2017 +0200

    SlidingWindow: Remove reset logic

commit e3a6000c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:32:53 2017 +0200

    Mux: remove reset logic

commit d8e4d2c7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Oct 11 12:31:18 2017 +0200

    Add read and write to Axi masters / addresses

commit 6f84679d
Merge: b351de03 c734b464
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 22 13:34:11 2017 +0200

    Merge chisel-miscutils

    Merge commit '48f930ee8d5d702ff5b29577c8dc13aef4b5363d'

commit c734b464
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 22 13:34:11 2017 +0200

    Squashed 'miscutils/' changes from 5041968..e9ddda0

    e9ddda0 Remove direct references of reset

    git-subtree-dir: miscutils
    git-subtree-split: e9ddda06381e35f203a5692dcd6395852424cb38

commit 1fee5bb1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 22 13:30:32 2017 +0200

    Remove direct references of reset

commit b351de03
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 31 08:50:18 2017 +0200

    !WIP! Refactor all components

commit 4ee69876
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 31 08:46:37 2017 +0200

    Add test/ to cleanFiles

commit 11694b7d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 11:05:16 2017 +0200

    Squashed 'miscutils/' changes from fa152fd..5041968

    5041968 SlowQueue: remove direct reset references
    bc2de4a Minimize SignalGenerator
    91f6202 Minimize DecoupledDataSource
    435a442 Minimize DataWidthConverter logic

    git-subtree-dir: miscutils
    git-subtree-split: 5041968ba66ec8c5329d7da6594b3f031437730d

commit 6064ffaf
Merge: f581c158 11694b7d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 11:05:16 2017 +0200

    Merge chisel-miscutils

    Merge commit '17ce5f15e119b08bf38d87c1276f001b9ff0d11d'

commit f581c158
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 11:02:24 2017 +0200

    Write FifoAxiAdapter specification

    *  basic tests implemented
    *  peekAt/pokeAt do not work; took a lot of time to figure out
    *  need to implement a workaround using a serial interface
    *  introduces its own problems, *sigh*

commit 2685786a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 10:53:20 2017 +0200

    SlowQueue: remove direct reset references

commit 57bf9a77
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 10:52:16 2017 +0200

    Minimize SignalGenerator

    *  direct reference of reset is discouraged
    *  replaced explicit reset code with RegInits

commit 7395f54f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 10:39:41 2017 +0200

    Minimize DecoupledDataSource

    *  direct references of reset are discouraged
    *  replaced all direct refs with RegInits, where appropriate
    *  fixed overwrite bug in test outputs, each test writes in separate dir

commit 8e94f119
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 30 10:21:12 2017 +0200

    Minimize DataWidthConverter logic

    * direct reference of reset is discouraged
    * replaced all direct references with RegInits or removed reset
    * fixed overwrites of test runs (now each in separate dir)
    * added test directory to cleanFiles, will be removed on sbt clean

commit dc850c61
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 29 14:21:25 2017 +0200

    Squashed 'miscutils/' changes from 5bda007..fa152fd

    fa152fd Cosmetic changes: Move IO defs to companion objects
    37a4949 Minor fix in valid signal

    git-subtree-dir: miscutils
    git-subtree-split: fa152fd8210a13bfb8024ae569b440ac247ccb73

commit df0710b6
Merge: 357a3810 dc850c61
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 29 14:21:25 2017 +0200

    Merged chisel-miscutils

    Merge commit 'c60f21734856c5828fd574bffe7c6e31acf1c942'

commit d1530d38
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 29 14:18:56 2017 +0200

    Cosmetic changes: Move IO defs to companion objects

commit cf989d9c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 29 14:00:55 2017 +0200

    Minor fix in valid signal

commit 357a3810
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Aug 28 18:43:05 2017 +0200

    More refactoring, started work on FifoAxiAdapterSpec

commit 441095fb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Aug 28 18:12:34 2017 +0200

    Refactoring, clean-up

    *  split into subpackages axi4 and axi4lite
    *  moved each module into its subpackage
    *  shortened names by removing Axi-prefixes wherever possible
    *  moved Configs and IOs into corresponding companion object
    *  replaced some printlns/printfs with Logging facilities

commit ce2a5d30
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 26 16:55:54 2017 +0200

    Squashed 'miscutils/' changes from c428dca..5bda007

    5bda007 DecoupledDataSource: repeat and non-pow2 sizes
    f6b927d Implement logging for Modules

    git-subtree-dir: miscutils
    git-subtree-split: 5bda007e1425eb09deb475dbe2e19849415f7a69

commit 82e7d31a
Merge: 03be2246 ce2a5d30
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 26 16:55:54 2017 +0200

    Merged chisel-miscutils

    Merge commit 'fe9856d869b808e52fc1a27225f684c78b392230'

commit 77b40f09
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 26 16:52:51 2017 +0200

    DecoupledDataSource: repeat and non-pow2 sizes

    * repeat now also works with size which are not a power of 2
    * more complex Mux logic is only generated in case size is not a power
      of 2, otherwise identical as before
    * cleaned up a little and used new logging facilities to implement
      fine-grained info at each consumption

commit 0e19c7ff
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 26 16:50:20 2017 +0200

    Implement logging for Modules

    * implemented both hardware (runtime) logging and constructor logging
      (compile time)
    * mix-in trait Logging provides methods info, warn and error (and cinfo,
      cwarn, cerror resp. for constructor logging)
    * logging level is controlled by implicit Logging.Level, determined at
      each call, allows for selective logging

commit 03be2246
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 18:40:33 2017 +0200

    !WIP! still working on fixing Axi

commit 20323ee9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:44:18 2017 +0200

    Squashed 'miscutils/' changes from 6b570c6..c428dca

    c428dca Decreased number of tests for DataWidthConverter
    3f395f6 Bugfix concerning log2Ceil(1) == 0
    0092287 Replace unit tests for DataWidthConverter with property spec
    9ffa2fe Finish data width converter correctness spec
    435ee4b Work on generator for valid data width conversions
    f91ed9f Start implementation of data width conversion spec
    1d57540 Improve debug output of DecoupledDataSource
    4a4a7d2 Replace DecoupledDataSource testing with prop check
    9da9dc5 Finish replacement of SignalGenerator tests
    aeee2cd Started with property-based testing
    20c08e2 Fix bug in DecoupledDataSource, remove crossVersions

    git-subtree-dir: miscutils
    git-subtree-split: c428dca006d0aa62d25c83ffdffad8baf229bcfb

commit 8f2faf2e
Merge: 511f7779 20323ee9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:44:18 2017 +0200

    Merge of chisel-miscutils

    Merge commit '61fdb4b48f81caf5ae3e68aead564fb34a2c4371'

commit f127f8f0
Merge: 46bd95d9 5a3d0f79
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:43:06 2017 +0200

    Merge of chisel-packaging

    Merge commit '2f16edbf19e62a15e4770e960b05be552770e6d5'

commit 511f7779
Merge: 2cd5e201 a8d00c84
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:43:06 2017 +0200

    Merge of chisel-packaging

    Merge commit '2f16edbf19e62a15e4770e960b05be552770e6d5'

commit a8d00c84
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:43:06 2017 +0200

    Squashed 'packaging/' changes from 7854cfd1..5a3d0f79

    5a3d0f79 Postfix issue, feature warnings activated
    fc967e4c Update to Scala 2.11.11
    ad1c4c32 Support for manual AXI-mapping, postBuildOps fix
    fa4bfbeb Fix README.md markdown syntax

    git-subtree-dir: packaging
    git-subtree-split: 5a3d0f79

commit 2cd5e201
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:40:47 2017 +0200

    Start port to Chisel3

commit 85e229eb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:36:55 2017 +0200

    Decreased number of tests for DataWidthConverter

commit 5702af68
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 14:33:56 2017 +0200

    Bugfix concerning log2Ceil(1) == 0

commit a09d132d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 11:39:36 2017 +0200

    Replace unit tests for DataWidthConverter with property spec

    * replaced unit test with much more generic property specs
    * also refactored test classes into module-subpackages

commit 52b5a373
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 08:12:56 2017 +0200

    Finish data width converter correctness spec

commit 8d7db075
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 07:28:55 2017 +0200

    Work on generator for valid data width conversions

commit 43beb5b4
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 25 07:26:34 2017 +0200

    Start implementation of data width conversion spec

commit d428bf8c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 15:55:09 2017 +0200

    Improve debug output of DecoupledDataSource

commit 44b5908e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 15:52:24 2017 +0200

    Replace DecoupledDataSource testing with prop check

    * defined generic property for DecoupledDataSource:
    * testing correctness (correct order + value of data), handshakes (wait
      while consumer is not ready) and repeat behavior
    * running random tests over arbitrary bitwidth, size and repeat flags

commit b3857489
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 15:18:02 2017 +0200

    Finish replacement of SignalGenerator tests

    * finished implementation of property based testing with random
      generators, much more thorough than the previous tests
    * implemented both regular clock input and generated random clock input

commit 187a74fb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 13:38:00 2017 +0200

    Started with property-based testing

commit 63498417
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 08:10:54 2017 +0200

    Fix bug in DecoupledDataSource, remove crossVersions

commit 5a3d0f79
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 24 08:01:40 2017 +0200

    Postfix issue, feature warnings activated

commit fc967e4c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 23 17:20:09 2017 +0200

    Update to Scala 2.11.11

commit 8d7821f5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Aug 23 13:31:55 2017 +0200

    Port to Chisel 3

commit ad1c4c32
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Aug 22 18:36:06 2017 +0200

    Support for manual AXI-mapping, postBuildOps fix

    * postBuildActions can no longer use the Module instance directly, since
      Chisel3 prohibits its instantiation outside of a Driver
    * added a configuration object of type Any instead, which will be passed
      to the postBuildActions - we do not actually need the Module instance,
      only the configuration options passed to it
    * Chisel3 no longer supports renaming of top-level ports (setName has
      vanished); auto-inference of the AXI-interfaces is not possible
      without renaming
    * fixed by adding interface definitions to CoreDefinition:
    * each module may declare "known" interfaces; in this case the IP-XACT
      Tcl will match to the generated port names manually

commit fa4bfbeb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 18 16:50:58 2017 +0200

    Fix README.md markdown syntax

commit 8a742587
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:42:23 2017 +0200

    Squashed 'miscutils/' changes from 6d4e97b..6b570c6

    6b570c6 Fix bug in DecoupledDataSourceSuite
    dee2777 Update README.md
    ad4e6f3 README.md edited online with Bitbucket
    3528414 Update to Chisel 3.0 (SNAPSHOT)

    git-subtree-dir: miscutils
    git-subtree-split: 6b570c6a26a7707719404beace67a289289c90ed

commit 48cb64c9
Merge: 641d8456 8a742587
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:42:23 2017 +0200

    Merge commit '537797a1709f872129c78d22b07ad42ab469c1cf'

    Pulled chisel-miscutils.

commit 46bd95d9
Merge: a4d7be88 7854cfd1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:41:25 2017 +0200

    Merge commit '69c3892a214fd740dd605d864fdd88f70a4c7dfd'

    Pulled chisel-miscutils.

commit c5f977bc
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:41:25 2017 +0200

    Squashed 'packaging/' changes from 99804e52..7854cfd1

    7854cfd1 Update README.md - fix dead link
    b992dd73 README.md edited online with Bitbucket
    f15683a7 Update README.md
    fdfd1420 Update README.md
    2190c490 Write README.md
    4531adea Update to Chisel 3.0 (SNAPSHOT)

    git-subtree-dir: packaging
    git-subtree-split: 7854cfd1

commit 641d8456
Merge: 356808da c5f977bc
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:41:25 2017 +0200

    Merge commit '69c3892a214fd740dd605d864fdd88f70a4c7dfd'

    Pulled chisel-miscutils.

commit 356808da
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 15 18:41:00 2017 +0200

    Update to chisel3

commit 9749d045
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 13 18:53:30 2017 +0200

    Fix bug in DecoupledDataSourceSuite

    * chisel3 is a little finicky with peek/poke: it seems only stuff in the
      io bundle of modules is really safe
    * needed to replace peeking in the internal mems, since that seems
      to crash the LoFirrtlEvaluator
    * all tests functional again

commit 04f0a4d7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 16:11:28 2017 +0200

    Update README.md

commit cc23217a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 14:05:47 2017 +0000

    README.md edited online with Bitbucket

commit 7854cfd1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 15:29:01 2017 +0200

    Update README.md - fix dead link

commit b992dd73
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 13:25:06 2017 +0000

    README.md edited online with Bitbucket

commit f15683a7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 12:58:01 2017 +0000

    Update README.md

commit fdfd1420
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 12:45:55 2017 +0000

    Update README.md

commit 2190c490
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 12:25:13 2017 +0000

    Write README.md

commit 9f3c5835
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 8 07:01:04 2017 +0200

    Update to Chisel 3.0 (SNAPSHOT)

commit 4531adea
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 7 17:22:29 2017 +0200

    Update to Chisel 3.0 (SNAPSHOT)

commit b8d8f0e1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:44:09 2016 +0200

    Define proper subprojects in build.sbt

    * miscutils, packaging are subprojects which are depended upon
    * configured correspondingly in build.sbt, removed symlinks in src
    * defined metadata for build artifact (incl. version)
    * updated .gitignore to ignore temp files in subprojects

commit f9b1ffdb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:39:16 2016 +0200

    Squashed 'miscutils/' changes from 0fec184f..6d4e97b

    6d4e97b Add build.sbt to define artifact

    git-subtree-dir: miscutils
    git-subtree-split: 6d4e97bfae9ff6dcb1f106ca6dd94bf086d40c77

commit 24c23140
Merge: e39c6df7 f9b1ffdb
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:39:16 2016 +0200

    Merge commit '671c7e7c48474bfe51815e56fbabb0f68151c617'

commit a4d7be88
Merge: eac01b7a 99804e52
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:38:44 2016 +0200

    Merge commit '972b1fb317c33c96523a9b48775f470c9d0faf03'

commit 9db79f78
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:38:44 2016 +0200

    Squashed 'packaging/' changes from d2df30ff..99804e52

    99804e52 Add build.sbt to define artifact
    401df026 Add support for post-build actions

    git-subtree-dir: packaging
    git-subtree-split: 99804e52

commit e39c6df7
Merge: 3d7635a0 9db79f78
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:38:44 2016 +0200

    Merge commit '972b1fb317c33c96523a9b48775f470c9d0faf03'

commit 1ebdde01
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Oct 1 09:28:15 2016 +0200

    Add build.sbt to define artifact

commit 99804e52
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Sat Oct 1 09:26:23 2016 +0200

    Add build.sbt to define artifact

commit 3d7635a0
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 30 19:33:00 2016 +0200

    Axi4LiteRegisterFile: Implement config register file

    * AXI4Lite interface
    * flexible ControlRegister class hierarchy: constants, single values,
      virtual registers (callbacks)
    * implemented unit test cases
    * had to implement Axi4LiteProgrammableMaster for batch testing

commit eac01b7a
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 30 19:31:47 2016 +0200

    Add support for post-build actions

commit 401df026
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Fri Sep 30 19:31:47 2016 +0200

    Add support for post-build actions

commit bf5ca040
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 30 19:31:47 2016 +0200

    Add support for post-build actions

commit 2ae7b74d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Sep 28 17:09:07 2016 +0200

    AxiSlidingWindow: reverse order in window

commit 992c37c2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Sep 18 13:26:54 2016 +0200

    Implement generic, round-robin Axi Mux

    * muxes N AXI-MM masters to one AXI-MM slave
    * read and write channels are mux'ed independently
    * no interruptions during bursts, next schedule on LAST
    * address valid is used to signal transfer requests
    * may cost up to N-1 cycles latency

commit 410607d7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Sep 14 20:26:01 2016 +0200

    AXIMasterIF: renameSignals with prefix and suffix

    * renameSignals on AXI bundle should support prefix and suffix in order
      to accomodate multiple instance of the interface in one module

commit 962277e9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Sep 14 10:19:13 2016 +0200

    Implement AxiSlidingWindow module

    * configurable sliding window module with AXI DMA backend
    * uses AxiFifoAdapter internally to retrieve data from AXI slave
    * shifts with Decoupled interface
    * generic module for arbitrary bitwidths / data types

commit 9ea813c5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Sep 14 10:17:24 2016 +0200

    AxiSlaveModel: Add companion object

    * has method to fill AxiSlaveModel with structured data for testing

commit 1e69313e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Sep 12 10:39:31 2016 +0200

    AxiFifoAdapter: Clean-up configuration

    * moved config params into sealed case class
    * unified constructors to use new config object
    * added companion object for convenience constructors (backward
      compatible)
    * changed constructor calls in unit tests accordingly

commit a5b8e23c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 2 15:51:36 2016 +0200

    FifoAxiAdapter: implement size parameter

    * size parameter indicates automatic address wrapping
    * no need for resets in between (not always feasible)
    * wraps on overflow to current value of `base` input

commit d011dbf5
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 2 15:49:52 2016 +0200

    Add memory access functions for AXI slave model

    * new methods allow getter access via address or index
    * set method supports writing at address

commit 928b15f9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Sep 2 15:48:51 2016 +0200

    Implement memory dumping for AXI slave models

commit e23188d9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:21:33 2016 +0200

    Squashed 'miscutils/' content from commit 0fec184f

    git-subtree-dir: miscutils
    git-subtree-split: 0fec184f

commit 52108c3e
Merge: b3c0eff4 e23188d9
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:21:33 2016 +0200

    Merge commit '9a26aa5c3479f3bc887be835aa73a078d7584fac' as 'miscutils'

commit 524cfa5f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:21:09 2016 +0200

    Squashed 'packaging/' content from commit d2df30ff

    git-subtree-dir: packaging
    git-subtree-split: d2df30ff

commit b3c0eff4
Merge: 1561873f 524cfa5f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:21:09 2016 +0200

    Merge commit 'e67e9eea647ec97b2dc3f10d9490d5029d7ef5c2' as 'packaging'

commit 1561873f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 27 12:20:54 2016 +0200

    Remove submodules

commit 6b48aac2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 6 08:26:29 2016 +0200

    Update miscutils

commit 0fec184f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Aug 6 08:10:08 2016 +0200

    Clean up, add info to DecoupledDataSource

commit 294d20c2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 5 11:17:25 2016 +0200

    Update miscutils

commit 79d6920e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 5 11:13:27 2016 +0200

    DataWidthConverter: Fix full throughput

    * new full speed test suite failed: output may not block
    * fixed by adding new special case
    * achieves full speed & correctness now

commit df4586fa
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 5 11:12:03 2016 +0200

    DataWidthConverter: Extend tests

    * separated correctness from speed tests for DWC
    * correctness tests with slow queue in between and varying delays
    * full speed suite tests full throughput of data stream (may not block)
    * current implementation fails the latter

commit 65c93606
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Aug 5 08:22:56 2016 +0200

    Update miscutils

commit a621d2be
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 4 20:56:29 2016 +0200

    Bugfix in DataWidthConverter

    * DWC only worked correctly at full speed
    * delays caused lost nibbles, fixed now
    * added secondary test harness to test against a slow receiver

commit 8199d1c0
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 4 07:48:28 2016 +0200

    Reduce default delays for AxiSlaveModel

commit 18cf7be1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Aug 4 07:46:43 2016 +0200

    Adapters: fix address valid logic

    * addresses should only be handshaked when data is actually avaiable /
      needed; previous logic would provide addresses as fast as possible
    * this fixes problems with handshaken addresses at other modules when
      adapter is being reset

commit fde9d942
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Aug 1 08:37:40 2016 +0200

    AxiFifoAdapter: Bugfix AXI interface

    * opposed to FifoAxiAdapter, addresses may only be supplied via the
      interface if data will be read (slave will supply data)
    * this bug led to erroneous read bursts, overflowing the buffer
    * fixed some minor condition issues

commit 1383a12d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 31 09:46:42 2016 +0200

    FifoAxiAdapter: fix transaction logic

    * addressess in transactions should be supplied as fast as possible
    * waiting for the transaction to finish is not necessary and harms
      performance
    * not sure if this implementation is ok; there could be a large gap
      between address handshake and data - if this blocks the slave it
      must be fixed (further tests required)

commit bea25fbf
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 31 09:45:01 2016 +0200

    AxiFifoAdapterSuite: replace asserts with expects

    * asserts cause unit test to fail w/o VCD dump

commit e70fb06c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 31 09:42:41 2016 +0200

    Simplify AxiFifoAdapter

    * replaced tick-tock-buffers with single FIFO
    * burst size now independent of buffer size
    * bursts start immediately when FIFO has space for one burst
    * operation similar to FifoAxiAdapter
    * unit tests work unchanged

commit dbf972b7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 27 10:27:29 2016 +0200

    Implement configurable read and write delays

    * considering the significant delays for real-world rw access
      to memory, AxiSlaveModel should have optional delays to sim
      that behavior
    * extracted config to AxiSlaveModelConfiguration class
    * adapted existing unit test suites
    * bugfix in Axi2AxiSuite: afa now waits for writes to finish

commit c7b36058
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 26 08:15:56 2016 +0200

    AxiFifoAdapter: Improve switching speed

    * condition for switching of FIFOs led to 1-cycle delay
    * now switching when either other FIFO empty, or dequeing
      in progress and exactly one element
    * conditions are the same in both states

commit 7ce43604
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 22 12:19:59 2016 +0200

    Add Tcl scripts for Vivado projects with AXI BFMs

    * two scripts to generate block designs that will use AxiFifoAdapter
      and FifoAxiAdapter with the Cadence AXI BFMs
    * server also as cross-verification of Chisel AXI slave model
    * checks are not automated, results must be verified manually
    * AxiFifoAdapter uses Zynq BFM to preload DDR memory
    * added testbench and memory preload data for AxiFifoAdapter project
    * also added source code of preload file generator

commit 5f640c4e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 22 12:15:41 2016 +0200

    FifoAxiAdapter: rewrite to use ASAP bursts

    * now has single FIFO of configurable size
    * burst size is configurable separately
    * burst is started as soon as burstSize is exceeded in buffer
    * decided against even more aggressive mode of starting immediately,
      since that would likely be detrimental to system performance
    * adapted and verified all unit tests

commit 3447f7f1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 21 10:34:13 2016 +0200

    FifoAxiAdapter: Fix WSTRB field

    * WSTRB now correctly adapts to dataWidth (all bytes enabled)

commit 4f3e1b66
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:46:20 2016 +0200

    Implement full-round trip validating test

    * new test suite: uses both FifoAxiAdapter and AxiFifoAdapter to
      validate a full roundtrip on a AxiSlaveModel
    * most comprehensive test

commit 6d6556b1
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:42:32 2016 +0200

    AxiSlaveModel: Support write bursts

    * also rewrote size-related code: addrWidth and size are now
      optional parameters, but one must be specified (other is calced)
    * fixed some issues with the write address masking (addresses are
      always byte-boundary)
    * modified tests accordingly
    * removed asserts from tests, using proper expect calls instead
      (test now finish with errors, instead of aborting pre-VCD dump)

commit 8e521465
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:39:40 2016 +0200

    FifoAxiAdapter: Bugfix size parameter

    * did not work correctly for different dataWidths
    * also size parameter in burst address was not set correctly:
      need to specify full-width bursts

commit 6f9d34f8
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:38:42 2016 +0200

    FifoAxiAdapter: Remove read channel

commit fe9d7b90
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 20 09:34:41 2016 +0200

    AxiFifoAdapter: improve performance

    * now stays in fetch mode and just flips buffers, if current FIFO
      is empty
    * empty checks more aggressive: now checks if FIFO will be empty
      in the next cycle to mask the state transition

commit 97bbef13
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 19 13:50:34 2016 +0200

    Update miscutils, move tests to chisel.axiutils

commit 14b8a115
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 19 11:17:27 2016 +0200

    DecoupledDataSource: unassert valid during reset

    * minor bug: valid would be asserted during reset, fixed

commit 3f3fef24
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 19 11:14:10 2016 +0200

    DataWidthConverter: Fix bugs in implementation

    * previous implementation was not capable of handling a continuous
      stream of data (continuity must be preserved to avoid congestion)
    * new implementation fixes this and several other minor issues
    * better unit test: now using inverted pairs of DWCs
    * makes testing code much simpler and data/waves easier to check
    * added additional tests to specify the required timing behavior
      (i.e., preserving continuous data streams)

commit d2df30ff
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 10:22:59 2016 +0200

    Use args to ModuleBuilder to filter builds

    * args can contain names of modules, only those are built
    * names are case-insensitive
    * no args builds all modules
    * added uniqueness check for module names

commit 47415f44
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 10:15:17 2016 +0200

    CoreDefinition: another bugfix

commit 723c66e4
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 10:01:49 2016 +0200

    Bugfix in new CoreDefinition constructor

commit 67b84bed
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 09:58:41 2016 +0200

    Implemented base module builder

    * ModuleBuilder generalizes the building of modules:
      user needs only supply list of CoreDefinitions to build
    * provides main() to run automatically
    * CoreDefinition: additional constructor to automatically
      supply root dir in ip/<name> subdir

commit f0013921
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 16 09:28:47 2016 +0200

    Add signal generator from separate package

    * separate package for SignalGenerator can be removed
    * unit test included

commit 4869b09f
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 15 11:33:18 2016 +0200

    Add links to packaging and miscutils submodules

commit 896bddf6
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 15 11:32:15 2016 +0200

    Move everything to package chisel.axiutils

commit a95601dd
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 15 11:21:54 2016 +0200

    Move to package chisel.packaging

commit 5adfb62d
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 15 11:19:04 2016 +0200

    Move all to package chisel.miscutils

commit 18a5d95e
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 14 18:01:59 2016 +0200

    AxiFifoAdapter: bugfix in burst length

commit 74d116c0
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 14 17:07:58 2016 +0200

    Add example AxiFifoAdapter IP-XACT core for BFM tests

commit fa52f452
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Thu Jul 14 17:06:59 2016 +0200

    AxiSlaveModel: fix off-by-1-bug in burst length

    * AR_LEN can be used directly for countdown var

commit c479cc97
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 13 10:42:22 2016 +0200

    Bugfix: Chisel tests cannot run in parallel

commit 9684a9c2
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 13 10:39:33 2016 +0200

    AxiFifoAdapter: implement AXI mem to FIFO adapter

    * tick-tock buffer approach: one buffer is filled via AXI4 read
      bursts, the other is made available for dequeuing
    * can provide continuous data at full speed, given that the bursts
      finish fast enough
    * also added some unit tests for fixed blocks of memory
    * missing: support for wrap-around (currently via reset)

commit 90c05e9b
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Wed Jul 13 10:38:45 2016 +0200

    AxiSlaveModel: Support for read bursts

commit e6c0e03b
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 12 10:03:55 2016 +0200

    Fix bug of failing tests when running 'sbt test'

    * caused by parallel execution of suites (apparently Chisel does
      not like that)
    * fixed by deactivating parallel and forked executions

commit 28b71a00
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Tue Jul 12 10:03:25 2016 +0200

    Move individual test outputs to own subdir

    * each suite now has a subdir
    * each test has subdir within suite dir

commit 6fc06386
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Jul 11 19:46:28 2016 +0200

    DataWidthConverter: support upsizing

    * upsizing mode (inWidth < outWidth) implemented
    * added unit test support for upsizing

commit fae43067
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Mon Jul 11 09:44:18 2016 +0200

    Implement DataWidthConverter and unit tests

    * basic Decoupled-based data width converter
    * currently only downsizing implemented with endianess selector
    * works, but performance is lackluster yet
    * unit tests cover several interesting combinations in both endianesses

commit 26f72705
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 10 14:45:40 2016 +0200

    AxiSlaveModel: implement mem size parameter

    * memory size can now be controlled independently from addrWidth
      to allow large address spaces

commit 4443aa0c
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sun Jul 10 09:51:58 2016 +0200

    First draft of FifoAxiAdapter

    * adapter to write data from Decoupled-Fifo as AXI4 master
    * base address supplied as input
    * all widths configurable
    * FifoAxiAdapterTest1 uses DecoupledDataSource to test with
      constant data set
    * can also be used to verify against AXI BFMs

commit 4a10a2e7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Sat Jul 9 09:22:45 2016 +0200

    Add CoreDefinition scala class

    * Scala model for core definitions
    * support for reading and writing Json format

commit 5a1f9945
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 8 15:33:36 2016 +0200

    DecoupledDataSource module

    * testing utility: provides fixed data via Decoupled
    * configurable with/without wrap-around
    * unit tests

commit c58f5a12
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 1 07:00:52 2016 +0200

    Bugfix

commit 90e7cca7
Author: Jens Korinth <jkorinth@gmx.net>
Date:   Fri Jul 1 06:38:27 2016 +0200

    Initial version of packaging script

    * based on Python, Vivado IP Integrator
    * produces component.xml with correct reset polarity
parent 76275656
Pipeline #327 failed with stages
in 722 minutes and 47 seconds
......@@ -43,3 +43,4 @@ bin/itapasco
bin/tapasco
bin/tapasco-logviewer
bin/tapasco-reportviewer
/tapasco-status-cache/
This diff is collapsed.
......@@ -15,7 +15,7 @@ set(GCMNDIR "${TAPASCO_HOME}/common")
set(PLATFORMDIR "${TAPASCO_HOME}/platform")
set(LIBPLATFORM_STATIC "${TAPASCO_HOME}/platform/lib/${TAPASCO_TARGET}/static/libplatform.a")
set(BASELINE_SOURCES "${SRCDIR}/tapasco_init.c"
set(AXI4MM_SOURCES "${SRCDIR}/tapasco_init.c"
"${SRCDIR}/tapasco_device.c"
"${SRCDIR}/tapasco_address_map.c")
set(COMMON_SOURCES "${CMNDIR}/tapasco_logging.c"
......@@ -26,6 +26,8 @@ set(COMMON_SOURCES "${CMNDIR}/tapasco_logging.c"
"${CMNDIR}/tapasco_status.c"
"${CMNDIR}/tapasco_version.c"
"${CMNDIR}/tapasco_memory.c"
"${CMNDIR}/tapasco_local_mem.c"
"${GCMNDIR}/src/gen_mem.c"
"${GCMNDIR}/src/gen_queue.c")
set(TAPASCO_LIBS_DIR "${TAPASCO_HOME}/arch/lib")
......@@ -34,9 +36,9 @@ link_directories("${PLATFORMDIR}/lib/${TAPASCO_TARGET}")
add_definitions(-DUSE_ASSERTIONS)
set_source_files_properties(${BASELINE_SOURCES} ${COMMON_SOURCES} PROPERTIES COMPILE_FLAGS "-g -O3 -Wall -Werror -std=gnu11")
add_library(tapasco SHARED ${BASELINE_SOURCES} ${COMMON_SOURCES})
add_library(libtapasco-static STATIC ${BASELINE_SOURCES} ${COMMON_SOURCES} ${LIBPLATFORM_STATIC})
set_source_files_properties(${AXI4MM_SOURCES} ${COMMON_SOURCES} PROPERTIES COMPILE_FLAGS "-g -O3 -Wall -Werror -std=gnu11")
add_library(tapasco SHARED ${AXI4MM_SOURCES} ${COMMON_SOURCES})
add_library(libtapasco-static STATIC ${AXI4MM_SOURCES} ${COMMON_SOURCES} ${LIBPLATFORM_STATIC})
target_link_libraries(tapasco platform atomic pthread)
set_target_properties(libtapasco-static PROPERTIES OUTPUT_NAME tapasco)
......
......@@ -16,9 +16,9 @@
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
# @file axi4mm.tcl
# @brief AXI4 memory mapped master/slave interface based Architectures.
# @author J. Korinth, TU Darmstadt (jk@esa.tu-darmstadt.de)
# @file axi4mm.tcl
# @brief AXI4 memory mapped master/slave interface based Architectures.
# @author J. Korinth, TU Darmstadt (jk@esa.tu-darmstadt.de)
#
namespace eval arch {
namespace export create
......@@ -40,7 +40,7 @@ namespace eval arch {
# Returns a list of the bd_cells of slave interfaces of the threadpool.
proc get_slaves {} {
set inst [current_bd_instance]
current_bd_instance "uArch"
current_bd_instance [::tapasco::subsystem::get arch]
set r [list [get_bd_intf_pins -of [get_bd_cells "in1"] -filter { MODE == "Slave" }]]
current_bd_instance $inst
return $r
......@@ -53,12 +53,12 @@ namespace eval arch {
}
proc get_processing_elements {} {
return [get_bd_cells "uArch/target*"]
return [get_bd_cells -of_objects [::tapasco::subsystem::get arch] -filter { NAME =~ target*}]
}
# Returns a list of interrupt lines from the threadpool.
proc get_irqs {} {
return [get_bd_pins -of_objects [get_bd_cells "uArch"] -filter {TYPE == "intr" && DIR == "O"}]
return [get_bd_pins -of_objects [::tapasco::subsystem::get arch] -filter {TYPE == "intr" && DIR == "O"}]
}
# Checks, if the current composition can be instantiated. Exits script with
......@@ -178,11 +178,11 @@ namespace eval arch {
set ic_ports [list]
set mdist [list]
for {set i 0} {$i < [llength $outs] && $i < $no_masters} {incr i} {
lappend ic_ports [create_bd_intf_pin -mode Master -vlnv "xilinx.com:interface:aximm_rtl:1.0" [format "M_AXI_MEM_%02d" $i]]
lappend ic_ports [create_bd_intf_pin -mode Master -vlnv "xilinx.com:interface:aximm_rtl:1.0" [format "M_MEM_%d" $i]]
lappend mdist 0
}
# distribute masters round-robin on all output ports: mdist holds
# distribute masters round-robin on all output ports: mdist holds
# number of masters for each port
set j 0
for {set i 0} {$i < $no_masters} {incr i} {
......@@ -224,7 +224,7 @@ namespace eval arch {
puts "Creating interconnects toward peripherals ..."
puts " $ic_s slaves to connect to host"
set out_port [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI]
set out_port [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "S_ARCH"]
connect_bd_intf_net $out_port [get_bd_intf_pins -of_objects $in1 -filter {NAME == "S000_AXI"}]
return $in1
......@@ -318,7 +318,7 @@ namespace eval arch {
set i 0
set j 0
set left [llength $ips]
set cc [tapasco::createConcat "xlconcat_$j" [expr "[llength $ips] > 32 ? 32 : [llength $ips]"]]
set cc [tapasco::ip::create_xlconcat "xlconcat_$j" [expr "[llength $ips] > 32 ? 32 : [llength $ips]"]]
lappend arch_irq_concats $cc
foreach ip [lsort $ips] {
foreach pin [get_bd_pins -of $ip -filter { TYPE == intr }] {
......@@ -327,11 +327,11 @@ namespace eval arch {
incr left -1
if {$i > 31} {
set i 0
incr j
if { $left > 0 } {
set cc [tapasco::createConcat "xlconcat_$j" [expr "$left > 32 ? 32 : $left"]]
lappend arch_irq_concats $cc
}
incr j
if { $left > 0 } {
set cc [tapasco::ip::create_xlconcat "xlconcat_$j" [expr "$left > 32 ? 32 : $left"]]
lappend arch_irq_concats $cc
}
}
}
}
......@@ -339,7 +339,7 @@ namespace eval arch {
foreach irq_concat $arch_irq_concats {
# create hierarchical port with correct width
set port [get_bd_pins -of_objects $irq_concat -filter {DIR == "O"}]
set out_port [create_bd_pin -type INTR -dir O -from [get_property LEFT $port] -to [get_property RIGHT $port] "irq_$i"]
set out_port [create_bd_pin -type INTR -dir O -from [get_property LEFT $port] -to [get_property RIGHT $port] "intr_$i"]
connect_bd_net $port $out_port
incr i
}
......@@ -347,44 +347,21 @@ namespace eval arch {
# Connect internal clock lines.
proc arch_connect_clocks {} {
set host_aclk [create_bd_pin -type clk -dir I "host_aclk"]
connect_bd_net $host_aclk [get_bd_pins -filter { NAME == "s_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
set design_aclk [create_bd_pin -type clk -dir I "design_aclk"]
connect_bd_net $design_aclk [get_bd_pins -filter { NAME == "m_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_aclk [get_bd_pins -filter { TYPE == clk && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip_*"}]]
puts " creating clock lines ..."
set memory_aclk [create_bd_pin -type clk -dir I "memory_aclk"]
if {[llength [get_bd_cells -filter {NAME =~ "out*"}]] > 0} {
connect_bd_net $design_aclk [get_bd_pins -filter { NAME == "s_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "out*"}]]
connect_bd_net $memory_aclk [get_bd_pins -filter { NAME == "m_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "out*"}]]
}
connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
[get_bd_pins -of_objects [get_bd_cells] -filter "TYPE == clk && DIR == I"]
}
# Connect internal reset lines.
proc arch_connect_resets {} {
# create hierarchical ports for host interconnect and peripheral resets
set host_ic_arstn [create_bd_pin -type rst -dir I "host_interconnect_aresetn"]
set host_p_arstn [create_bd_pin -type rst -dir I "host_peripheral_aresetn"]
connect_bd_net $host_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $host_p_arstn [get_bd_pins -filter { NAME == "s_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
# create hierarchical ports for design interconnect and peripheral resets
set design_ic_arstn [create_bd_pin -type rst -dir I "design_interconnect_aresetn"]
set design_p_arstn [create_bd_pin -type rst -dir I "design_peripheral_aresetn"]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "m_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { NAME == "m_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { TYPE == rst && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip*"}]]
# create hierarchical ports for memory interconnect and peripheral resets
set memory_ic_arstn [create_bd_pin -type rst -dir I "memory_interconnect_aresetn"]
set memory_p_arstn [create_bd_pin -type rst -dir I "memory_peripheral_aresetn"]
if {[llength [get_bd_cells -filter {NAME =~ "out*"}]] > 0} {
set outs [get_bd_cells -filter {NAME =~ "out*"}]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects $outs]
connect_bd_net $design_p_arstn [get_bd_pins -filter { NAME == "s_peripheral_aresetn" } -of_objects $outs]
connect_bd_net $memory_ic_arstn [get_bd_pins -filter { NAME == "m_interconnect_aresetn" } -of_objects $outs]
connect_bd_net $memory_p_arstn [get_bd_pins -filter { NAME == "m_peripheral_aresetn" } -of_objects $outs]
}
connect_bd_net [tapasco::subsystem::get_port "design" "rst" "interconnect"] \
[get_bd_pins -of_objects [get_bd_cells] -filter "TYPE == rst && NAME =~ *interconnect_aresetn && DIR == I"]
connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
[get_bd_pins -of_objects [get_bd_cells -of_objects [current_bd_instance .]] -filter "TYPE == rst && NAME =~ *peripheral_aresetn && DIR == I"] \
[get_bd_pins -filter { TYPE == rst && DIR == I && CONFIG.POLARITY != ACTIVE_HIGH } -of_objects [get_bd_cells -filter {NAME =~ "target_ip*"}]]
set active_high_resets [get_bd_pins -of_objects [get_bd_cells] -filter "TYPE == rst && DIR == I && CONFIG.POLARITY == ACTIVE_HIGH"]
if {[llength $active_high_resets] > 0} {
connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "reset"] $active_high_resets
}
}
# Instantiates the architecture.
......@@ -397,7 +374,7 @@ namespace eval arch {
}
# create hierarchical group
set group [create_bd_cell -type hier "uArch"]
set group [tapasco::subsystem::create "arch"]
set instance [current_bd_instance .]
current_bd_instance $group
......
......@@ -30,14 +30,16 @@ namespace eval debug {
set interfaces {}
set debug [tapasco::get_feature "Debug"]
puts "Debug feature enabled: $debug"
dict with debug {
set num_ifs [llength $interfaces]
if {$num_ifs > 0} {
set i 0
foreach ifs $interfaces {
puts " found interface def: $ifs"
if {[llength $ifs] == 3} {
set s_ila [tapasco::createSystemILA "SILA_$i" $num_ifs $depth $stages]
puts " ifs = $ifs"
set s_ila [tapasco::ip::create_system_ila "SILA_$i" $num_ifs $depth $stages]
puts " create System ILA SILA_$i for $num_ifs interfaces with depth $depth and $stages stages"
set intf [get_bd_intf_pins [lindex $ifs 0]]
set clk [get_bd_pins [lindex $ifs 1]]
set rst [get_bd_pins [lindex $ifs 2]]
......@@ -56,4 +58,4 @@ namespace eval debug {
}
}
tapasco::register_plugin "arch::debug::debug_feature" "post-bd"
tapasco::register_plugin "arch::debug::debug_feature" "pre-wrapper"
......@@ -45,7 +45,7 @@ namespace eval full_axi_wrapper {
foreach fs $full_slave_ifs {
# create slave port
set saxi_port [create_bd_intf_pin -vlnv "xilinx.com:interface:aximm_rtl:1.0" -mode Slave "S_AXI_LITE_$si"]
set conv [tapasco::createProtocolConverter "conv_$si" "AXI4LITE" [get_property CONFIG.PROTOCOL $fs]]
set conv [tapasco::ip::create_proto_conv "conv_$si" "AXI4LITE" [get_property CONFIG.PROTOCOL $fs]]
connect_bd_intf_net $saxi_port [get_bd_intf_pins -of_objects $conv -filter {MODE == Slave}]
connect_bd_intf_net [get_bd_intf_pins -filter {MODE == Master} -of_objects $conv] $fs
incr si
......
......@@ -30,6 +30,7 @@
#include <tapasco_scheduler.h>
#include <tapasco_logging.h>
#include <tapasco_status.h>
#include <tapasco_local_mem.h>
#include <platform.h>
#include <platform_errors.h>
......@@ -40,8 +41,24 @@ struct tapasco_dev_ctx {
tapasco_ctx_t *ctx;
tapasco_dev_id_t id;
tapasco_status_t *status;
tapasco_local_mem_t *lmem;
};
tapasco_functions_t *tapasco_device_functions(tapasco_dev_ctx_t *ctx)
{
return ctx->functions;
}
tapasco_status_t *tapasco_device_status(tapasco_dev_ctx_t *ctx)
{
return ctx->status;
}
tapasco_local_mem_t *tapasco_device_local_mem(tapasco_dev_ctx_t *ctx)
{
return ctx->lmem;
}
/** Interrupt handler callback. */
void irq_handler(int const event);
......@@ -65,6 +82,7 @@ tapasco_res_t tapasco_create_device(tapasco_ctx_t *ctx, tapasco_dev_id_t const d
res = res == TAPASCO_SUCCESS ? tapasco_functions_init(p->status,
&p->functions) : res;
res = res == TAPASCO_SUCCESS ? tapasco_jobs_init(&p->jobs) : res;
res = res == TAPASCO_SUCCESS ? tapasco_local_mem_init(p->status, &p->lmem) : res;
if (res != TAPASCO_SUCCESS) return res;
p->ctx = ctx;
p->id = dev_id;
......@@ -80,6 +98,7 @@ tapasco_res_t tapasco_create_device(tapasco_ctx_t *ctx, tapasco_dev_id_t const d
void tapasco_destroy_device(tapasco_ctx_t *ctx, tapasco_dev_ctx_t *dev_ctx)
{
platform_stop(0);
tapasco_local_mem_deinit(dev_ctx->lmem);
tapasco_jobs_deinit(dev_ctx->jobs);
tapasco_functions_deinit(dev_ctx->functions);
tapasco_status_deinit(dev_ctx->status);
......@@ -148,6 +167,15 @@ tapasco_res_t tapasco_device_job_set_arg(tapasco_dev_ctx_t *dev_ctx,
return tapasco_jobs_set_arg(dev_ctx->jobs, j_id, arg_idx, arg_len, arg_value);
}
tapasco_res_t tapasco_device_job_set_arg_transfer(tapasco_dev_ctx_t *dev_ctx,
tapasco_job_id_t const job_id, uint32_t arg_idx,
size_t const arg_len, void *arg_value,
tapasco_device_alloc_flag_t const flags)
{
return tapasco_jobs_set_arg_transfer(dev_ctx->jobs, job_id, arg_idx,
arg_len, arg_value, flags);
}
tapasco_res_t tapasco_device_job_get_return(tapasco_dev_ctx_t *dev_ctx,
tapasco_job_id_t const j_id, size_t const ret_len,
void *ret_value)
......
namespace eval arch {
namespace export create
namespace export get_address_map
# Returns the address map of the current composition.
# Format: <INTF> -> <BASE ADDR> <RANGE> <KIND>
# Kind is either memory, register or master.
# Must be implemented by Platforms.
proc get_address_map {offset} {
if {$offset == ""} { set offset [platform::get_pe_base_address] }
set ret [dict create]
set pes [lsort [get_processing_elements]]
foreach pe $pes {
puts " processing $pe registers ..."
set usrs [lsort [get_bd_addr_segs $pe/* -filter { USAGE == register }]]
for {set i 0} {$i < [llength $usrs]} {incr i; incr offset 0x10000} {
set seg [lindex $usrs $i]
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind register"
}
puts " processing $pe memories ..."
set usrs [lsort [get_bd_addr_segs $pe/* -filter { USAGE == memory }]]
for {set i 0} {$i < [llength $usrs]} {incr i; incr offset 0x10000} {
set seg [lindex $usrs $i]
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind memory"
}
puts " processing $pe masters ..."
set masters [lsort [tapasco::get_aximm_interfaces $pe]]
foreach intf $masters {
set space [get_bd_addr_spaces -of_objects $intf]
if {$space != {}} {
set off [get_property OFFSET $space]
if {$off == ""} { set off 0 }
set range [get_property RANGE $space]
if {$range == ""} { error "no range found on $space for $intf!" }
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $off $range] kind master"
} else {
puts " no address spaces found on $intf, continuing ..."
}
}
}
return $ret
}
}
......@@ -42,6 +42,8 @@
//! License along with Tapasco. If not, see
//! <http://www.gnu.org/licenses/>.
//! @details ### Change Log ###
//! - Version 1.4 (jk)
//! + added support for pe-local memories
//! - Version 1.3 (jk)
//! + added device capabilities
//! - Version 1.2.1 (jk)
......@@ -115,7 +117,9 @@ typedef enum {
/** Flags for memory allocation (implementation defined). **/
typedef enum {
/** no flags **/
TAPASCO_DEVICE_ALLOC_FLAGS_NONE = 0
TAPASCO_DEVICE_ALLOC_FLAGS_NONE = 0,
/** PE-local, i.e., only accessible from scheduled PE **/
TAPASCO_DEVICE_ALLOC_FLAGS_PE_LOCAL = 1,
} tapasco_device_alloc_flag_t;
/** Flags for bitstream loading (implementation defined). **/
......@@ -132,6 +136,8 @@ typedef enum {
TAPASCO_DEVICE_COPY_BLOCKING = 0,
/** return immediately after transfer was scheduled **/
TAPASCO_DEVICE_COPY_NONBLOCKING = 1,
/** copy to local memory **/
TAPASCO_DEVICE_COPY_PE_LOCAL = 2,
} tapasco_device_copy_flag_t;
/** Flags for calls to tapasco_device_acquire_job_id. **/
......@@ -170,7 +176,7 @@ typedef enum {
* @{
**/
#define TAPASCO_API_VERSION "1.3"
#define TAPASCO_API_VERSION "1.4"
/**
* Returns the version string of the library.
......@@ -297,8 +303,9 @@ tapasco_res_t tapasco_device_load_bitstream(tapasco_dev_ctx_t *dev_ctx, size_t c
* @param flags device memory allocation flags
* @return TAPASCO_SUCCESS if successful, error code otherwise
**/
tapasco_res_t tapasco_device_alloc(tapasco_dev_ctx_t *dev_ctx, tapasco_handle_t *handle,
size_t const len, tapasco_device_alloc_flag_t const flags);
tapasco_res_t tapasco_device_alloc(tapasco_dev_ctx_t *dev_ctx,
tapasco_handle_t *handle, size_t const len,
tapasco_device_alloc_flag_t const flags, ...);
/**
* Frees a previously allocated chunk of device memory.
......@@ -307,7 +314,7 @@ tapasco_res_t tapasco_device_alloc(tapasco_dev_ctx_t *dev_ctx, tapasco_handle_t
* @param flags device memory allocation flags
**/
void tapasco_device_free(tapasco_dev_ctx_t *dev_ctx, tapasco_handle_t handle,
tapasco_device_alloc_flag_t const flags);
tapasco_device_alloc_flag_t const flags, ...);
/**
* Copys memory from main memory to the FPGA device.
......@@ -318,9 +325,9 @@ void tapasco_device_free(tapasco_dev_ctx_t *dev_ctx, tapasco_handle_t handle,
* @param flags flags for copy operation, e.g., TAPASCO_COPY_NONBLOCKING
* @return TAPASCO_SUCCESS if copy was successful, TAPASCO_FAILURE otherwise
**/
tapasco_res_t tapasco_device_copy_to(tapasco_dev_ctx_t *dev_ctx, void const *src,
tapasco_handle_t dst, size_t len,
tapasco_device_copy_flag_t const flags);
tapasco_res_t tapasco_device_copy_to(tapasco_dev_ctx_t *dev_ctx,
void const *