Commit 1b830fc0 authored by Jaco Hofmann's avatar Jaco Hofmann
Browse files

Merge branch 'sfp' into '2018.2'

Add modularized SFP support in Tapasco

See merge request !29
parents a66b236d 53e4ace5
Pipeline #828 passed with stage
in 8 minutes and 13 seconds
......@@ -36,4 +36,5 @@ dict set stdcomps axi_iic vlnv "xilinx.com:ip:axi_iic:2.0"
dict set stdcomps util_buf vlnv "xilinx.com:ip:util_ds_buf:2.1"
dict set stdcomps pciebridgetolite vlnv "esa.informatik.tu-darmstadt.de:user:PCIeBridgeToLite:1.0"
dict set stdcomps pciebridgetolite_x16 vlnv "esa.informatik.tu-darmstadt.de:user:PCIeBridgeToLite_x16:1.0"
dict set stdcomps hsa_wrapper vlnv "esa.informatik.tu-darmstadt.de:user:HSAWrapper:1.0"
dict set stdcomps hsa_wrapper vlnv "esa.informatik.tu-darmstadt.de:user:HSAWrapper:1.0"
dict set stdcomps axis_arbiter vlnv "esa.informatik.tu-darmstadt.de:user:AXIS_Arbiter:1.0"
package AXI4_Stream;
import GetPut :: *;
import FIFOF :: *;
import SpecialFIFOs :: *;
import Connectable :: *;
// Project specific
/*
=============
Types
=============
*/
typedef struct {
Bit#(datawidth) data;
Bit#(userwidth) user;
Bit#(TDiv#(datawidth, 8)) keep;
Bit#(4) dest;
Bool last;
} AXI4_Stream_Pkg#(numeric type datawidth, numeric type userwidth) deriving(Bits, Eq, FShow);
typedef AXI4_Stream_Pkg#(32, 1) AXI4_Stream_Pkg_32;
typedef AXI4_Stream_Pkg#(64, 1) AXI4_Stream_Pkg_64;
typedef AXI4_Stream_Pkg#(128, 1) AXI4_Stream_Pkg_128;
typedef AXI4_Stream_Pkg#(256, 1) AXI4_Stream_Pkg_256;
typedef AXI4_Stream_Pkg#(512, 1) AXI4_Stream_Pkg_512;
/*
========================
AXI 4 Stream Read
========================
*/
(* always_ready, always_enabled *)
interface AXI4_Stream_Rd_Fab#(numeric type datawidth, numeric type userwidth);
method Bool tready;
(*prefix=""*)method Action ptvalid((*port="tvalid"*) Bool tvalid);
(*prefix=""*)method Action ptdata((*port="tdata"*)Bit#(datawidth) data);
(*prefix=""*)method Action ptuser((*port="tuser"*)Bit#(userwidth) user);
(*prefix=""*)method Action ptkeep((*port="tkeep"*)Bit#(TDiv#(datawidth, 8)) keep);
(*prefix=""*)method Action ptDest((*port="tDest"*)Bit#(4) dest);
(*prefix=""*)method Action ptlast((*port="tlast"*)Bool last);
endinterface
interface AXI4_Stream_Rd#(numeric type datawidth, numeric type userwidth);
(* prefix="" *)
interface AXI4_Stream_Rd_Fab#(datawidth, userwidth) fab;
interface Get#(AXI4_Stream_Pkg#(datawidth, userwidth)) pkg;
endinterface
module mkAXI4_Stream_Rd#(Integer bufferSize)(AXI4_Stream_Rd#(datawidth, userwidth))
provisos(Div#(datawidth, 8, keepwidth));
Wire#(Bool) tvalidIn <- mkBypassWire();
Wire#(Bit#(datawidth)) dataIn <- mkBypassWire();
Wire#(Bit#(userwidth)) userIn <- mkBypassWire();
Wire#(Bit#(keepwidth)) keepIn <- mkBypassWire();
Wire#(Bit#(4)) destIn <- mkBypassWire();
Wire#(Bool) lastIn <- mkBypassWire();
FIFOF#(AXI4_Stream_Pkg#(datawidth, userwidth)) in <- mkSizedFIFOF(bufferSize);
if(bufferSize == 1)
in <- mkPipelineFIFOF();
if(bufferSize == 2)
in <- mkFIFOF();
rule writeFIFO if(tvalidIn && in.notFull());
AXI4_Stream_Pkg#(datawidth, userwidth) s;
s.data = dataIn;
s.user = userIn;
s.keep = keepIn;
s.dest = destIn;
s.last = lastIn;
in.enq(s);
endrule
interface Get pkg = toGet(in);
interface AXI4_Stream_Rd_Fab fab;
interface tready = in.notFull();
interface ptvalid = tvalidIn._write;
interface ptdata = dataIn._write;
interface ptuser = userIn._write;
interface ptkeep = keepIn._write;
interface ptDest = destIn._write;
interface ptlast = lastIn._write;
endinterface
endmodule
/*
========================
AXI 4 Stream Write
========================
*/
(* always_ready, always_enabled *)
interface AXI4_Stream_Wr_Fab#(numeric type datawidth, numeric type userwidth);
method Bool tvalid;
(*prefix=""*)method Action ptready((*port="tready"*) Bool tr);
method Bit#(datawidth) tdata;
method Bool tlast;
method Bit#(userwidth) tuser;
method Bit#(TDiv#(datawidth, 8)) tkeep;
method Bit#(4) tDest;
endinterface
interface AXI4_Stream_Wr#(numeric type datawidth, numeric type userwidth);
(* prefix="" *)
interface AXI4_Stream_Wr_Fab#(datawidth, userwidth) fab;
interface Put#(AXI4_Stream_Pkg#(datawidth, userwidth)) pkg;
endinterface
module mkAXI4_Stream_Wr#(Integer bufferSize)(AXI4_Stream_Wr#(datawidth, userwidth))
provisos(Div#(datawidth, 8, keepwidth));
FIFOF#(AXI4_Stream_Pkg#(datawidth, userwidth)) out <- mkSizedFIFOF(bufferSize);
if(bufferSize == 1)
out <- mkPipelineFIFOF();
if(bufferSize == 2)
out <- mkFIFOF();
Wire#(Bool) treadyIn <- mkBypassWire;
Wire#(Bool) tvalidOut <- mkDWire(False);
Wire#(Bit#(datawidth)) tdataOut <- mkDWire(unpack(0));
Wire#(Bit#(userwidth)) tuserOut <- mkDWire(unpack(0));
Wire#(Bit#(keepwidth)) tkeepOut <- mkDWire(unpack(0));
Wire#(Bit#(4)) tdestOut <- mkDWire(unpack(0));
Wire#(Bool) tlastOut <- mkDWire(False);
rule deqFIFO if(treadyIn && out.notEmpty());
out.deq();
endrule
rule writeOutputs;
tdataOut <= out.first().data();
tlastOut <= out.first().last();
tuserOut <= out.first().user();
tkeepOut <= out.first().keep();
tdestOut <= out.first().dest();
endrule
interface AXI4_Stream_Wr_Fab fab;
interface tvalid = out.notEmpty();
interface ptready = treadyIn._write();
interface tdata = tdataOut;
interface tlast = tlastOut;
interface tuser = tuserOut;
interface tkeep = tkeepOut;
interface tDest = tdestOut;
endinterface
interface Put pkg = toPut(out);
endmodule
/*
========================
Connectable
========================
*/
instance Connectable#(AXI4_Stream_Wr_Fab#(datawidth, userwidth), AXI4_Stream_Rd_Fab#(datawidth, userwidth));
module mkConnection#(AXI4_Stream_Wr_Fab#(datawidth, userwidth) wr, AXI4_Stream_Rd_Fab#(datawidth, userwidth) rd)(Empty);
rule forward1;
wr.ptready(rd.tready());
endrule
rule forward2;
rd.ptvalid(wr.tvalid());
endrule
rule forward3;
rd.ptdata(wr.tdata());
endrule
rule forward4;
rd.ptlast(wr.tlast());
endrule
rule forward5;
rd.ptuser(wr.tuser());
endrule
rule forward6;
rd.ptkeep(wr.tkeep());
endrule
rule forward7;
rd.ptDest(wr.tDest());
endrule
endmodule
endinstance
endpackage
package AXIS_Arbiter;
import AXI4_Stream :: *;
import GetPut :: *;
interface Arbiter;
interface AXI4_Stream_Wr_Fab#(64,1) axis_M;
interface AXI4_Stream_Rd_Fab#(64,1) axis_S;
(* always_ready, always_enabled, prefix = "" *)
method Action arbiter_turnover((* port = "maxClients" *) Bit#(5) b);
endinterface
module mkAXIS_Arbiter(Arbiter);
AXI4_Stream_Wr#(64, 1) streamOut <- mkAXI4_Stream_Wr(1);
AXI4_Stream_Rd#(64, 1) streamIn <- mkAXI4_Stream_Rd(1);
//---------------------------------------------------
Wire#(Bit#(5)) turnover <- mkDWire(0);
Reg#(Bit#(5)) arbiter <- mkReg(0);
//---------------------------------------------------
rule axiStream1;
AXI4_Stream_Pkg_64 in <- streamIn.pkg.get();
in.dest = arbiter[3:0];
streamOut.pkg.put(in);
arbiter <= in.last? (arbiter+1) % turnover : arbiter;
endrule
method arbiter_turnover = turnover._write;
interface AXI4_Stream_Receive axis_S = streamIn.fab;
interface AXI4_Stream_Send axis_M = streamOut.fab;
endmodule
endpackage
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
This diff is collapsed.
//
// Generated by Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21)
//
// On Fri Sep 7 15:31:51 CEST 2018
//
//
// Ports:
// Name I/O size props
// axis_M_tvalid O 1
// axis_M_tdata O 64
// axis_M_tlast O 1
// axis_M_tuser O 1
// axis_M_tkeep O 8
// axis_M_tDest O 4
// axis_S_tready O 1
// CLK I 1 clock
// RST_N I 1 reset
// axis_M_tready I 1
// axis_S_tvalid I 1
// axis_S_tdata I 64
// axis_S_tuser I 1
// axis_S_tkeep I 8
// axis_S_tDest I 4
// axis_S_tlast I 1
// maxClients I 5
//
// Combinational paths from inputs to outputs:
// axis_M_tready -> axis_S_tready
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkAXIS_Arbiter(CLK,
RST_N,
axis_M_tvalid,
axis_M_tready,
axis_M_tdata,
axis_M_tlast,
axis_M_tuser,
axis_M_tkeep,
axis_M_tDest,
axis_S_tready,
axis_S_tvalid,
axis_S_tdata,
axis_S_tuser,
axis_S_tkeep,
axis_S_tDest,
axis_S_tlast,
maxClients);
input CLK;
input RST_N;
// value method axis_M_tvalid
output axis_M_tvalid;
// action method axis_M_ptready
input axis_M_tready;
// value method axis_M_tdata
output [63 : 0] axis_M_tdata;
// value method axis_M_tlast
output axis_M_tlast;
// value method axis_M_tuser
output axis_M_tuser;
// value method axis_M_tkeep
output [7 : 0] axis_M_tkeep;
// value method axis_M_tDest
output [3 : 0] axis_M_tDest;
// value method axis_S_tready
output axis_S_tready;
// action method axis_S_ptvalid
input axis_S_tvalid;
// action method axis_S_ptdata
input [63 : 0] axis_S_tdata;
// action method axis_S_ptuser
input axis_S_tuser;
// action method axis_S_ptkeep
input [7 : 0] axis_S_tkeep;
// action method axis_S_ptDest
input [3 : 0] axis_S_tDest;
// action method axis_S_ptlast
input axis_S_tlast;
// action method arbiter_turnover
input [4 : 0] maxClients;
// signals for module outputs
wire [63 : 0] axis_M_tdata;
wire [7 : 0] axis_M_tkeep;
wire [3 : 0] axis_M_tDest;
wire axis_M_tlast, axis_M_tuser, axis_M_tvalid, axis_S_tready;
// inlined wires
wire [78 : 0] streamIn_in_1_rv$port1__read,
streamIn_in_1_rv$port1__write_1,
streamIn_in_1_rv$port2__read,
streamOut_out_1_rv$port1__read,
streamOut_out_1_rv$port1__write_1,
streamOut_out_1_rv$port2__read;
wire streamIn_in_1_rv$EN_port0__write,
streamIn_in_1_rv$EN_port1__write,
streamOut_out_1_rv$EN_port0__write,
streamOut_out_1_rv$EN_port1__write;
// register arbiter
reg [4 : 0] arbiter;
wire [4 : 0] arbiter$D_IN;
wire arbiter$EN;
// register streamIn_in_1_rv
reg [78 : 0] streamIn_in_1_rv;
wire [78 : 0] streamIn_in_1_rv$D_IN;
wire streamIn_in_1_rv$EN;
// register streamOut_out_1_rv
reg [78 : 0] streamOut_out_1_rv;
wire [78 : 0] streamOut_out_1_rv$D_IN;
wire streamOut_out_1_rv$EN;
// ports of submodule streamIn_in
wire [77 : 0] streamIn_in$D_IN;
wire streamIn_in$CLR, streamIn_in$DEQ, streamIn_in$ENQ;
// ports of submodule streamOut_out
wire [77 : 0] streamOut_out$D_IN;
wire streamOut_out$CLR, streamOut_out$DEQ, streamOut_out$ENQ;
// remaining internal signals
wire [4 : 0] arbiter_1_PLUS_1_6_REM_IF_turnover_whas__7_THE_ETC___d40,
x__h2285;
// value method axis_M_tvalid
assign axis_M_tvalid = streamOut_out_1_rv[78] ;
// value method axis_M_tdata
assign axis_M_tdata =
streamOut_out_1_rv[78] ? streamOut_out_1_rv[77:14] : 64'd0 ;
// value method axis_M_tlast
assign axis_M_tlast = streamOut_out_1_rv[78] && streamOut_out_1_rv[0] ;
// value method axis_M_tuser
assign axis_M_tuser = streamOut_out_1_rv[78] && streamOut_out_1_rv[13] ;
// value method axis_M_tkeep
assign axis_M_tkeep =
streamOut_out_1_rv[78] ? streamOut_out_1_rv[12:5] : 8'd0 ;
// value method axis_M_tDest
assign axis_M_tDest =
streamOut_out_1_rv[78] ? streamOut_out_1_rv[4:1] : 4'd0 ;
// value method axis_S_tready
assign axis_S_tready = !streamIn_in_1_rv$port1__read[78] ;
// submodule streamIn_in
FIFO1 #(.width(32'd78), .guarded(32'd1)) streamIn_in(.RST(RST_N),
.CLK(CLK),
.D_IN(streamIn_in$D_IN),
.ENQ(streamIn_in$ENQ),
.DEQ(streamIn_in$DEQ),
.CLR(streamIn_in$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule streamOut_out
FIFO1 #(.width(32'd78), .guarded(32'd1)) streamOut_out(.RST(RST_N),
.CLK(CLK),
.D_IN(streamOut_out$D_IN),
.ENQ(streamOut_out$ENQ),
.DEQ(streamOut_out$DEQ),
.CLR(streamOut_out$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// inlined wires
assign streamOut_out_1_rv$EN_port0__write =