Commit 1de898c4 authored by Jens Korinth's avatar Jens Korinth
Browse files

Fix compilation issues in ProgrammableMaster

parent 72ee604c
...@@ -36,3 +36,4 @@ lazy val root = (project in file(".")).dependsOn(packaging, miscutils, miscutils ...@@ -36,3 +36,4 @@ lazy val root = (project in file(".")).dependsOn(packaging, miscutils, miscutils
cleanFiles += (baseDirectory.value / "test") cleanFiles += (baseDirectory.value / "test")
aggregate in test := false
...@@ -24,7 +24,7 @@ class ProgrammableMaster(action: Seq[MasterAction]) ...@@ -24,7 +24,7 @@ class ProgrammableMaster(action: Seq[MasterAction])
val w_resp = Decoupled(UInt(2.W)) val w_resp = Decoupled(UInt(2.W))
}) })
val cnt = Reg(UInt(log2Ceil(action.length + 1).W)) // current action; last value indicates completion val cnt = RegInit(UInt(log2Ceil(action.length + 1).W), init = 0.U) // current action; last value indicates completion
val s_addr :: s_wtransfer :: s_rtransfer :: s_response :: s_idle :: Nil = Enum(5) val s_addr :: s_wtransfer :: s_rtransfer :: s_response :: s_idle :: Nil = Enum(5)
val state = RegInit(s_addr) val state = RegInit(s_addr)
val w_data = Reg(UInt(axi.dataWidth)) val w_data = Reg(UInt(axi.dataWidth))
...@@ -50,53 +50,48 @@ class ProgrammableMaster(action: Seq[MasterAction]) ...@@ -50,53 +50,48 @@ class ProgrammableMaster(action: Seq[MasterAction])
io.finished := cnt === action.length.U io.finished := cnt === action.length.U
when (reset) { // always assign address from current action
cnt := 0.U for (i <- 0 until action.length) {
when (i.U === cnt) {
io.maxi.readAddr.bits.addr := action(i).addr.U
io.maxi.writeAddr.bits.addr := action(i).addr.U
}
} }
.otherwise {
// always assign address from current action when (state === s_addr) {
for (i <- 0 until action.length) { for (i <- 0 until action.length) {
when (i.U === cnt) { when (i.U === cnt) {
io.maxi.readAddr.bits.addr := action(i).addr.U io.maxi.readAddr.valid := action(i).isRead.B
io.maxi.writeAddr.bits.addr := action(i).addr.U io.maxi.writeAddr.valid := (! action(i).isRead).B
} action(i).value map { v => w_data := v.U }
}
when (state === s_addr) {
for (i <- 0 until action.length) {
when (i.U === cnt) {
io.maxi.readAddr.valid := action(i).isRead.B
io.maxi.writeAddr.valid := (! action(i).isRead).B
action(i).value map { v => w_data := v.U }
}
} }
when (io.maxi.readAddr.ready && io.maxi.readAddr.valid) { state := s_rtransfer }
when (io.maxi.writeAddr.ready && io.maxi.writeAddr.valid) { state := s_wtransfer }
when (cnt === action.length.U) { state := s_idle }
} }
when (io.maxi.readAddr.ready && io.maxi.readAddr.valid) { state := s_rtransfer }
when (io.maxi.writeAddr.ready && io.maxi.writeAddr.valid) { state := s_wtransfer }
when (cnt === action.length.U) { state := s_idle }
}
when (state === s_rtransfer) { when (state === s_rtransfer) {
for (i <- 0 until action.length) { for (i <- 0 until action.length) {
val readReady = action(i).isRead.B && io.maxi.readData.ready && io.maxi.readData.valid val readReady = action(i).isRead.B && io.maxi.readData.ready && io.maxi.readData.valid
when (i.U === cnt && readReady) { when (i.U === cnt && readReady) {
q.io.enq.valid := io.maxi.readData.bits.resp === 0.U // response OKAY q.io.enq.valid := io.maxi.readData.bits.resp === 0.U // response OKAY
cnt := cnt + 1.U cnt := cnt + 1.U
state := s_addr state := s_addr
}
} }
} }
}
when (state === s_wtransfer) { when (state === s_wtransfer) {
for (i <- 0 until action.length) { for (i <- 0 until action.length) {
val writeReady = (!action(i).isRead).B && io.maxi.writeData.ready && io.maxi.writeData.valid val writeReady = (!action(i).isRead).B && io.maxi.writeData.ready && io.maxi.writeData.valid
when (i.U === cnt && writeReady) { when (i.U === cnt && writeReady) {
cnt := cnt + 1.U cnt := cnt + 1.U
state := s_response state := s_response
}
} }
} }
when (state === s_response && io.maxi.writeResp.valid) { state := s_addr }
} }
when (state === s_response && io.maxi.writeResp.valid) { state := s_addr }
} }
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