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tapasco
tapasco
Commits
2785e65e
Commit
2785e65e
authored
Jul 07, 2017
by
Jaco Hofmann
1
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Eases timing in the wait for completion path
parent
5029ff2f
Changes
3
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3 changed files
with
61 additions
and
70 deletions
+61
-70
common/ip/MSIXIntrCtrl/component.xml
common/ip/MSIXIntrCtrl/component.xml
+5
-5
common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc
common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc
+0
-1
common/ip/MSIXIntrCtrl/src/mkMSIXIntrCtrl.v
common/ip/MSIXIntrCtrl/src/mkMSIXIntrCtrl.v
+56
-64
No files found.
common/ip/MSIXIntrCtrl/component.xml
View file @
2785e65e
...
...
@@ -427,7 +427,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>
viewChecksum
</spirit:name>
<spirit:value>
558b72a
a
</spirit:value>
<spirit:value>
e07e9e3
a
</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
...
...
@@ -443,7 +443,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>
viewChecksum
</spirit:name>
<spirit:value>
558b72a
a
</spirit:value>
<spirit:value>
e07e9e3
a
</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
...
...
@@ -1267,7 +1267,7 @@
<spirit:file>
<spirit:name>
src/mkMSIXIntrCtrl.v
</spirit:name>
<spirit:fileType>
verilogSource
</spirit:fileType>
<spirit:userFileType>
CHECKSUM_
7049b426
</spirit:userFileType>
<spirit:userFileType>
CHECKSUM_
f02cbad3
</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
...
...
@@ -1323,7 +1323,7 @@
<xilinx:displayName>
MSIXIntrCtrl
</xilinx:displayName>
<xilinx:definitionSource>
package_project
</xilinx:definitionSource>
<xilinx:coreRevision>
1
</xilinx:coreRevision>
<xilinx:coreCreationDateTime>
2017-07-0
5T16:28:24
Z
</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>
2017-07-0
7T08:36:48
Z
</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag
xilinx:name=
"nopcore"
/>
</xilinx:tags>
...
...
@@ -1333,7 +1333,7 @@
<xilinx:checksum
xilinx:scope=
"busInterfaces"
xilinx:value=
"a9103989"
/>
<xilinx:checksum
xilinx:scope=
"addressSpaces"
xilinx:value=
"39f94240"
/>
<xilinx:checksum
xilinx:scope=
"memoryMaps"
xilinx:value=
"2b2da2c0"
/>
<xilinx:checksum
xilinx:scope=
"fileGroups"
xilinx:value=
"
057aaeb0
"
/>
<xilinx:checksum
xilinx:scope=
"fileGroups"
xilinx:value=
"
ecf6481e
"
/>
<xilinx:checksum
xilinx:scope=
"ports"
xilinx:value=
"19368f77"
/>
<xilinx:checksum
xilinx:scope=
"parameters"
xilinx:value=
"4b2b81b7"
/>
</xilinx:packagingInfo>
...
...
common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc
deleted
100644 → 0
View file @
5029ff2f
set_false_path -through [get_pins system_i/InterruptControl/msix_intr_ctrl/interrupt*]
common/ip/MSIXIntrCtrl/src/mkMSIXIntrCtrl.v
View file @
2785e65e
//
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
//
// On
Wed Jul 5 18:26:0
3 CEST 2017
// On
Fri Jul 7 10:35:3
3 CEST 2017
//
//
// Ports:
...
...
@@ -344,8 +344,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
nextInterrupt_rv$port1__write_1,
nextInterrupt_rv$port2__read;
wire [1 : 0] msixTable_serverAdapterB_s1_1$wget;
wire msixTable_serverAdapterA_outData_deqCalled$whas,
msixTable_serverAdapterA_outData_enqData$whas,
wire msixTable_serverAdapterA_outData_enqData$whas,
msixTable_serverAdapterA_outData_outData$whas,
msixTable_serverAdapterB_cnt_1$whas,
msixTable_serverAdapterB_outData_enqData$whas,
...
...
@@ -357,9 +356,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
s_config_writeSlave_addrIn_rv$EN_port1__write,
s_config_writeSlave_dataIn_rv$EN_port0__write,
s_config_writeSlave_dataIn_rv$EN_port1__write,
send_pending$EN_port0__write,
send_pending$port1__read,
send_pending$port2__read,
writeMaster_addrOut_rv$EN_port0__write,
writeMaster_addrOut_rv$EN_port1__write,
writeMaster_dataOut_rv$EN_port0__write,
...
...
@@ -3508,7 +3504,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
MUX_s_config_readSlave_out$enq_1__VAL_4,
MUX_s_config_readSlave_out$enq_1__VAL_5,
MUX_s_config_readSlave_out$enq_1__VAL_6;
wire MUX_msixTable_memory$b_put_
1
__SEL_1,
wire MUX_msixTable_memory$b_put_
2
__SEL_1,
MUX_pba_vector_0$write_1__SEL_1,
MUX_pba_vector_1$write_1__SEL_1,
MUX_pba_vector_10$write_1__SEL_1,
...
...
@@ -3641,14 +3637,15 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
MUX_pba_vector_97$write_1__SEL_1,
MUX_pba_vector_98$write_1__SEL_1,
MUX_pba_vector_99$write_1__SEL_1,
MUX_s_config_readBusy$write_1__SEL_1;
MUX_s_config_readBusy$write_1__SEL_1,
MUX_send_pending$write_1__SEL_2;
// remaining internal signals
reg [31 : 0] v__h2837
4
;
reg [31 : 0] v__h2837
3
;
reg SEL_ARR_vector_control_0_81_vector_control_1_8_ETC___d315;
wire [63 : 0] x_addr__h93
62
8;
wire [31 : 0] r__h2853
9
;
wire [15 : 0] addr__h2872
2, i__h28619, i__h54995
;
wire [63 : 0] x_addr__h93
46
8;
wire [31 : 0] r__h2853
8
;
wire [15 : 0] addr__h2872
1, i__h28618, i__h54994
;
wire [7 : 0] IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1830,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1832,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1833,
...
...
@@ -3698,7 +3695,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1739;
wire [2 : 0] msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32,
msixTable_serverAdapterB_cnt_3_PLUS_IF_msixTab_ETC___d89;
wire [1 : 0] ab__h1881
4
;
wire [1 : 0] ab__h1881
3
;
wire NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1015,
NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1315,
NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d931,
...
...
@@ -4047,8 +4044,8 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
// rule RL_s_config_axiReadSpecialRangeDelayedIsHandled_1
assign WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 =
s_config_readSlave_in$EMPTY_N && i__h2861
9
>= 16'd32768 &&
i__h2861
9
< 16'd32788 ;
s_config_readSlave_in$EMPTY_N && i__h2861
8
>= 16'd32768 &&
i__h2861
8
< 16'd32788 ;
// rule RL_s_config_axiReadSpecialIsHandled
assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled =
...
...
@@ -4073,8 +4070,8 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
// rule RL_s_config_axiReadSpecialRangeDelayed_1
assign WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed_1 =
s_config_readSlave_in$EMPTY_N && pbaRet$FULL_N &&
i__h2861
9
>= 16'd32768 &&
i__h2861
9
< 16'd32788 &&
i__h2861
8
>= 16'd32768 &&
i__h2861
8
< 16'd32788 &&
!s_config_readBusy ;
// rule RL_s_config_axiReadSpecialRangeDelayedReturn
...
...
@@ -4668,7 +4665,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
assign WILL_FIRE_RL_msixTable_serverAdapterA_outData_enqAndDeq =
msixTable_serverAdapterA_outDataCore$EMPTY_N &&
msixTable_serverAdapterA_outDataCore$FULL_N &&
msixTable_serverAdapterA_outData_deqCalled$whas
&&
MUX_send_pending$write_1__SEL_2
&&
msixTable_serverAdapterA_outData_enqData$whas ;
// rule RL_s_config_1_axiWriteSpecialRange
...
...
@@ -4676,7 +4673,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
s_config_writeSlave_in$EMPTY_N &&
s_config_writeSlave_out$FULL_N &&
msixTable_serverAdapterB_cnt_3_SLT_3___d168 &&
i__h5499
5
< 16'd2112 &&
i__h5499
4
< 16'd2112 &&
!WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed ;
// rule RL_s_config_axiReadSpecialRangeDelayed
...
...
@@ -4700,7 +4697,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
// rule RL_waitForCompletion
assign WILL_FIRE_RL_waitForCompletion =
writeMaster_out$EMPTY_N && active && send_pending
$port1__read
&&
writeMaster_out$EMPTY_N && active && send_pending &&
!WILL_FIRE_RL_catchInterrupt_131 &&
!WILL_FIRE_RL_catchInterrupt_130 &&
!WILL_FIRE_RL_catchInterrupt_129 &&
...
...
@@ -4835,7 +4832,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
!WILL_FIRE_RL_catchInterrupt ;
// inputs to muxes for submodule ports
assign MUX_msixTable_memory$b_put_
1
__SEL_1 =
assign MUX_msixTable_memory$b_put_
2
__SEL_1 =
WILL_FIRE_RL_s_config_1_axiWriteSpecialRange &&
(s_config_writeSlave_in$D_OUT[42:41] == 2'd0 ||
s_config_writeSlave_in$D_OUT[42:41] == 2'd1 ||
...
...
@@ -5239,6 +5236,9 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
assign MUX_s_config_readBusy$write_1__SEL_1 =
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn_1 ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn ;
assign MUX_send_pending$write_1__SEL_2 =
msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 &&
enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ;
always@(s_config_writeSlave_in$D_OUT)
begin
case (s_config_writeSlave_in$D_OUT[42:41])
...
...
@@ -5249,7 +5249,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
end
assign MUX_msixTable_memory$b_put_3__VAL_1 =
{3{s_config_writeSlave_in$D_OUT[38:7]}} ;
assign MUX_s_config_readSlave_out$enq_1__VAL_1 = { v__h2837
4
, 2'd0 } ;
assign MUX_s_config_readSlave_out$enq_1__VAL_1 = { v__h2837
3
, 2'd0 } ;
assign MUX_s_config_readSlave_out$enq_1__VAL_2 = { pbaRet$D_OUT, 2'd0 } ;
assign MUX_s_config_readSlave_out$enq_1__VAL_3 = { id, 2'd0 } ;
assign MUX_s_config_readSlave_out$enq_1__VAL_4 = { enableAndMask, 2'd0 } ;
...
...
@@ -5280,14 +5280,14 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
WILL_FIRE_RL_msixTable_serverAdapterB_outData_setFirstEnq ||
msixTable_serverAdapterB_outDataCore$EMPTY_N ;
assign msixTable_serverAdapterB_cnt_1$whas =
(MUX_msixTable_memory$b_put_
1
__SEL_1 ||
(MUX_msixTable_memory$b_put_
2
__SEL_1 ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed) &&
(!ab__h1881
4[1] || ab__h18814
[0]) ;
(!ab__h1881
3[1] || ab__h18813
[0]) ;
assign msixTable_serverAdapterB_writeWithResp$whas =
MUX_msixTable_memory$b_put_
1
__SEL_1 ||
MUX_msixTable_memory$b_put_
2
__SEL_1 ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed ;
assign msixTable_serverAdapterB_s1_1$wget =
{ 1'd1, !ab__h1881
4[1] || ab__h18814
[0] } ;
{ 1'd1, !ab__h1881
3[1] || ab__h18813
[0] } ;
assign s_config_readIsHandled$whas =
WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 ||
WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 ||
...
...
@@ -5295,9 +5295,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
WILL_FIRE_RL_s_config_axiReadSpecialIsHandled ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled ;
assign msixTable_serverAdapterA_outData_deqCalled$whas =
msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 &&
enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ;
assign s_config_writeSlave_addrIn_rv$EN_port0__write =
!s_config_writeSlave_addrIn_rv[19] && S_AXI_awvalid ;
assign s_config_writeSlave_addrIn_rv$port0__write_1 =
...
...
@@ -5330,13 +5327,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
s_config_writeSlave_dataIn_rv$EN_port1__write ?
37'h0AAAAAAAAA :
s_config_writeSlave_dataIn_rv$port1__read ;
assign send_pending$EN_port0__write =
msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 &&
enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ;
assign send_pending$port1__read =
send_pending$EN_port0__write || send_pending ;
assign send_pending$port2__read =
!WILL_FIRE_RL_waitForCompletion && send_pending$port1__read ;
assign nextInterrupt_rv$port1__read =
WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways ?
9'd170 :
...
...
@@ -7137,7 +7127,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32 ;
assign msixTable_serverAdapterA_cnt$EN =
WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways ||
msixTable_serverAdapterA_outData_deqCalled$whas
;
MUX_send_pending$write_1__SEL_2
;
// register msixTable_serverAdapterA_s1
assign msixTable_serverAdapterA_s1$D_IN =
...
...
@@ -8125,12 +8115,15 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
assign s_config_writeSlave_dataIn_rv$EN = 1'b1 ;
// register send_pending
assign send_pending$D_IN = send_pending$port2__read ;
assign send_pending$EN = 1'b1 ;
assign send_pending$D_IN = !WILL_FIRE_RL_waitForCompletion ;
assign send_pending$EN =
WILL_FIRE_RL_waitForCompletion ||
msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 &&
enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ;
// register sentReg
assign sentReg$D_IN = sentReg + 32'd1 ;
assign sentReg$EN =
msixTable_serverAdapterA_outData_deqCalled$whas
;
assign sentReg$EN =
MUX_send_pending$write_1__SEL_2
;
// register vector_control_0
assign vector_control_0$D_IN = s_config_writeSlave_in$D_OUT[7] ;
...
...
@@ -9067,17 +9060,17 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
// submodule msixTable_memory
assign msixTable_memory$ADDRA = nextInterrupt_rv[7:0] ;
assign msixTable_memory$ADDRB =
MUX_msixTable_memory$b_put_
1
__SEL_1 ?
MUX_msixTable_memory$b_put_
2
__SEL_1 ?
s_config_writeSlave_in$D_OUT[50:43] :
s_config_readSlave_in$D_OUT[14:7] ;
assign msixTable_memory$DIA = 96'd0 ;
assign msixTable_memory$DIB =
MUX_msixTable_memory$b_put_
1
__SEL_1 ?
MUX_msixTable_memory$b_put_
2
__SEL_1 ?
MUX_msixTable_memory$b_put_3__VAL_1 :
96'd0 ;
assign msixTable_memory$WEA = 12'd0 ;
assign msixTable_memory$WEB =
MUX_msixTable_memory$b_put_
1
__SEL_1 ?
MUX_msixTable_memory$b_put_
2
__SEL_1 ?
MUX_msixTable_memory$b_put_1__VAL_1 :
12'd0 ;
assign msixTable_memory$ENA =
...
...
@@ -9094,12 +9087,12 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
assign msixTable_serverAdapterA_outDataCore$ENQ =
WILL_FIRE_RL_msixTable_serverAdapterA_outData_enqAndDeq ||
msixTable_serverAdapterA_outDataCore$FULL_N &&
!
msixTable_serverAdapterA_outData_deqCalled$whas
&&
!
MUX_send_pending$write_1__SEL_2
&&
msixTable_serverAdapterA_outData_enqData$whas ;
assign msixTable_serverAdapterA_outDataCore$DEQ =
WILL_FIRE_RL_msixTable_serverAdapterA_outData_enqAndDeq ||
msixTable_serverAdapterA_outDataCore$EMPTY_N &&
msixTable_serverAdapterA_outData_deqCalled$whas
&&
MUX_send_pending$write_1__SEL_2
&&
!msixTable_serverAdapterA_outData_enqData$whas ;
assign msixTable_serverAdapterA_outDataCore$CLR = 1'b0 ;
...
...
@@ -9118,7 +9111,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
assign msixTable_serverAdapterB_outDataCore$CLR = 1'b0 ;
// submodule pbaRet
always@(addr__h2872
2
or
always@(addr__h2872
1
or
pba_vector_31 or
pba_vector_30 or
pba_vector_29 or
...
...
@@ -9250,7 +9243,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
pba_vector_131 or
pba_vector_130 or pba_vector_129 or pba_vector_128)
begin
case (addr__h2872
2
[6:2])
case (addr__h2872
1
[6:2])
5'd0:
pbaRet$D_IN =
{ pba_vector_31,
...
...
@@ -9533,11 +9526,10 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
// submodule writeMaster_in
assign writeMaster_in$D_IN =
{ x_addr__h93
62
8,
{ x_addr__h93
46
8,
msixTable_serverAdapterA_outData_outData$wget[31:0],
7'd120 } ;
assign writeMaster_in$ENQ =
msixTable_serverAdapterA_outData_deqCalled$whas ;
assign writeMaster_in$ENQ = MUX_send_pending$write_1__SEL_2 ;
assign writeMaster_in$DEQ =
writeMaster_in$EMPTY_N && !writeMaster_addrOut_rv[67] &&
!writeMaster_dataOut_rv[36] ;
...
...
@@ -10038,20 +10030,20 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
NOT_vector_control_116_97_265_AND_pba_vector_1_ETC___d1275 ||
NOT_vector_control_120_01_277_AND_pba_vector_1_ETC___d1287 ||
NOT_vector_control_124_05_288_AND_pba_vector_1_ETC___d1298 ;
assign ab__h1881
4 = MUX_msixTable_memory$b_put_1
__SEL_1 ? 2'd2 : 2'd1 ;
assign addr__h2872
2
= s_config_readSlave_in$D_OUT[18:3] - 16'd32768 ;
assign ab__h1881
3 = MUX_msixTable_memory$b_put_2
__SEL_1 ? 2'd2 : 2'd1 ;
assign addr__h2872
1
= s_config_readSlave_in$D_OUT[18:3] - 16'd32768 ;
assign enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 =
cfg_interrupt_msix_enable[0] && !cfg_interrupt_msix_mask[0] &&
active &&
!send_pending ;
assign i__h2861
9
= { s_config_readSlave_in$D_OUT[18:5], 2'd0 } ;
assign i__h5499
5
= { s_config_writeSlave_in$D_OUT[54:41], 2'd0 } ;
assign i__h2861
8
= { s_config_readSlave_in$D_OUT[18:5], 2'd0 } ;
assign i__h5499
4
= { s_config_writeSlave_in$D_OUT[54:41], 2'd0 } ;
assign msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32 =
msixTable_serverAdapterA_cnt +
(WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways ?
3'd1 :
3'd0) +
(
msixTable_serverAdapterA_outData_deqCalled$whas
? 3'd7 : 3'd0) ;
(
MUX_send_pending$write_1__SEL_2
? 3'd7 : 3'd0) ;
assign msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 =
(msixTable_serverAdapterA_outDataCore$EMPTY_N ||
msixTable_serverAdapterA_outData_enqData$whas) &&
...
...
@@ -10065,9 +10057,9 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
3'd0) ;
assign msixTable_serverAdapterB_cnt_3_SLT_3___d168 =
(msixTable_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign r__h2853
9
= { 31'd0, typeRequest$D_OUT[0] } ;
assign r__h2853
8
= { 31'd0, typeRequest$D_OUT[0] } ;
assign s_config_readSlave_in_first__71_BITS_18_TO_5_7_ETC___d174 =
i__h2861
9
< 16'd2112 ;
i__h2861
8
< 16'd2112 ;
assign typeRequest_i_notEmpty__27_AND_msixTable_serve_ETC___d333 =
typeRequest$EMPTY_N &&
(msixTable_serverAdapterB_outDataCore$EMPTY_N ||
...
...
@@ -10270,7 +10262,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
vector_control_116_97_OR_NOT_pba_vector_116_26_ETC___d1670 &&
vector_control_120_01_OR_NOT_pba_vector_120_20_ETC___d1682 &&
vector_control_124_05_OR_NOT_pba_vector_124_14_ETC___d1693 ;
assign x_addr__h93
62
8 =
assign x_addr__h93
46
8 =
{ msixTable_serverAdapterA_outData_outData$wget[63:32],
msixTable_serverAdapterA_outData_outData$wget[95:64] } ;
always@(s_config_readSlave_in$D_OUT or
...
...
@@ -10807,13 +10799,13 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
endcase
end
always@(typeRequest$D_OUT or
msixTable_serverAdapterB_outData_outData$wget or r__h2853
9
)
msixTable_serverAdapterB_outData_outData$wget or r__h2853
8
)
begin
case (typeRequest$D_OUT[2:1])
2'd0: v__h2837
4
= msixTable_serverAdapterB_outData_outData$wget[95:64];
2'd1: v__h2837
4
= msixTable_serverAdapterB_outData_outData$wget[63:32];
2'd2: v__h2837
4
= msixTable_serverAdapterB_outData_outData$wget[31:0];
2'd3: v__h2837
4 = r__h28539
;
2'd0: v__h2837
3
= msixTable_serverAdapterB_outData_outData$wget[95:64];
2'd1: v__h2837
3
= msixTable_serverAdapterB_outData_outData$wget[63:32];
2'd2: v__h2837
3
= msixTable_serverAdapterB_outData_outData$wget[31:0];
2'd3: v__h2837
3 = r__h28538
;
endcase
end
...
...
@@ -13703,7 +13695,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (S_AXI_ARESETN != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed_1)
$display("addr %x, addrShifted %x", addr__h2872
2, addr__h28722
[6:2]);
$display("addr %x, addrShifted %x", addr__h2872
1, addr__h28721
[6:2]);
if (S_AXI_ARESETN != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways)
$display("Preparing to send interrupt %d", nextInterrupt_rv[7:0]);
...
...
Jens Korinth
@jk
mentioned in commit
a831b501
·
Jul 14, 2017
mentioned in commit
a831b501
mentioned in commit a831b5015df6bd8f8d23ddd334a3b1159392de92
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