Commit 278fae90 authored by Jens Korinth's avatar Jens Korinth
Browse files

Merge branch 'BlueIPUpdates' into '2017.1'

Update BlueDMA and MSIxIntrCtrl to the newest versions

See merge request !5
parents 5029ff2f 0608e988
......@@ -528,6 +528,20 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>m64_axi</spirit:name>
......@@ -890,6 +904,20 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>s_axi_aresetn</spirit:name>
......@@ -1096,7 +1124,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>ded3be7f</spirit:value>
<spirit:value>6dca3063</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -1112,7 +1140,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>ded3be7f</spirit:value>
<spirit:value>6dca3063</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -2983,7 +3011,7 @@
<spirit:file>
<spirit:name>src/mkBlueDMAVivado.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_578878b6</spirit:userFileType>
<spirit:userFileType>CHECKSUM_031e6e27</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
......@@ -3055,17 +3083,17 @@
<xilinx:displayName>BlueDMA</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-06T11:01:37Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2017-07-07T08:39:29Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="4abcc88b"/>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9aa6aa20"/>
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d8fab998"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f4bc37ca"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="8523f8a5"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1bb46e31"/>
</xilinx:packagingInfo>
......
//
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
//
// On Thu Jul 6 13:00:48 CEST 2017
// On Fri Jul 7 10:38:49 CEST 2017
//
//
// Ports:
......@@ -26,7 +26,7 @@
// pcie_rd_arqos O 4
// pcie_rd_arregion O 4
// pcie_rd_aruser O 1
// pcie_rd_rready O 1
// pcie_rd_rready O 1 reg
// pcie_wr_awvalid O 1 reg
// pcie_wr_awid O 1
// pcie_wr_awaddr O 64
......@@ -39,7 +39,7 @@
// pcie_wr_awqos O 4
// pcie_wr_awregion O 4
// pcie_wr_awuser O 1
// pcie_wr_wvalid O 1
// pcie_wr_wvalid O 1 reg
// pcie_wr_wdata O 256
// pcie_wr_wstrb O 32
// pcie_wr_wlast O 1
......@@ -57,7 +57,7 @@
// fpga_rd_arqos O 4
// fpga_rd_arregion O 4
// fpga_rd_aruser O 1
// fpga_rd_rready O 1
// fpga_rd_rready O 1 reg
// fpga_wr_awvalid O 1 reg
// fpga_wr_awid O 1
// fpga_wr_awaddr O 64
......@@ -70,7 +70,7 @@
// fpga_wr_awqos O 4
// fpga_wr_awregion O 4
// fpga_wr_awuser O 1
// fpga_wr_wvalid O 1
// fpga_wr_wvalid O 1 reg
// fpga_wr_wdata O 512
// fpga_wr_wstrb O 64
// fpga_wr_wlast O 1
......@@ -96,11 +96,11 @@
// S_AXI_bready I 1
// pcie_rd_arready I 1
// pcie_rd_rvalid I 1
// pcie_rd_rid I 1
// pcie_rd_rdata I 256
// pcie_rd_rresp I 2
// pcie_rd_rlast I 1
// pcie_rd_ruser I 1
// pcie_rd_rid I 1 reg
// pcie_rd_rdata I 256 reg
// pcie_rd_rresp I 2 reg
// pcie_rd_rlast I 1 reg
// pcie_rd_ruser I 1 reg
// pcie_wr_awready I 1
// pcie_wr_wready I 1
// pcie_wr_bvalid I 1
......@@ -109,11 +109,11 @@
// pcie_wr_buser I 1 reg
// fpga_rd_arready I 1
// fpga_rd_rvalid I 1
// fpga_rd_rid I 1
// fpga_rd_rdata I 512
// fpga_rd_rresp I 2
// fpga_rd_rlast I 1
// fpga_rd_ruser I 1
// fpga_rd_rid I 1 reg
// fpga_rd_rdata I 512 reg
// fpga_rd_rresp I 2 reg
// fpga_rd_rlast I 1 reg
// fpga_rd_ruser I 1 reg
// fpga_wr_awready I 1
// fpga_wr_wready I 1
// fpga_wr_bvalid I 1
......@@ -730,22 +730,7 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_fpga_wr_master_wr_wawcache$wget,
m_pcie_rd_master_rd_warcache$wget,
m_pcie_wr_master_wr_wawcache$wget;
wire [578 : 0] m_fpga_wr_master_wr_in_data_1_rv$port1__read,
m_fpga_wr_master_wr_in_data_1_rv$port1__write_1,
m_fpga_wr_master_wr_in_data_1_rv$port2__read;
wire [517 : 0] m_fpga_rd_master_rd_out_1_rv$port1__read,
m_fpga_rd_master_rd_out_1_rv$port1__write_1,
m_fpga_rd_master_rd_out_1_rv$port2__read;
wire [516 : 0] m_fpga_rd_master_rd_rinpkg$wget;
wire [512 : 0] m_fpga_rd_outgoingBuffer_rv$port1__read,
m_fpga_rd_outgoingBuffer_rv$port1__write_1,
m_fpga_rd_outgoingBuffer_rv$port2__read,
m_fpga_wr_incomingBuffer_rv$port1__read,
m_fpga_wr_incomingBuffer_rv$port1__write_1,
m_fpga_wr_incomingBuffer_rv$port2__read,
writeConverter_dataSync_rv$port1__read,
writeConverter_dataSync_rv$port1__write_1,
writeConverter_dataSync_rv$port2__read;
wire [511 : 0] byteAlignerReader_buffer$port0__write_1,
byteAlignerReader_buffer$port1__read,
byteAlignerReader_buffer$port1__write_1,
......@@ -754,25 +739,7 @@ module mkBlueDMA(CLK_m32_axi_aclk,
byteAlignerWriter_buffer$port1__read,
byteAlignerWriter_buffer$port1__write_1,
byteAlignerWriter_buffer$port2__read;
wire [290 : 0] m_pcie_wr_master_wr_in_data_1_rv$port1__read,
m_pcie_wr_master_wr_in_data_1_rv$port1__write_1,
m_pcie_wr_master_wr_in_data_1_rv$port2__read;
wire [261 : 0] m_pcie_rd_master_rd_out_1_rv$port1__read,
m_pcie_rd_master_rd_out_1_rv$port1__write_1,
m_pcie_rd_master_rd_out_1_rv$port2__read;
wire [260 : 0] m_pcie_rd_master_rd_rinpkg$wget;
wire [256 : 0] byteAlignerReader_incoming_rv$port1__read,
byteAlignerReader_outgoing_rv$port1__write_1,
byteAlignerReader_outgoing_rv$port2__read,
byteAlignerWriter_incoming_rv$port1__read,
byteAlignerWriter_outgoing_rv$port1__write_1,
byteAlignerWriter_outgoing_rv$port2__read,
m_pcie_rd_outgoingBuffer_rv$port1__read,
m_pcie_rd_outgoingBuffer_rv$port1__write_1,
m_pcie_rd_outgoingBuffer_rv$port2__read,
m_pcie_wr_incomingBuffer_rv$port1__read,
m_pcie_wr_incomingBuffer_rv$port1__write_1,
m_pcie_wr_incomingBuffer_rv$port2__read;
wire [192 : 0] readIn_rv$port1__read,
readIn_rv$port1__write_1,
readIn_rv$port2__read,
......@@ -795,23 +762,13 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire byteAlignerReader_buffer$EN_port0__write,
byteAlignerReader_bytes_left_in_buffer$EN_port0__write,
byteAlignerReader_fetchedDatum$EN_port0__write,
byteAlignerReader_fetchedDatum$EN_port1__write,
byteAlignerReader_fetchedDatum$port1__read,
byteAlignerReader_fetchedDatum$port2__read,
byteAlignerReader_outgoing_rv$EN_port1__write,
byteAlignerWriter_buffer$EN_port0__write,
byteAlignerWriter_bytes_left_in_buffer$EN_port0__write,
byteAlignerWriter_fetchedDatum$EN_port0__write,
byteAlignerWriter_fetchedDatum$EN_port1__write,
byteAlignerWriter_fetchedDatum$port1__read,
byteAlignerWriter_fetchedDatum$port2__read,
byteAlignerWriter_outgoing_rv$EN_port1__write,
m_fpga_rd_master_rd_out_1_rv$EN_port1__write,
m_fpga_rd_outgoingBuffer_rv$EN_port0__write,
m_fpga_wr_incomingBuffer_rv$EN_port1__write,
m_fpga_wr_master_wr_in_data_1_rv$EN_port0__write,
m_pcie_rd_master_rd_out_1_rv$EN_port1__write,
m_pcie_wr_master_wr_in_data_1_rv$EN_port0__write,
readConverter_bufferEmpty$EN_port0__write,
readConverter_bufferEmpty$EN_port1__write,
readConverter_bufferEmpty$port1__read,
......@@ -823,8 +780,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
s_config_writeSlave_addrIn_rv$EN_port1__write,
s_config_writeSlave_dataIn_rv$EN_port0__write,
s_config_writeSlave_dataIn_rv$EN_port1__write,
writeConverter_dataSync_rv$EN_port0__write,
writeConverter_dataSync_rv$EN_port1__write,
writeIn_rv$EN_port1__write;
// register byteAlignerReader_buffer
......@@ -861,16 +816,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
reg byteAlignerReader_fetchedDatum;
wire byteAlignerReader_fetchedDatum$D_IN, byteAlignerReader_fetchedDatum$EN;
// register byteAlignerReader_incoming_rv
reg [256 : 0] byteAlignerReader_incoming_rv;
wire [256 : 0] byteAlignerReader_incoming_rv$D_IN;
wire byteAlignerReader_incoming_rv$EN;
// register byteAlignerReader_outgoing_rv
reg [256 : 0] byteAlignerReader_outgoing_rv;
wire [256 : 0] byteAlignerReader_outgoing_rv$D_IN;
wire byteAlignerReader_outgoing_rv$EN;
// register byteAlignerWriter_buffer
reg [511 : 0] byteAlignerWriter_buffer;
wire [511 : 0] byteAlignerWriter_buffer$D_IN;
......@@ -905,16 +850,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
reg byteAlignerWriter_fetchedDatum;
wire byteAlignerWriter_fetchedDatum$D_IN, byteAlignerWriter_fetchedDatum$EN;
// register byteAlignerWriter_incoming_rv
reg [256 : 0] byteAlignerWriter_incoming_rv;
wire [256 : 0] byteAlignerWriter_incoming_rv$D_IN;
wire byteAlignerWriter_incoming_rv$EN;
// register byteAlignerWriter_outgoing_rv
reg [256 : 0] byteAlignerWriter_outgoing_rv;
wire [256 : 0] byteAlignerWriter_outgoing_rv$D_IN;
wire byteAlignerWriter_outgoing_rv$EN;
// register doneInterruptReg
reg doneInterruptReg;
wire doneInterruptReg$D_IN, doneInterruptReg$EN;
......@@ -958,16 +893,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [31 : 0] m_fpga_rd_lastPut$D_IN;
wire m_fpga_rd_lastPut$EN;
// register m_fpga_rd_master_rd_out_1_rv
reg [517 : 0] m_fpga_rd_master_rd_out_1_rv;
wire [517 : 0] m_fpga_rd_master_rd_out_1_rv$D_IN;
wire m_fpga_rd_master_rd_out_1_rv$EN;
// register m_fpga_rd_outgoingBuffer_rv
reg [512 : 0] m_fpga_rd_outgoingBuffer_rv;
wire [512 : 0] m_fpga_rd_outgoingBuffer_rv$D_IN;
wire m_fpga_rd_outgoingBuffer_rv$EN;
// register m_fpga_rd_putDelay
reg [31 : 0] m_fpga_rd_putDelay;
wire [31 : 0] m_fpga_rd_putDelay$D_IN;
......@@ -998,21 +923,11 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [31 : 0] m_fpga_wr_clkCntr$D_IN;
wire m_fpga_wr_clkCntr$EN;
// register m_fpga_wr_incomingBuffer_rv
reg [512 : 0] m_fpga_wr_incomingBuffer_rv;
wire [512 : 0] m_fpga_wr_incomingBuffer_rv$D_IN;
wire m_fpga_wr_incomingBuffer_rv$EN;
// register m_fpga_wr_lastPut
reg [31 : 0] m_fpga_wr_lastPut;
wire [31 : 0] m_fpga_wr_lastPut$D_IN;
wire m_fpga_wr_lastPut$EN;
// register m_fpga_wr_master_wr_in_data_1_rv
reg [578 : 0] m_fpga_wr_master_wr_in_data_1_rv;
wire [578 : 0] m_fpga_wr_master_wr_in_data_1_rv$D_IN;
wire m_fpga_wr_master_wr_in_data_1_rv$EN;
// register m_fpga_wr_putDelay
reg [31 : 0] m_fpga_wr_putDelay;
wire [31 : 0] m_fpga_wr_putDelay$D_IN;
......@@ -1043,16 +958,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [31 : 0] m_pcie_rd_lastPut$D_IN;
wire m_pcie_rd_lastPut$EN;
// register m_pcie_rd_master_rd_out_1_rv
reg [261 : 0] m_pcie_rd_master_rd_out_1_rv;
wire [261 : 0] m_pcie_rd_master_rd_out_1_rv$D_IN;
wire m_pcie_rd_master_rd_out_1_rv$EN;
// register m_pcie_rd_outgoingBuffer_rv
reg [256 : 0] m_pcie_rd_outgoingBuffer_rv;
wire [256 : 0] m_pcie_rd_outgoingBuffer_rv$D_IN;
wire m_pcie_rd_outgoingBuffer_rv$EN;
// register m_pcie_rd_putDelay
reg [31 : 0] m_pcie_rd_putDelay;
wire [31 : 0] m_pcie_rd_putDelay$D_IN;
......@@ -1083,21 +988,11 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [31 : 0] m_pcie_wr_clkCntr$D_IN;
wire m_pcie_wr_clkCntr$EN;
// register m_pcie_wr_incomingBuffer_rv
reg [256 : 0] m_pcie_wr_incomingBuffer_rv;
wire [256 : 0] m_pcie_wr_incomingBuffer_rv$D_IN;
wire m_pcie_wr_incomingBuffer_rv$EN;
// register m_pcie_wr_lastPut
reg [31 : 0] m_pcie_wr_lastPut;
wire [31 : 0] m_pcie_wr_lastPut$D_IN;
wire m_pcie_wr_lastPut$EN;
// register m_pcie_wr_master_wr_in_data_1_rv
reg [290 : 0] m_pcie_wr_master_wr_in_data_1_rv;
wire [290 : 0] m_pcie_wr_master_wr_in_data_1_rv$D_IN;
wire m_pcie_wr_master_wr_in_data_1_rv$EN;
// register m_pcie_wr_putDelay
reg [31 : 0] m_pcie_wr_putDelay;
wire [31 : 0] m_pcie_wr_putDelay$D_IN;
......@@ -1188,11 +1083,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire [63 : 0] writeConverter_byteCntr$D_IN;
wire writeConverter_byteCntr$EN;
// register writeConverter_dataSync_rv
reg [512 : 0] writeConverter_dataSync_rv;
wire [512 : 0] writeConverter_dataSync_rv$D_IN;
wire writeConverter_dataSync_rv$EN;
// register writeConverter_wordInCntr
reg [1 : 0] writeConverter_wordInCntr;
wire [1 : 0] writeConverter_wordInCntr$D_IN;
......@@ -1220,6 +1110,21 @@ module mkBlueDMA(CLK_m32_axi_aclk,
byteAlignerReader_addr_ff$dEMPTY_N,
byteAlignerReader_addr_ff$sENQ;
// ports of submodule byteAlignerReader_incoming
wire [255 : 0] byteAlignerReader_incoming$D_IN,
byteAlignerReader_incoming$D_OUT;
wire byteAlignerReader_incoming$CLR,
byteAlignerReader_incoming$DEQ,
byteAlignerReader_incoming$EMPTY_N,
byteAlignerReader_incoming$ENQ;
// ports of submodule byteAlignerReader_outgoing
wire [255 : 0] byteAlignerReader_outgoing$D_IN;
wire byteAlignerReader_outgoing$CLR,
byteAlignerReader_outgoing$DEQ,
byteAlignerReader_outgoing$ENQ,
byteAlignerReader_outgoing$FULL_N;
// ports of submodule byteAlignerWriter_addr_ff
wire [191 : 0] byteAlignerWriter_addr_ff$dD_OUT,
byteAlignerWriter_addr_ff$sD_IN;
......@@ -1227,6 +1132,21 @@ module mkBlueDMA(CLK_m32_axi_aclk,
byteAlignerWriter_addr_ff$dEMPTY_N,
byteAlignerWriter_addr_ff$sENQ;
// ports of submodule byteAlignerWriter_incoming
wire [255 : 0] byteAlignerWriter_incoming$D_IN,
byteAlignerWriter_incoming$D_OUT;
wire byteAlignerWriter_incoming$CLR,
byteAlignerWriter_incoming$DEQ,
byteAlignerWriter_incoming$EMPTY_N,
byteAlignerWriter_incoming$ENQ;
// ports of submodule byteAlignerWriter_outgoing
wire [255 : 0] byteAlignerWriter_outgoing$D_IN;
wire byteAlignerWriter_outgoing$CLR,
byteAlignerWriter_outgoing$DEQ,
byteAlignerWriter_outgoing$ENQ,
byteAlignerWriter_outgoing$FULL_N;
// ports of submodule cmdsIn
wire cmdsIn$CLR,
cmdsIn$DEQ,
......@@ -1287,10 +1207,21 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_fpga_rd_master_rd_in$FULL_N;
// ports of submodule m_fpga_rd_master_rd_out
wire [516 : 0] m_fpga_rd_master_rd_out$D_IN;
wire [516 : 0] m_fpga_rd_master_rd_out$D_IN, m_fpga_rd_master_rd_out$D_OUT;
wire m_fpga_rd_master_rd_out$CLR,
m_fpga_rd_master_rd_out$DEQ,
m_fpga_rd_master_rd_out$ENQ;
m_fpga_rd_master_rd_out$EMPTY_N,
m_fpga_rd_master_rd_out$ENQ,
m_fpga_rd_master_rd_out$FULL_N;
// ports of submodule m_fpga_rd_outgoingBuffer
wire [511 : 0] m_fpga_rd_outgoingBuffer$D_IN,
m_fpga_rd_outgoingBuffer$D_OUT;
wire m_fpga_rd_outgoingBuffer$CLR,
m_fpga_rd_outgoingBuffer$DEQ,
m_fpga_rd_outgoingBuffer$EMPTY_N,
m_fpga_rd_outgoingBuffer$ENQ,
m_fpga_rd_outgoingBuffer$FULL_N;
// ports of submodule m_fpga_rd_reqGen_incomingBuffer
wire [131 : 0] m_fpga_rd_reqGen_incomingBuffer$D_IN,
......@@ -1337,6 +1268,15 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_fpga_wr_beatsPerRequestFIFO$ENQ,
m_fpga_wr_beatsPerRequestFIFO$FULL_N;
// ports of submodule m_fpga_wr_incomingBuffer
wire [511 : 0] m_fpga_wr_incomingBuffer$D_IN,
m_fpga_wr_incomingBuffer$D_OUT;
wire m_fpga_wr_incomingBuffer$CLR,
m_fpga_wr_incomingBuffer$DEQ,
m_fpga_wr_incomingBuffer$EMPTY_N,
m_fpga_wr_incomingBuffer$ENQ,
m_fpga_wr_incomingBuffer$FULL_N;
// ports of submodule m_fpga_wr_master_wr_in_addr
wire [94 : 0] m_fpga_wr_master_wr_in_addr$D_IN,
m_fpga_wr_master_wr_in_addr$D_OUT;
......@@ -1347,10 +1287,13 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_fpga_wr_master_wr_in_addr$FULL_N;
// ports of submodule m_fpga_wr_master_wr_in_data
wire [577 : 0] m_fpga_wr_master_wr_in_data$D_IN;
wire [577 : 0] m_fpga_wr_master_wr_in_data$D_IN,
m_fpga_wr_master_wr_in_data$D_OUT;
wire m_fpga_wr_master_wr_in_data$CLR,
m_fpga_wr_master_wr_in_data$DEQ,
m_fpga_wr_master_wr_in_data$ENQ;
m_fpga_wr_master_wr_in_data$EMPTY_N,
m_fpga_wr_master_wr_in_data$ENQ,
m_fpga_wr_master_wr_in_data$FULL_N;
// ports of submodule m_fpga_wr_master_wr_out
wire [3 : 0] m_fpga_wr_master_wr_out$D_IN;
......@@ -1405,10 +1348,21 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_pcie_rd_master_rd_in$FULL_N;
// ports of submodule m_pcie_rd_master_rd_out
wire [260 : 0] m_pcie_rd_master_rd_out$D_IN;
wire [260 : 0] m_pcie_rd_master_rd_out$D_IN, m_pcie_rd_master_rd_out$D_OUT;
wire m_pcie_rd_master_rd_out$CLR,
m_pcie_rd_master_rd_out$DEQ,
m_pcie_rd_master_rd_out$ENQ;
m_pcie_rd_master_rd_out$EMPTY_N,
m_pcie_rd_master_rd_out$ENQ,
m_pcie_rd_master_rd_out$FULL_N;
// ports of submodule m_pcie_rd_outgoingBuffer
wire [255 : 0] m_pcie_rd_outgoingBuffer$D_IN,
m_pcie_rd_outgoingBuffer$D_OUT;
wire m_pcie_rd_outgoingBuffer$CLR,
m_pcie_rd_outgoingBuffer$DEQ,
m_pcie_rd_outgoingBuffer$EMPTY_N,
m_pcie_rd_outgoingBuffer$ENQ,
m_pcie_rd_outgoingBuffer$FULL_N;
// ports of submodule m_pcie_rd_reqGen_incomingBuffer
wire [131 : 0] m_pcie_rd_reqGen_incomingBuffer$D_IN,
......@@ -1455,6 +1409,15 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_pcie_wr_beatsPerRequestFIFO$ENQ,
m_pcie_wr_beatsPerRequestFIFO$FULL_N;
// ports of submodule m_pcie_wr_incomingBuffer
reg [255 : 0] m_pcie_wr_incomingBuffer$D_IN;
wire [255 : 0] m_pcie_wr_incomingBuffer$D_OUT;
wire m_pcie_wr_incomingBuffer$CLR,
m_pcie_wr_incomingBuffer$DEQ,
m_pcie_wr_incomingBuffer$EMPTY_N,
m_pcie_wr_incomingBuffer$ENQ,
m_pcie_wr_incomingBuffer$FULL_N;
// ports of submodule m_pcie_wr_master_wr_in_addr
wire [94 : 0] m_pcie_wr_master_wr_in_addr$D_IN,
m_pcie_wr_master_wr_in_addr$D_OUT;
......@@ -1465,10 +1428,13 @@ module mkBlueDMA(CLK_m32_axi_aclk,
m_pcie_wr_master_wr_in_addr$FULL_N;
// ports of submodule m_pcie_wr_master_wr_in_data
wire [289 : 0] m_pcie_wr_master_wr_in_data$D_IN;
wire [289 : 0] m_pcie_wr_master_wr_in_data$D_IN,
m_pcie_wr_master_wr_in_data$D_OUT;
wire m_pcie_wr_master_wr_in_data$CLR,
m_pcie_wr_master_wr_in_data$DEQ,
m_pcie_wr_master_wr_in_data$ENQ;
m_pcie_wr_master_wr_in_data$EMPTY_N,
m_pcie_wr_master_wr_in_data$ENQ,
m_pcie_wr_master_wr_in_data$FULL_N;
// ports of submodule m_pcie_wr_master_wr_out
wire [3 : 0] m_pcie_wr_master_wr_out$D_IN;
......@@ -1612,6 +1578,14 @@ module mkBlueDMA(CLK_m32_axi_aclk,
writeConvBTT_ff$sENQ,
writeConvBTT_ff$sFULL_N;
// ports of submodule writeConverter_dataSync
wire [511 : 0] writeConverter_dataSync$D_IN, writeConverter_dataSync$D_OUT;
wire writeConverter_dataSync$CLR,
writeConverter_dataSync$DEQ,
writeConverter_dataSync$EMPTY_N,
writeConverter_dataSync$ENQ,
writeConverter_dataSync$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_byteAlignerReader_forwardOutputLast,
CAN_FIRE_RL_byteAlignerWriter_forwardOutputLast,
......@@ -1691,10 +1665,6 @@ module mkBlueDMA(CLK_m32_axi_aclk,
// inputs to muxes for submodule ports
wire [511 : 0] MUX_byteAlignerReader_buffer$port0__write_1__VAL_1,
MUX_byteAlignerWriter_buffer$port0__write_1__VAL_1;
wire [256 : 0] MUX_byteAlignerReader_outgoing_rv$port1__write_1__VAL_1,
MUX_byteAlignerReader_outgoing_rv$port1__write_1__VAL_2,
MUX_byteAlignerWriter_outgoing_rv$port1__write_1__VAL_1,
MUX_byteAlignerWriter_outgoing_rv$port1__write_1__VAL_2;
wire [134 : 0] MUX_m_pcie_rd_task_data_requests_reg$write_1__VAL_1,
MUX_m_pcie_wr_task_data_requests_reg$write_1__VAL_1;
wire [133 : 0] MUX_m_fpga_rd_task_data_requests_reg$write_1__VAL_1,
......@@ -1740,132 +1710,131 @@ module mkBlueDMA(CLK_m32_axi_aclk,
wire MUX_opInProgress$write_1__SEL_2;
// remaining internal signals
reg [255 : 0] CASE_readConverter_wordInCntr_0_readConverter__ETC__q2;
reg [3 : 0] CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q6,
CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q5,
CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q4,
CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q3;
reg [3 : 0] CASE_m_fpga_rd_master_rd_warcachewget_1_m_fpg_ETC__q5,
CASE_m_fpga_wr_master_wr_wawcachewget_1_m_fpg_ETC__q4,
CASE_m_pcie_rd_master_rd_warcachewget_1_m_pci_ETC__q3,
CASE_m_pcie_wr_master_wr_wawcachewget_1_m_pci_ETC__q2;
wire [63 : 0] _theResult____h24288,
_theResult____h24472,
_theResult____h34798,
_theResult____h34982,
_theResult____h39240,
_theResult____h39424,
_theResult____h55143,
_theResult____h55327,
btt__h103430,
btt__h147854,
_theResult____h34242,
_theResult____h34426,
_theResult____h38131,
_theResult____h38315,
_theResult____h53478,
_theResult____h53662,
btt__h100105,
btt__h143147,
bytes_first___1__h24323,
bytes_first___1__h34833,
bytes_first___1__h39275,
bytes_first___1__h55178,
bytes_first___1__h34277,
bytes_first___1__h38166,
bytes_first___1__h53513,
bytes_first__h24287,
bytes_first__h34797,
bytes_first__h39239,
bytes_first__h55142,
m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7,
m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8,
m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9,
m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q10,
bytes_first__h34241,
bytes_first__h38130,
bytes_first__h53477,
m_fpga_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q6,
m_fpga_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q7,
m_pcie_rd_reqGen_incomingBufferD_OUT_BITS_67__ETC__q8,
m_pcie_wr_reqGen_incomingBufferD_OUT_BITS_67__ETC__q9,
request_data_address__h24612,
request_data_address__h35122,
request_data_address__h39564,
request_data_address__h55467,
request_data_address__h34566,
request_data_address__h38455,
request_data_address__h53802,
transfers_total___1__h24480,
transfers_total___1__h34990,
transfers_total___1__h39432,
transfers_total___1__h55335,
transfers_total___1__h34434,
transfers_total___1__h38323,
transfers_total___1__h53670,
transfers_total__h24471,
transfers_total__h24477,
transfers_total__h34981,
transfers_total__h34987,
transfers_total__h39423,
transfers_total__h39429,
transfers_total__h55326,
transfers_total__h55332,
transfers_total__h34425,
transfers_total__h34431,
transfers_total__h38314,