Commit 278fae90 authored by Jens Korinth's avatar Jens Korinth
Browse files

Merge branch 'BlueIPUpdates' into '2017.1'

Update BlueDMA and MSIxIntrCtrl to the newest versions

See merge request !5
parents 5029ff2f 0608e988
...@@ -528,6 +528,20 @@ ...@@ -528,6 +528,20 @@
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
</spirit:portMaps> </spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M32_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>m64_axi</spirit:name> <spirit:name>m64_axi</spirit:name>
...@@ -890,6 +904,20 @@ ...@@ -890,6 +904,20 @@
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
</spirit:portMaps> </spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.M64_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>s_axi_aresetn</spirit:name> <spirit:name>s_axi_aresetn</spirit:name>
...@@ -1096,7 +1124,7 @@ ...@@ -1096,7 +1124,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>ded3be7f</spirit:value> <spirit:value>6dca3063</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -1112,7 +1140,7 @@ ...@@ -1112,7 +1140,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>ded3be7f</spirit:value> <spirit:value>6dca3063</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -2983,7 +3011,7 @@ ...@@ -2983,7 +3011,7 @@
<spirit:file> <spirit:file>
<spirit:name>src/mkBlueDMAVivado.v</spirit:name> <spirit:name>src/mkBlueDMAVivado.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType> <spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_578878b6</spirit:userFileType> <spirit:userFileType>CHECKSUM_031e6e27</spirit:userFileType>
</spirit:file> </spirit:file>
</spirit:fileSet> </spirit:fileSet>
<spirit:fileSet> <spirit:fileSet>
...@@ -3055,17 +3083,17 @@ ...@@ -3055,17 +3083,17 @@
<xilinx:displayName>BlueDMA</xilinx:displayName> <xilinx:displayName>BlueDMA</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource> <xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision> <xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-06T11:01:37Z</xilinx:coreCreationDateTime> <xilinx:coreCreationDateTime>2017-07-07T08:39:29Z</xilinx:coreCreationDateTime>
<xilinx:tags> <xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/> <xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags> </xilinx:tags>
</xilinx:coreExtensions> </xilinx:coreExtensions>
<xilinx:packagingInfo> <xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion> <xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="4abcc88b"/> <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9aa6aa20"/>
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/> <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f16c3a"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/> <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5dd283ff"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d8fab998"/> <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f4bc37ca"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="8523f8a5"/> <xilinx:checksum xilinx:scope="ports" xilinx:value="8523f8a5"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1bb46e31"/> <xilinx:checksum xilinx:scope="parameters" xilinx:value="1bb46e31"/>
</xilinx:packagingInfo> </xilinx:packagingInfo>
......
This diff is collapsed.
// //
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
// //
// On Thu Jul 6 13:00:49 CEST 2017 // On Fri Jul 7 10:38:51 CEST 2017
// //
// //
// Ports: // Ports:
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
// m64_axi_arqos O 4 // m64_axi_arqos O 4
// m64_axi_arregion O 4 // m64_axi_arregion O 4
// m64_axi_aruser O 1 // m64_axi_aruser O 1
// m64_axi_rready O 1 // m64_axi_rready O 1 reg
// m64_axi_awvalid O 1 reg // m64_axi_awvalid O 1 reg
// m64_axi_awid O 1 // m64_axi_awid O 1
// m64_axi_awaddr O 64 // m64_axi_awaddr O 64
...@@ -39,7 +39,7 @@ ...@@ -39,7 +39,7 @@
// m64_axi_awqos O 4 // m64_axi_awqos O 4
// m64_axi_awregion O 4 // m64_axi_awregion O 4
// m64_axi_awuser O 1 // m64_axi_awuser O 1
// m64_axi_wvalid O 1 // m64_axi_wvalid O 1 reg
// m64_axi_wdata O 256 // m64_axi_wdata O 256
// m64_axi_wstrb O 32 // m64_axi_wstrb O 32
// m64_axi_wlast O 1 // m64_axi_wlast O 1
...@@ -57,7 +57,7 @@ ...@@ -57,7 +57,7 @@
// m32_axi_arqos O 4 // m32_axi_arqos O 4
// m32_axi_arregion O 4 // m32_axi_arregion O 4
// m32_axi_aruser O 1 // m32_axi_aruser O 1
// m32_axi_rready O 1 // m32_axi_rready O 1 reg
// m32_axi_awvalid O 1 reg // m32_axi_awvalid O 1 reg
// m32_axi_awid O 1 // m32_axi_awid O 1
// m32_axi_awaddr O 64 // m32_axi_awaddr O 64
...@@ -70,7 +70,7 @@ ...@@ -70,7 +70,7 @@
// m32_axi_awqos O 4 // m32_axi_awqos O 4
// m32_axi_awregion O 4 // m32_axi_awregion O 4
// m32_axi_awuser O 1 // m32_axi_awuser O 1
// m32_axi_wvalid O 1 // m32_axi_wvalid O 1 reg
// m32_axi_wdata O 512 // m32_axi_wdata O 512
// m32_axi_wstrb O 64 // m32_axi_wstrb O 64
// m32_axi_wlast O 1 // m32_axi_wlast O 1
...@@ -96,11 +96,11 @@ ...@@ -96,11 +96,11 @@
// S_AXI_bready I 1 // S_AXI_bready I 1
// m64_axi_arready I 1 // m64_axi_arready I 1
// m64_axi_rvalid I 1 // m64_axi_rvalid I 1
// m64_axi_rid I 1 // m64_axi_rid I 1 reg
// m64_axi_rdata I 256 // m64_axi_rdata I 256 reg
// m64_axi_rresp I 2 // m64_axi_rresp I 2 reg
// m64_axi_rlast I 1 // m64_axi_rlast I 1 reg
// m64_axi_ruser I 1 // m64_axi_ruser I 1 reg
// m64_axi_awready I 1 // m64_axi_awready I 1
// m64_axi_wready I 1 // m64_axi_wready I 1
// m64_axi_bvalid I 1 // m64_axi_bvalid I 1
...@@ -109,11 +109,11 @@ ...@@ -109,11 +109,11 @@
// m64_axi_buser I 1 reg // m64_axi_buser I 1 reg
// m32_axi_arready I 1 // m32_axi_arready I 1
// m32_axi_rvalid I 1 // m32_axi_rvalid I 1
// m32_axi_rid I 1 // m32_axi_rid I 1 reg
// m32_axi_rdata I 512 // m32_axi_rdata I 512 reg
// m32_axi_rresp I 2 // m32_axi_rresp I 2 reg
// m32_axi_rlast I 1 // m32_axi_rlast I 1 reg
// m32_axi_ruser I 1 // m32_axi_ruser I 1 reg
// m32_axi_awready I 1 // m32_axi_awready I 1
// m32_axi_wready I 1 // m32_axi_wready I 1
// m32_axi_bvalid I 1 // m32_axi_bvalid I 1
......
...@@ -427,7 +427,7 @@ ...@@ -427,7 +427,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>558b72aa</spirit:value> <spirit:value>e07e9e3a</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -443,7 +443,7 @@ ...@@ -443,7 +443,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>558b72aa</spirit:value> <spirit:value>e07e9e3a</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -1267,7 +1267,7 @@ ...@@ -1267,7 +1267,7 @@
<spirit:file> <spirit:file>
<spirit:name>src/mkMSIXIntrCtrl.v</spirit:name> <spirit:name>src/mkMSIXIntrCtrl.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType> <spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_7049b426</spirit:userFileType> <spirit:userFileType>CHECKSUM_f02cbad3</spirit:userFileType>
</spirit:file> </spirit:file>
</spirit:fileSet> </spirit:fileSet>
<spirit:fileSet> <spirit:fileSet>
...@@ -1323,7 +1323,7 @@ ...@@ -1323,7 +1323,7 @@
<xilinx:displayName>MSIXIntrCtrl</xilinx:displayName> <xilinx:displayName>MSIXIntrCtrl</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource> <xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision> <xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-07-05T16:28:24Z</xilinx:coreCreationDateTime> <xilinx:coreCreationDateTime>2017-07-07T08:36:48Z</xilinx:coreCreationDateTime>
<xilinx:tags> <xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/> <xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags> </xilinx:tags>
...@@ -1333,7 +1333,7 @@ ...@@ -1333,7 +1333,7 @@
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="a9103989"/> <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="a9103989"/>
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f94240"/> <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="39f94240"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="2b2da2c0"/> <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="2b2da2c0"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="057aaeb0"/> <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ecf6481e"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="19368f77"/> <xilinx:checksum xilinx:scope="ports" xilinx:value="19368f77"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="4b2b81b7"/> <xilinx:checksum xilinx:scope="parameters" xilinx:value="4b2b81b7"/>
</xilinx:packagingInfo> </xilinx:packagingInfo>
......
set_false_path -through [get_pins system_i/InterruptControl/msix_intr_ctrl/interrupt*]
// //
// Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07) // Generated by Bluespec Compiler, version 2015.09.beta2 (build 34689, 2015-09-07)
// //
// On Wed Jul 5 18:26:03 CEST 2017 // On Fri Jul 7 10:35:33 CEST 2017
// //
// //
// Ports: // Ports:
...@@ -344,8 +344,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -344,8 +344,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
nextInterrupt_rv$port1__write_1, nextInterrupt_rv$port1__write_1,
nextInterrupt_rv$port2__read; nextInterrupt_rv$port2__read;
wire [1 : 0] msixTable_serverAdapterB_s1_1$wget; wire [1 : 0] msixTable_serverAdapterB_s1_1$wget;
wire msixTable_serverAdapterA_outData_deqCalled$whas, wire msixTable_serverAdapterA_outData_enqData$whas,
msixTable_serverAdapterA_outData_enqData$whas,
msixTable_serverAdapterA_outData_outData$whas, msixTable_serverAdapterA_outData_outData$whas,
msixTable_serverAdapterB_cnt_1$whas, msixTable_serverAdapterB_cnt_1$whas,
msixTable_serverAdapterB_outData_enqData$whas, msixTable_serverAdapterB_outData_enqData$whas,
...@@ -357,9 +356,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -357,9 +356,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
s_config_writeSlave_addrIn_rv$EN_port1__write, s_config_writeSlave_addrIn_rv$EN_port1__write,
s_config_writeSlave_dataIn_rv$EN_port0__write, s_config_writeSlave_dataIn_rv$EN_port0__write,
s_config_writeSlave_dataIn_rv$EN_port1__write, s_config_writeSlave_dataIn_rv$EN_port1__write,
send_pending$EN_port0__write,
send_pending$port1__read,
send_pending$port2__read,
writeMaster_addrOut_rv$EN_port0__write, writeMaster_addrOut_rv$EN_port0__write,
writeMaster_addrOut_rv$EN_port1__write, writeMaster_addrOut_rv$EN_port1__write,
writeMaster_dataOut_rv$EN_port0__write, writeMaster_dataOut_rv$EN_port0__write,
...@@ -3508,7 +3504,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -3508,7 +3504,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
MUX_s_config_readSlave_out$enq_1__VAL_4, MUX_s_config_readSlave_out$enq_1__VAL_4,
MUX_s_config_readSlave_out$enq_1__VAL_5, MUX_s_config_readSlave_out$enq_1__VAL_5,
MUX_s_config_readSlave_out$enq_1__VAL_6; MUX_s_config_readSlave_out$enq_1__VAL_6;
wire MUX_msixTable_memory$b_put_1__SEL_1, wire MUX_msixTable_memory$b_put_2__SEL_1,
MUX_pba_vector_0$write_1__SEL_1, MUX_pba_vector_0$write_1__SEL_1,
MUX_pba_vector_1$write_1__SEL_1, MUX_pba_vector_1$write_1__SEL_1,
MUX_pba_vector_10$write_1__SEL_1, MUX_pba_vector_10$write_1__SEL_1,
...@@ -3641,14 +3637,15 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -3641,14 +3637,15 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
MUX_pba_vector_97$write_1__SEL_1, MUX_pba_vector_97$write_1__SEL_1,
MUX_pba_vector_98$write_1__SEL_1, MUX_pba_vector_98$write_1__SEL_1,
MUX_pba_vector_99$write_1__SEL_1, MUX_pba_vector_99$write_1__SEL_1,
MUX_s_config_readBusy$write_1__SEL_1; MUX_s_config_readBusy$write_1__SEL_1,
MUX_send_pending$write_1__SEL_2;
   
// remaining internal signals // remaining internal signals
reg [31 : 0] v__h28374; reg [31 : 0] v__h28373;
reg SEL_ARR_vector_control_0_81_vector_control_1_8_ETC___d315; reg SEL_ARR_vector_control_0_81_vector_control_1_8_ETC___d315;
wire [63 : 0] x_addr__h93628; wire [63 : 0] x_addr__h93468;
wire [31 : 0] r__h28539; wire [31 : 0] r__h28538;
wire [15 : 0] addr__h28722, i__h28619, i__h54995; wire [15 : 0] addr__h28721, i__h28618, i__h54994;
wire [7 : 0] IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1830, wire [7 : 0] IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1830,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1832, IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1832,
IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1833, IF_vector_control_0_81_OR_NOT_pba_vector_0_12__ETC___d1833,
...@@ -3698,7 +3695,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -3698,7 +3695,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1739; IF_vector_control_96_77_OR_NOT_pba_vector_96_5_ETC___d1739;
wire [2 : 0] msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32, wire [2 : 0] msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32,
msixTable_serverAdapterB_cnt_3_PLUS_IF_msixTab_ETC___d89; msixTable_serverAdapterB_cnt_3_PLUS_IF_msixTab_ETC___d89;
wire [1 : 0] ab__h18814; wire [1 : 0] ab__h18813;
wire NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1015, wire NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1015,
NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1315, NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d1315,
NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d931, NOT_vector_control_0_81_21_AND_pba_vector_0_12_ETC___d931,
...@@ -4047,8 +4044,8 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -4047,8 +4044,8 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
   
// rule RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 // rule RL_s_config_axiReadSpecialRangeDelayedIsHandled_1
assign WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 = assign WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 =
s_config_readSlave_in$EMPTY_N && i__h28619 >= 16'd32768 && s_config_readSlave_in$EMPTY_N && i__h28618 >= 16'd32768 &&
i__h28619 < 16'd32788 ; i__h28618 < 16'd32788 ;
   
// rule RL_s_config_axiReadSpecialIsHandled // rule RL_s_config_axiReadSpecialIsHandled
assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled = assign WILL_FIRE_RL_s_config_axiReadSpecialIsHandled =
...@@ -4073,8 +4070,8 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -4073,8 +4070,8 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
// rule RL_s_config_axiReadSpecialRangeDelayed_1 // rule RL_s_config_axiReadSpecialRangeDelayed_1
assign WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed_1 = assign WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed_1 =
s_config_readSlave_in$EMPTY_N && pbaRet$FULL_N && s_config_readSlave_in$EMPTY_N && pbaRet$FULL_N &&
i__h28619 >= 16'd32768 && i__h28618 >= 16'd32768 &&
i__h28619 < 16'd32788 && i__h28618 < 16'd32788 &&
!s_config_readBusy ; !s_config_readBusy ;
   
// rule RL_s_config_axiReadSpecialRangeDelayedReturn // rule RL_s_config_axiReadSpecialRangeDelayedReturn
...@@ -4668,7 +4665,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -4668,7 +4665,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
assign WILL_FIRE_RL_msixTable_serverAdapterA_outData_enqAndDeq = assign WILL_FIRE_RL_msixTable_serverAdapterA_outData_enqAndDeq =
msixTable_serverAdapterA_outDataCore$EMPTY_N && msixTable_serverAdapterA_outDataCore$EMPTY_N &&
msixTable_serverAdapterA_outDataCore$FULL_N && msixTable_serverAdapterA_outDataCore$FULL_N &&
msixTable_serverAdapterA_outData_deqCalled$whas && MUX_send_pending$write_1__SEL_2 &&
msixTable_serverAdapterA_outData_enqData$whas ; msixTable_serverAdapterA_outData_enqData$whas ;
   
// rule RL_s_config_1_axiWriteSpecialRange // rule RL_s_config_1_axiWriteSpecialRange
...@@ -4676,7 +4673,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -4676,7 +4673,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
s_config_writeSlave_in$EMPTY_N && s_config_writeSlave_in$EMPTY_N &&
s_config_writeSlave_out$FULL_N && s_config_writeSlave_out$FULL_N &&
msixTable_serverAdapterB_cnt_3_SLT_3___d168 && msixTable_serverAdapterB_cnt_3_SLT_3___d168 &&
i__h54995 < 16'd2112 && i__h54994 < 16'd2112 &&
!WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed ; !WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed ;
   
// rule RL_s_config_axiReadSpecialRangeDelayed // rule RL_s_config_axiReadSpecialRangeDelayed
...@@ -4700,7 +4697,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -4700,7 +4697,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
   
// rule RL_waitForCompletion // rule RL_waitForCompletion
assign WILL_FIRE_RL_waitForCompletion = assign WILL_FIRE_RL_waitForCompletion =
writeMaster_out$EMPTY_N && active && send_pending$port1__read && writeMaster_out$EMPTY_N && active && send_pending &&
!WILL_FIRE_RL_catchInterrupt_131 && !WILL_FIRE_RL_catchInterrupt_131 &&
!WILL_FIRE_RL_catchInterrupt_130 && !WILL_FIRE_RL_catchInterrupt_130 &&
!WILL_FIRE_RL_catchInterrupt_129 && !WILL_FIRE_RL_catchInterrupt_129 &&
...@@ -4835,7 +4832,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -4835,7 +4832,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
!WILL_FIRE_RL_catchInterrupt ; !WILL_FIRE_RL_catchInterrupt ;
   
// inputs to muxes for submodule ports // inputs to muxes for submodule ports
assign MUX_msixTable_memory$b_put_1__SEL_1 = assign MUX_msixTable_memory$b_put_2__SEL_1 =
WILL_FIRE_RL_s_config_1_axiWriteSpecialRange && WILL_FIRE_RL_s_config_1_axiWriteSpecialRange &&
(s_config_writeSlave_in$D_OUT[42:41] == 2'd0 || (s_config_writeSlave_in$D_OUT[42:41] == 2'd0 ||
s_config_writeSlave_in$D_OUT[42:41] == 2'd1 || s_config_writeSlave_in$D_OUT[42:41] == 2'd1 ||
...@@ -5239,6 +5236,9 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -5239,6 +5236,9 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
assign MUX_s_config_readBusy$write_1__SEL_1 = assign MUX_s_config_readBusy$write_1__SEL_1 =
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn_1 || WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn_1 ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn ; WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedReturn ;
assign MUX_send_pending$write_1__SEL_2 =
msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 &&
enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ;
always@(s_config_writeSlave_in$D_OUT) always@(s_config_writeSlave_in$D_OUT)
begin begin
case (s_config_writeSlave_in$D_OUT[42:41]) case (s_config_writeSlave_in$D_OUT[42:41])
...@@ -5249,7 +5249,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -5249,7 +5249,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
end end
assign MUX_msixTable_memory$b_put_3__VAL_1 = assign MUX_msixTable_memory$b_put_3__VAL_1 =
{3{s_config_writeSlave_in$D_OUT[38:7]}} ; {3{s_config_writeSlave_in$D_OUT[38:7]}} ;
assign MUX_s_config_readSlave_out$enq_1__VAL_1 = { v__h28374, 2'd0 } ; assign MUX_s_config_readSlave_out$enq_1__VAL_1 = { v__h28373, 2'd0 } ;
assign MUX_s_config_readSlave_out$enq_1__VAL_2 = { pbaRet$D_OUT, 2'd0 } ; assign MUX_s_config_readSlave_out$enq_1__VAL_2 = { pbaRet$D_OUT, 2'd0 } ;
assign MUX_s_config_readSlave_out$enq_1__VAL_3 = { id, 2'd0 } ; assign MUX_s_config_readSlave_out$enq_1__VAL_3 = { id, 2'd0 } ;
assign MUX_s_config_readSlave_out$enq_1__VAL_4 = { enableAndMask, 2'd0 } ; assign MUX_s_config_readSlave_out$enq_1__VAL_4 = { enableAndMask, 2'd0 } ;
...@@ -5280,14 +5280,14 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -5280,14 +5280,14 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
WILL_FIRE_RL_msixTable_serverAdapterB_outData_setFirstEnq || WILL_FIRE_RL_msixTable_serverAdapterB_outData_setFirstEnq ||
msixTable_serverAdapterB_outDataCore$EMPTY_N ; msixTable_serverAdapterB_outDataCore$EMPTY_N ;
assign msixTable_serverAdapterB_cnt_1$whas = assign msixTable_serverAdapterB_cnt_1$whas =
(MUX_msixTable_memory$b_put_1__SEL_1 || (MUX_msixTable_memory$b_put_2__SEL_1 ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed) && WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed) &&
(!ab__h18814[1] || ab__h18814[0]) ; (!ab__h18813[1] || ab__h18813[0]) ;
assign msixTable_serverAdapterB_writeWithResp$whas = assign msixTable_serverAdapterB_writeWithResp$whas =
MUX_msixTable_memory$b_put_1__SEL_1 || MUX_msixTable_memory$b_put_2__SEL_1 ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed ; WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayed ;
assign msixTable_serverAdapterB_s1_1$wget = assign msixTable_serverAdapterB_s1_1$wget =
{ 1'd1, !ab__h18814[1] || ab__h18814[0] } ; { 1'd1, !ab__h18813[1] || ab__h18813[0] } ;
assign s_config_readIsHandled$whas = assign s_config_readIsHandled$whas =
WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_3 ||
WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled_2 ||
...@@ -5295,9 +5295,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -5295,9 +5295,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
WILL_FIRE_RL_s_config_axiReadSpecialIsHandled || WILL_FIRE_RL_s_config_axiReadSpecialIsHandled ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 || WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled_1 ||
WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled ; WILL_FIRE_RL_s_config_axiReadSpecialRangeDelayedIsHandled ;
assign msixTable_serverAdapterA_outData_deqCalled$whas =
msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 &&
enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ;
assign s_config_writeSlave_addrIn_rv$EN_port0__write = assign s_config_writeSlave_addrIn_rv$EN_port0__write =
!s_config_writeSlave_addrIn_rv[19] && S_AXI_awvalid ; !s_config_writeSlave_addrIn_rv[19] && S_AXI_awvalid ;
assign s_config_writeSlave_addrIn_rv$port0__write_1 = assign s_config_writeSlave_addrIn_rv$port0__write_1 =
...@@ -5330,13 +5327,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -5330,13 +5327,6 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
s_config_writeSlave_dataIn_rv$EN_port1__write ? s_config_writeSlave_dataIn_rv$EN_port1__write ?
37'h0AAAAAAAAA : 37'h0AAAAAAAAA :
s_config_writeSlave_dataIn_rv$port1__read ; s_config_writeSlave_dataIn_rv$port1__read ;
assign send_pending$EN_port0__write =
msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 &&
enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ;
assign send_pending$port1__read =
send_pending$EN_port0__write || send_pending ;
assign send_pending$port2__read =
!WILL_FIRE_RL_waitForCompletion && send_pending$port1__read ;
assign nextInterrupt_rv$port1__read = assign nextInterrupt_rv$port1__read =
WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways ? WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways ?
9'd170 : 9'd170 :
...@@ -7137,7 +7127,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -7137,7 +7127,7 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32 ; msixTable_serverAdapterA_cnt_6_PLUS_IF_msixTab_ETC___d32 ;
assign msixTable_serverAdapterA_cnt$EN = assign msixTable_serverAdapterA_cnt$EN =
WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways || WILL_FIRE_RL_msixTable_serverAdapterA_stageReadResponseAlways ||
msixTable_serverAdapterA_outData_deqCalled$whas ; MUX_send_pending$write_1__SEL_2 ;
   
// register msixTable_serverAdapterA_s1 // register msixTable_serverAdapterA_s1
assign msixTable_serverAdapterA_s1$D_IN = assign msixTable_serverAdapterA_s1$D_IN =
...@@ -8125,12 +8115,15 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -8125,12 +8115,15 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
assign s_config_writeSlave_dataIn_rv$EN = 1'b1 ; assign s_config_writeSlave_dataIn_rv$EN = 1'b1 ;
   
// register send_pending // register send_pending
assign send_pending$D_IN = send_pending$port2__read ; assign send_pending$D_IN = !WILL_FIRE_RL_waitForCompletion ;
assign send_pending$EN = 1'b1 ; assign send_pending$EN =
WILL_FIRE_RL_waitForCompletion ||
msixTable_serverAdapterA_outDataCore_notEmpty__ETC___d1902 &&
enable_wget__02_BIT_0_14_AND_NOT_mask_wget__03_ETC___d1907 ;
   
// register sentReg // register sentReg
assign sentReg$D_IN = sentReg + 32'd1 ; assign sentReg$D_IN = sentReg + 32'd1 ;
assign sentReg$EN = msixTable_serverAdapterA_outData_deqCalled$whas ; assign sentReg$EN = MUX_send_pending$write_1__SEL_2 ;
   
// register vector_control_0 // register vector_control_0
assign vector_control_0$D_IN = s_config_writeSlave_in$D_OUT[7] ; assign vector_control_0$D_IN = s_config_writeSlave_in$D_OUT[7] ;
...@@ -9067,17 +9060,17 @@ module mkMSIXIntrCtrl(S_AXI_ACLK, ...@@ -9067,17 +9060,17 @@ module mkMSIXIntrCtrl(S_AXI_ACLK,
// submodule msixTable_memory // submodule msixTable_memory
assign msixTable_memory$ADDRA = nextInterrupt_rv[7:0] ; assign msixTable_memory$ADDRA = nextInterrupt_rv[7:0] ;
assign msixTable_memory$ADDRB = assign msixTable_memory$ADDRB =
MUX_msixTable_memory$b_put_1__SEL_1 ? MUX_msixTable_memory$b_put_2__SEL_1 ?
s_config_writeSlave_in$D_OUT[50:43] : s_config_writeSlave_in$D_OUT[50:43] :
s_config_readSlave_in$D_OUT[14:7] ; s_config_readSlave_in$D_OUT[14:7] ;
assign msixTable_memory$DIA = 96'd0 ; assign msixTable_memory$DIA = 96'd0 ;
assign msixTable_memory$DIB = assign msixTable_memory$DIB =
MUX_msixTable_memory$b_put_1__SEL_1 ? MUX_msixTable_memory$b_put_2__SEL_1 ?
MUX_msixTable_memory$b_put_3__VAL_1 : MUX_msixTable_memory$b_put_3__VAL_1 :
96'd0 ; 96'd0 ;
assign msixTable_memory$WEA = 12'd0 ; assign msixTable_memory$WEA = 12'd0 ;
assign msixTable_memory$WEB = assign msixTable_memory$WEB =
MUX_msixTable_memory$b_put_1__SEL_1 ? MUX_msixTable_memory$b_put_2__SEL_1 ?
MUX_msixTable_memory$b_put_1__VAL_1 : MUX_msixTable_memory$b_put_1__VAL_1 :
12'd0 ; 12'd0 ;
assign msixTable_memory$ENA =