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Commit 2fba2589 authored by Jens Korinth's avatar Jens Korinth
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VC709: Fix clock and reset wiring

parent 31e7a81c
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arch/axi4mm/axi4mm.tcl
View file @ 2fba2589
......@@ -347,43 +347,20 @@ namespace eval arch {
# Connect internal clock lines.
proc arch_connect_clocks {} {
set host_aclk [tapasco::subsystem::get_port "host" "clk"]
connect_bd_net $host_aclk [get_bd_pins -filter { NAME == "s_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
set design_aclk [tapasco::subsystem::get_port "design" "clk"]
connect_bd_net $design_aclk [get_bd_pins -filter { NAME == "m_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_aclk [get_bd_pins -filter { TYPE == clk && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip_*"}]]
puts " creating clock lines ..."
set memory_aclk [tapasco::subsystem::get_port "mem" "clk"]
if {[llength [get_bd_cells -filter {NAME =~ "out*"}]] > 0} {
connect_bd_net $design_aclk [get_bd_pins -filter { NAME == "s_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "out*"}]]
connect_bd_net $memory_aclk [get_bd_pins -filter { NAME == "m_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "out*"}]]
}
connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
[get_bd_pins -of_objects [get_bd_cells] -filter "TYPE == clk && DIR == I"]
}
# Connect internal reset lines.
proc arch_connect_resets {} {
# create hierarchical ports for host interconnect and peripheral resets
set host_ic_arstn [tapasco::subsystem::get_port "host" "rst" "interconnect"]
set host_p_arstn [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"]
connect_bd_net $host_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $host_p_arstn [get_bd_pins -filter { NAME == "s_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
# create hierarchical ports for design interconnect and peripheral resets
set design_ic_arstn [tapasco::subsystem::get_port "design" "rst" "interconnect"]
set design_p_arstn [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "m_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { NAME == "m_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { TYPE == rst && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip*"}]]
# create hierarchical ports for memory interconnect and peripheral resets
set memory_ic_arstn [tapasco::subsystem::get_port "mem" "rst" "interconnect"]
set memory_p_arstn [tapasco::subsystem::get_port "mem" "rst" "peripheral" "resetn"]
if {[llength [get_bd_cells -filter {NAME =~ "out*"}]] > 0} {
set outs [get_bd_cells -filter {NAME =~ "out*"}]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects $outs]
connect_bd_net $design_p_arstn [get_bd_pins -filter { NAME == "s_peripheral_aresetn" } -of_objects $outs]
connect_bd_net $memory_ic_arstn [get_bd_pins -filter { NAME == "m_interconnect_aresetn" } -of_objects $outs]
connect_bd_net $memory_p_arstn [get_bd_pins -filter { NAME == "m_peripheral_aresetn" } -of_objects $outs]
connect_bd_net [tapasco::subsystem::get_port "design" "rst" "interconnect"] \
[get_bd_pins -of_objects [get_bd_cells] -filter "TYPE == rst && NAME =~ *interconnect_aresetn && DIR == I"]
connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
[get_bd_pins -of_objects [get_bd_cells -of_objects [current_bd_instance .]] -filter "TYPE == rst && NAME =~ *peripheral_aresetn && DIR == I"] \
[get_bd_pins -filter { TYPE == rst && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip*"}]]
set active_high_resets [get_bd_pins -of_objects [get_bd_cells] -filter "TYPE == rst && DIR == I && CONFIG.POLARITY == ACTIVE_HIGH"]
if {[llength $active_high_resets] > 0} {
connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "reset"] $active_high_resets
}
}
......
common/common.tcl
View file @ 2fba2589
......@@ -431,14 +431,16 @@ namespace eval tapasco {
# @param name Name of the instance.
# @param from Data width on slave side (default: 256)
# @param to Data width on master side (default: 64)
proc createDWidthConverter {name {from "256"} {to "64"}} {
proc createDWidthConverter {name {from "256"} {to ""}} {
variable stdcomps
puts "Creating AXI Datawidth converter $name $from -> $to ..."
set vlnv [dict get $stdcomps dwidth_conv vlnv]
puts " VLNV: $vlnv"
set inst [create_bd_cell -type ip -vlnv $vlnv $name]
set_property -dict [list CCONFIG.SI_DATA_WIDTH $from CONFIG.MI_DATA_WIDTH $to] $inst
if {$to != ""} {
set_property -dict [list CCONFIG.SI_DATA_WIDTH $from CONFIG.MI_DATA_WIDTH $to] $inst
}
return $inst
}
......@@ -1041,7 +1043,7 @@ namespace eval tapasco {
"Clocks" [json::write array \
[json::write object "Domain" [json::write string "Host"] "Frequency" [tapasco::get_host_frequency]] \
[json::write object "Domain" [json::write string "Design"] "Frequency" [tapasco::get_design_frequency]] \
[json::write object "Domain" [json::write string "Memory"] "Frequency" [tapasco::get_host_frequency]] \
[json::write object "Domain" [json::write string "Memory"] "Frequency" [tapasco::get_memory_frequency]] \
] \
"Capabilities" [json::write object "Capabilities 0" [get_capabilities_flags]] \
]
......
common/subsystem.tcl
View file @ 2fba2589
......@@ -41,7 +41,6 @@ namespace eval subsystem {
set prstn [create_bd_pin -type rst -dir $d "${c}_peripheral_aresetn"]
set prst [create_bd_pin -type rst -dir $d "${c}_peripheral_areset"]
set irstn [create_bd_pin -type rst -dir $d "${c}_interconnect_aresetn"]
set_property CONFIG.POLARITY ACTIVE_LOW $prstn $irstn
}
current_bd_instance $instance
......
platform/common/platform.tcl
View file @ 2fba2589
......@@ -53,14 +53,6 @@ namespace eval platform {
current_bd_instance $instance
}
for {set i 1} {$i < [llength $sss]} {incr i} {
connect_bd_intf_net [get_bd_intf_pins [lindex $sss [expr "$i - 1"]]/M_CLOCKS_RESETS] \
[get_bd_intf_pins [lindex $sss $i]/S_CLOCKS_RESETS]
}
connect_bd_intf_net [get_bd_intf_pins [lindex $sss end]/M_CLOCKS_RESETS] \
[get_bd_intf_pins -of_objects [get_bd_cells "/uArch"] -filter "VLNV == [tapasco::get_vlnv "tapasco_clocks_resets"] && MODE == Slave"]
# create custom subsystems
foreach ss [info commands create_custom_subsystem_*] {
set name [regsub {.*create_custom_subsystem_(.*)} $ss {\1}]
......@@ -72,6 +64,25 @@ namespace eval platform {
wire_subsystem_wires
wire_subsystem_intfs
construct_address_map
}
proc construct_address_map {{map ""}} {
if {$map == ""} { set map [get_address_map [get_pe_base_address]] }
puts "ADDRESS MAP: $map"
}
proc connect_subsystems {} {
foreach s {host design mem} {
connect_bd_net [get_bd_pins -of_objects [get_bd_cells] -filter "NAME == ${s}_clk && DIR == O"] \
[get_bd_pins -of_objects [get_bd_cells] -filter "NAME =~ ${s}_clk && DIR == I"]
connect_bd_net [get_bd_pins -of_objects [get_bd_cells] -filter "NAME == ${s}_interconnect_resetn && DIR == O"] \
[get_bd_pins -of_objects [get_bd_cells] -filter "NAME =~ ${s}_interconnect_resetn && DIR == I"] \
connect_bd_net [get_bd_pins -of_objects [get_bd_cells] -filter "NAME == ${s}_peripheral_resetn && DIR == O"] \
[get_bd_pins -of_objects [get_bd_cells] -filter "NAME =~ ${s}_peripheral_resetn && DIR == I"] \
connect_bd_net [get_bd_pins -of_objects [get_bd_cells] -filter "NAME == ${s}_peripheral_reset && DIR == O"] \
[get_bd_pins -of_objects [get_bd_cells] -filter "NAME =~ ${s}_peripheral_resetn && DIR == O"] \
}
}
proc get_pe_base_address {} {
......@@ -83,7 +94,7 @@ namespace eval platform {
set tapasco_status [tapasco::createTapascoStatus "tapasco_status"]
connect_bd_intf_net $port [get_bd_intf_pins -of_objects $tapasco_status -filter "VLNV == [tapasco::get_vlnv aximm_intf] && MODE == Slave"]
connect_bd_net [tapasco::subsystem::get_port "design" "clk"] [get_bd_pins -of_objects $tapasco_status -filter {TYPE == clk && DIR == I}]
connect_bd_net [tapasco::subsystem::get_port "design" "peripheral" "rst" false] [get_bd_pins -of_objects $tapasco_status -filter {TYPE == rst && DIR == I}]
connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "reset"] [get_bd_pins -of_objects $tapasco_status -filter {TYPE == rst && DIR == I}]
}
proc wire_subsystem_wires {} {
......
platform/vc709/vc709.tcl
View file @ 2fba2589
......@@ -249,7 +249,7 @@ namespace eval platform {
set mm_to_lite_slice_before [tapasco::createRegisterSlice "mm_to_lite_slice_before"]
set mm_to_lite_slice_mid [tapasco::createRegisterSlice "mm_to_lite_slice_mid"]
set mm_to_lite_slice_after [tapasco::createRegisterSlice "mm_to_lite_slice_after"]
set mm_to_lite_dwidth [tapasco::createDWidthConverter "mm_to_lite_dwidth" 256 64]
set mm_to_lite_dwidth [tapasco::createDWidthConverter "mm_to_lite_dwidth" 256]
# connect PCIe slave to external port
connect_bd_intf_net $s_axi [get_bd_intf_pins axi_pcie3_0/S_AXI]
......@@ -274,22 +274,20 @@ namespace eval platform {
connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
[get_bd_pins $out_ic/ACLK] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == clk}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == clk}]
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == clk}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M03_* && TYPE == clk}]
connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M00_* && TYPE == clk}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M02_* && TYPE == clk}]
connect_bd_net [tapasco::subsystem::get_port "mem" "clk"] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M03_* && TYPE == clk}]
connect_bd_net [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"] \
[get_bd_pins $out_ic/ARESETN] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == rst}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == rst}]
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == rst}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M03_* && TYPE == rst}]
connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M00_* && TYPE == rst}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M02_* && TYPE == rst}]
connect_bd_net [tapasco::subsystem::get_port "mem" "rst" "peripheral" "resetn"] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M03_* && TYPE == rst}]
set version [lindex [split [get_property VLNV [get_bd_cells axi_pcie3_0]] :] end]
if {[expr "$version < 3.0"]} {
......
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