Commit 325673de authored by Jens Korinth's avatar Jens Korinth
Browse files

Fix reset behavior in RegisterFile

* AXI mandates that all ready signals be low during reset
* unfortunately, not only is this not the case in Queues, but they
  actively start working while reset is high (insane)
* fixed by manually pulling the signals low on reset
* tested with Xilinx AXI Verification IP, all's well
parent 5db38ae2
......@@ -163,4 +163,12 @@ class RegisterFile(cfg: RegisterFile.Configuration)
}
out_q_wr_enq_valid := true.B
}
when (reset.toBool) { // this is required for AXI compliance; apparently Queues start working while reset is high
io.saxi.readAddr.ready := false.B
io.saxi.readData.valid := false.B
io.saxi.writeAddr.ready := false.B
io.saxi.writeData.ready := false.B
io.saxi.writeResp.valid := false.B
}
}
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