Commit 328f9c33 authored by Jens Korinth's avatar Jens Korinth
Browse files

Remove outdated documentation in doc subdir

parent d0169b2d
MK ?= latexmk
MKFLAGS += -pdf
PDF = "Tapasco.pdf"
MAINTEX = Tapasco.tex
.PHONY: $(PDF) clean tikz tikz-clean
$(PDF): tikz
$(MK) $(MKFLAGS) $(MAINTEX)
clean: tikz-clean
$(MK) -C $(MAINTEX)
tikz:
$(MAKE) -C tikz
tikz-clean:
$(MAKE) -C tikz clean
\documentclass[a4paper, oneside, 11pt]{scrreprt}
\usepackage[utf8]{inputenc}
\usepackage[T1]{fontenc}
\usepackage{booktabs}
\usepackage{hyperref}
\usepackage{listings}
\usepackage{longtable}
\usepackage{array}
\usepackage{paralist}
\usepackage{rotating}
\usepackage{tikz}
\usetikzlibrary{arrows,backgrounds,shadows,shapes}
\usepackage{pgf-umlsd}
\newcolumntype{L}[1]{>{\raggedright\let\newline\\\arraybackslash\hspace{0pt}}m{#1}}
\newcolumntype{C}[1]{>{\centering\let\newline\\\arraybackslash\hspace{0pt}}m{#1}}
\newcolumntype{R}[1]{>{\raggedleft\let\newline\\\arraybackslash\hspace{0pt}}m{#1}}
\title{Threadpool Composer}
\subtitle{Installation and User Guide}
\date{}
\newcommand{\gloss}[1]{\textsf{\small #1}}
\newcommand{\tapasco}{\gloss{Tapasco}}
\newcommand{\tapascohome}{\code{TPC\_HOME}}
\newcommand{\code}[1]{\texttt{\footnotesize #1}}
\newcommand{\tblref}[1]{Table~\ref{#1}}
\newcommand{\figref}[1]{Figure~\ref{#1}}
\newcommand{\chpref}[1]{Chapter~\ref{#1}}
\newcommand{\secref}[1]{Section~\ref{#1}}
\newcommand{\lstref}[1]{Listing~\ref{#1}}
\lstset{
showstringspaces=false,
showspaces=false,
basicstyle=\footnotesize\ttfamily
}
\input{esacolors}
\newcommand{\lstnumbers}[1]{\smash{\ttfamily #1}}
\newcommand{\lstcomments}[1]{\smash{\color{gray}\ttfamily\itshape #1}}
\newcommand{\lstkeywords}[1]{\smash{\color{esa4}\ttfamily\bfseries #1}}
\newcommand{\fullscreen}[0]{\thispagestyle{empty}\vspace*{-15ex}}%
\lstdefinelanguage{kernel}{%
keywords={Name,Kernel,Version,ValueArgs,ReferenceArgs,ReturnSize,Files,TestbenchFiles},
comment=[l]{\#}
}
\lstdefinelanguage{arch}{%
keywords={Name,DesignTclTemplate,ReferenceArgTemplate,ValueArgTemplate},
comment=[l]{\#}
}
\lstdefinelanguage{platform}{%
keywords={Name,PlatformTclTemplate,Part,BoardPart},
comment=[l]{\#}
}
\lstdefinelanguage{bitstream}{%
keywords={Composition},
comment=[l]{\#}
}
\lstdefinelanguage{run}{%
keywords={Architecture, Platform, Bitstream, Kernel, ArchDir, KernelDir, PlatformDir, BitstreamDir},
comment=[l]{\#}
}
\lstdefinelanguage[TemplateTcl]{Tcl}[]{Tcl}{%
morecomment=**[s][\bfseries\color{green!30!black}]{@@}{@@},
morestring=*[b]"
}
\lstset{%
%frame = single,%
%backgroundcolor = \color{black!40},%
%numbers = left,%
basicstyle = \ttfamily\scriptsize, %
numberstyle = \lstnumbers, %
keywordstyle = \lstkeywords, %
commentstyle = \lstcomments
}
\usepackage[framemethod=tikz]{mdframed}
\newmdenv[innerlinewidth=0.5pt,
roundcorner=4pt,
linecolor=esa0!10!white,
innerleftmargin=6pt,
innerrightmargin=6pt,
innertopmargin=3pt,
innerbottommargin=3pt,
backgroundcolor=esa0!10!white
]{noteframe}
\newenvironment{note}[1][Note]{\begin{noteframe}\textbf{\color{esa3}#1 }\itshape}{\end{noteframe}}
\begin{document}
\maketitle
\input{revisions}
\tableofcontents
\chapter{Installation Guide}\label{chp:ig}
\input{ig.tex}
\chapter{User Guide}\label{chp:ug}
\input{ug.tex}
\chapter{Prototypical Implementations}\label{chp:ex}
\input{ex.tex}
\chapter{Appendix}\bibliographystyle{IEEEtran}
\bibliography{tapasco}
\end{document}
% define simple color names for esa colors and a highlight
\definecolor{esa}{RGB}{10,156,215}
\def\esacolorfactor{20}
\colorlet{esa0}{esa!90!white}
\colorlet{esa1}{black!\esacolorfactor!esa0}
\colorlet{esa2}{black!\esacolorfactor!esa1}
\colorlet{esa3}{black!\esacolorfactor!esa2}
\colorlet{esa4}{black!\esacolorfactor!esa3}
\colorlet{esa5}{black!\esacolorfactor!esa4}
\definecolor{highlight}{RGB}{189,27,27}
This chapter discusses the exemplary \gloss{Architecture} called \code{baseline} in \secref{sec:baseline-architecture} and \gloss{Platform} for Zynq-7000 series devices \code{zynq} in \secref{sec:zynq-platform}.
Finally, some of the examples which are part of the \tapasco{} archive are discussed and a small tutorial shows how ModelSim can be used to perform hardware/software co-simulation using the \tapasco{} libraries.
\figref{fig:baseline-zynq} illustrates a complete design for the exemplary \gloss{Architecture} and \gloss{Platform} for hypothetical \gloss{Composition} of \gloss{Kernels} "A-E" and is explained in detail in the following sections.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{The Zynq Platform}\label{sec:zynq-platform}
This \gloss{Platform} targets the Xilinx Zynq-7000 series of system-on-chips (SoC), which combine a \emph{28nm Artix-/Kintex-7 FPGA with dual core ARM Cortex A9 CPU} on a single chip.
The Zynq-7000 can be used as a standalone embedded system capable of running a variant of Linux using a standard Linux kernel.
The close connection of FPGA and CPU makes accessing the FPGA very convenient and eases prototyping.
Furthermore, one of the most interesting features of the Zynq-7000 is the fact that \emph{the CPU and the FPGA share main system memory}, via the so called ACP port it is even possible to use level-2 cache coherent memory accesses between CPU and FPGA.
This is a very interesting design, since usually FPGA accelerators are rather distant from the memory controllers, often being connected by peripheral buses with high throughput, but also high latency, such as PCIe.
On Zynq-7000 boards, memory accesses from the FPGA are almost on-par with the CPU.
This low latency access facilitates a \emph{zero-copy approach}:
In other design the common technique is to transfer the data for a \gloss{Job} to the device, compute, then transfer the data back.
On Zynq-7000 boards it is possible to directly access the shared main memory instead, removing the need for data transfer (zero copy).
This is the approach chosen for the \code{zynq} platform.
\paragraph{Host Connection}
The Zynq-7000 offers several AXI4 Master interfaces as hard IP, i.e., outside of the reconfigurable fabric.
To connect the threadpool register space, \code{zynq} uses the \code{GP0} port (cf. left-hand side of \figref{fig:baseline-zynq}), while it uses the \code{GP1} port to connect slave interfaces in the \gloss{Platform} infrastructure.
\paragraph{Memory Connection}
To access the shared main memory, the Zynq-7000 also offers several hard IP AXI4 Slave interfaces.
Since \tapasco{} is currently only providing thread-private memory to the hardware threads, memory coherency is not a primary concern.
The hardware threads can therefore be connected to the fastest AXI4 slaves, \code{HP0}-\code{HP2}, both of which can support up to 16 parallel masters, giving a total of 48 possible master interfaces.
\paragraph{Signaling}
The interrupt lines of the hardware threads are being connected to a standard component from the Xilinx IP catalog, the \emph{AXI4 Interrupt Controller IP}.
Among many features not even required for this simple \gloss{Platform}, it supports up to 32 edge- or level-sensitive interrupt lines.
The \gloss{Platform} automatically instantiates the required number of interrupt controller instances, depending on the number of interrupt wires returned by \code{arch\_get\_irqs}.
Each interrupt controller has itself an interrupt output wire, all of which are connected to the Zynq-7000 \code{IRQ2FP} port, which connects to the CPU interrupt controller.
The \code{IRQ2FP} port is up to 16bit wide, can support up to 16 AXI4 interrupt controllers, giving a maximum of $16 * 32 = 512$ hardware thread interrupts which could be supported by the design, which leaves a lot of room to scale.
\paragraph{Address Mapping}
The simple \code{zynq} implementation only requires register space addresses for the slave registers of the interrupt controllers.
They start at \code{0x80800000}, using a \code{0x1000} window each, thus the address space from \code{0x80800000-0x80810000} is reserved for the interrupt controllers and cannot be used by the threadpool.
\paragraph{Simulation Design}
For the simulation design, the \emph{Zynq Processing System BFM Core} is used instead of the regular core.
Furthermore, an instance of the \emph{AXI BFM Core} IP is also instantiated, which is a simulation core to easily generate AXI4 transactions in simulation.
It is very helpful to debug the memory system and accesses and is directly connected to the last of the high-performance memory ports, \code{HP3}.
\paragraph{Platform API: Simulation Implementation}
The \gloss{Platform API} is implemented in \code{platform/\allowbreak zynq/\allowbreak include/\allowbreak platform-api.svh}.
The implementation is straight-forward and uses the Zynq BFM core to simulate host accesses.
There is one slight deviation from the real design:
Since the simulator cannot actually access the memory located in the client process, data transfers must be performed in simulation; the AXI4 BFM core mentioned in the previous paragraph is used to perform that task and initializes the memory seen by the simulated hardware threads.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{The Baseline Architecture}\label{sec:baseline-architecture}
The \code{baseline} architecture serves as a proof-of-concept implementation for \tapasco{}, it shall support up to 48 independent hardware threads.
It is intended to be the simplest organization of a hardware threadpool which can be realized using only standard Xilinx IP components and the AXI4 bus.
Furthermore, as the name already suggests, this \gloss{Architecture} provides a reasonable baseline to compare future optimizations against.
\paragraph{HLS Directives}
The first design choice is to provide a AXI4Lite Slave interface (a simplified AXI4 slave without burst support) for all value arguments of a \gloss{Kernel}.
This can be achieved by the following directive template:
\lstinputlisting[language={[TemplateTcl]Tcl}, firstline=2]{../arch/baseline/valuearg.directives.template}
Reference arguments shall receive a AXI4 Master interface with a configurable base address register, which enables them to perform random access patterns:
\lstinputlisting[language={[TemplateTcl]Tcl}, firstline=1]{../arch/baseline/referencearg.directives.template}
\paragraph{Bus Structure}
Toward the host \code{baseline} therefore uses a two-tiered hierarchy of AXI4 Interconnect IPs (standard bus structure components from the Xilinx IP catalog), see "Host AXI Interconnect 1-3" in \figref{fig:baseline-zynq}.
In theory, each AXI4 Interconnect can support up to 16 Master/Slave interfaces each; yielding a theoretical maximum of $16 * 16 = 256$ slave interfaces, which easily suffices to accomodate the 48 hardware threads, even if some have several slave interfaces.
\medskip
Toward memory, \code{baseline} aims to provide reasonably short paths and uses only a single-tier of AXI4 Interconnects; "Mem AXI Interconnect 1-3" are connected to \code{HP0-2}, each supporting up to 16 independent masters, giving a total of $16 * 3 = 48$ masters this design can support, making at least one master per hardware thread possible.
Each of the \code{HPx} ports is mapped to the first GB of physical memory, making the address space \code{0x00000000-\allowbreak 0x3FFFFFFF} directly accessible to the hardware threads.
\medskip
\emph{Remark: In \figref{fig:baseline-zynq} "Mem AXI Interconnect 2" is actually connected to \code{HP2} instead of \code{HP1}.
The reason for this choice is that the pairs \code{HP0/1} and \code{HP2/3} are not completely disjoint in the hard IP and full performance cannot be achieved when saturating both \code{HP0} and \code{HP1}, or \code{HP2} and \code{HP3} at once.
Thus a minor performance boost can be achieved when connecting the first 32 hardware threads to \code{HP0} and \code{HP2} instead of \code{HP1}.}
\paragraph{Threadpool Organization}
The internal organization of the threadpool is as simple as possible:
Each \gloss{Kernel} in the \gloss{Composition} is instantiated the requested number of times and assigned ascending hardware thread slot IDs.
Each slave and master interface of the hardware threads is then connected to the first available master / slave interface on the host / memory interconnects.
This may result in asymmetric connections, and also in unused interfaces, as \figref{fig:baseline-zynq} illustrates:
In the center of the diagram the hardware threads are depicted, their left-hand side (slave interfaces) facing toward the host, their right-hand side (master interfaces) facing toward memory.
There are several unused slave interfaces on "Mem AXI Interconnect 2"; these will in fact not be instantiated, since the IP is freely configurable, and will thus not waste area in the final design.
\paragraph{Signaling}
By default, Vivado HLS automatically generates a level-sensitive interrupt line to indicate completion on the IP cores produced by HLS.
The array of interrupt lines returned by \code{arch\_get\_irqs} (see \tblref{tbl:architecture.tcl}) contains each of these interrupt lines ordered by the hardware thread slot ID.
\paragraph{Address Mappping}
In Zynq designs it is common to have the primary AXI peripheral address space begin at \code{0x43C00000}, so \code{baseline} adheres to this convention.
Each of the up to 48 hardware threads is mapped into a window of size \code{0x00010000}, thus the threadpool register space ranges from \code{0x43C00000-\allowbreak 0x43F00000}, as indicated on the left of \figref{fig:baseline-zynq}.
%
\begin{sidewaysfigure}[p]
\centering%
\includegraphics[width=\textwidth]{tikz/baseline_zynq}
\caption{Complete design for example composition using zynq Platform and baseline Architecture.}
\label{fig:baseline-zynq}
\end{sidewaysfigure}
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{Examples}\label{sec:examples}
TODO
\input{ig_prerequisites}%
\section{Compile Xilinx IP Catalog for ModelSim}\label{sec:compile_simlib}%
Vivado Design Suite contains the Xilinx IP catalog with many useful predefined IP cores, some of which are used by \tapasco{}.
In order to simulate such IP with ModelSim \cite{modelsim} and to speed up the simulation, the entire IP catalog should be precompiled for ModelSim once.
Please refer to Xilinx UG900 "Logic Simulation" \cite{ug900-2014.3}, Chapter 8, p. 134ff for instructions on how to compile the Xilinx IP catalog for ModelSim.
Place the compiled library in a location reachable from the system where \tapasco{} is to be executed, and point the environment variable \emph{COMPILED\_SIMLIB} to this location.
\section{Installation of Tapasco}%
\begin{enumerate}
\item Extract the \tapasco{} archive to a suitable location.
%
\begin{lstlisting}[language=bash]
~$ mkdir tapasco && cd tapasco && tar xvzf ../REPARA_D5.1_v1.0.tar.gz
\end{lstlisting}
%
\item Set the \code{TPC\_HOME} environment variable to that location, e.g.,
%
\begin{lstlisting}[language=bash]
~$ export TAPASCO_HOME=~/tapasco
\end{lstlisting}
%
\item Make sure that the system has a working internet connection for the next step.
\item Change into that directory and compile \tapasco{}:
\begin{lstlisting}[language=bash]
~$ cd $TAPASCO_HOME && sbt compile && sbt doc
[info] Loading project definition from /tmp/tapasco/project
[info] Updating {file:/tmp/tapasco/project/}tapasco-build...
[info] Resolving org.scala-sbt#compiler-interface;0.13.1 ...
...
[info] Done updating.
[info] Set current project to tapasco (in build file:/tmp/tapasco/)
Building dependencies ...
make: Entering directory `/tmp/tapasco/arch/baseline'
mkdir -p lib
cc -g -O3 -fPIC -Iinclude -I../common/include -I/tmp/tapasco/platform/common/include -I../common/src -std=gnu99 -pedantic-errors -Wall -Werror -shared -o lib/libtapasco-baseline-sim.so src/tapasco_sim.c src/tapasco_device.c src/tapasco_address_map.c ../common/src/tapasco_errors.c ../common/src/tapasco_functions.c ../common/src/tapasco_scheduler.c ../common/src/tapasco_jobs.c
cc -g -O3 -fPIC -Iinclude -I../common/include -I/tmp/tapasco/platform/common/include -I../common/src -std=gnu99 -pedantic-errors -Wall -Werror -shared -o lib/libtapasco-baseline-bit.so src/tapasco_sim.c src/tapasco_device.c src/tapasco_address_map.c ../common/src/tapasco_errors.c ../common/src/tapasco_functions.c ../common/src/tapasco_scheduler.c ../common/src/tapasco_jobs.c
make: Leaving directory `/tmp/tapasco/arch/baseline'
make: Entering directory `/tmp/tapasco/platform/zynq'
mkdir -p lib
cd include && /opt/cad/mentor/modelsim/latest/modeltech/bin/vlib work && /opt/cad/mentor/modelsim/latest/modeltech/bin/vlog -dpiheader platform_dpi.h -sv ../sv/platform-dpi.sv +incdir+../include && rm -rf work transcript
Model Technology ModelSim SE-64 vlog 10.0c_1 Compiler 2011.08 Aug 26 2011
-- Compiling module tb
Top level modules:
tb
cc -O3 -fPIC -I/opt/cad/mentor/modelsim/latest/modeltech/include -Iinclude -I../common/include -std=gnu99 -pedantic-errors -Wall -Werror -shared -pthread -o lib/libplatform-server.so src/platform_server.c
cc -O3 -fPIC -I/opt/cad/mentor/modelsim/latest/modeltech/include -Iinclude -I../common/include -std=gnu99 -pedantic-errors -Wall -Werror -shared -pthread -o lib/libplatform-client.so src/platform_client.c
make: Leaving directory `/tmp/tapasco/platform/zynq'
[info] Updating {file:/tmp/tapasco/}tapasco...
[info] Resolving com.dongxiguo#fastring_2.10;0.2.4 ...
[info] Done updating.
[info] Compiling 11 Scala sources to /tmp/tapasco/target/scala-2.10/classes...
[success] Total time: 13 s, completed Feb 10, 2015 5:45:43 PM
[info] Loading project definition from /tmp/tapasco/project
[info] Set current project to tapasco (in build file:/tmp/tapasco/)
[info] Main Scala API documentation to /tmp/tapasco/target/scala-2.10/api...
model contains 21 documentable templates
[info] Main Scala API documentation successful.
[success] Total time: 10 s, completed Feb 10, 2015 5:45:56 PM
~$
\end{lstlisting}
\end{enumerate}
The last step should trigger a number of downloads via \gloss{sbt}, C library compilation in subdirectories \code{arch} and \code{platform} and, finally, compilation of the main Scala code.
Please make sure that the system has a working internet connection for this step.
Downloading the packages via sbt is usually only necessary once, an internet connection is not required after the first downloads have succeeded.
Manual installation of the packages is also possible, if the system cannot be connected to the internet.
Please refer to the sbt documentation for instructions on how to make packages available to sbt with a manual installation.
\section{System Requirements}
\tapasco{} requires a computer running a \textsf{Linux} operating system with a 3.x series kernel.
It has been tested on a system running Fedora 22 Linux distribution, more precisely \code{GNU/Linux 3.19.5-100.fc20.x86\_64}.
The recommended Linux distribution for the Xilinx Zynq platforms is \emph{archlinux/ARM} \cite{archlinuxarm}, which is also the basis for the ready-for-use SDcard image files available on the \tapasco{} website.
No other system requirements have been identified for \tapasco{}, however, the requirements of subsequently listed third-party software apply.
\section{Prerequisites}
\tapasco{} is based on several third-party software components, the most important of which are listed in \tblref{tbl:thirdparty}.
If nothing else is explicitly specified in the corresponding section, C/C++ code can be built by the GNU project toolchain, specifically the GNU C Compiler gcc \cite{gcc} and GNU make \cite{gmake}, Scala code by the Scala compiler \cite{scala} and \gloss{sbt} \cite{sbt} (for supported versions see \tblref{tbl:thirdparty}).
It is likely possible to use different tools for these tasks, but is neither recommended nor supported.
\emph{Xilinx Vivado Design Suite} is used for all synthesis tasks, but the capabilities of the Vivado Simulator (specifically the SystemVerilog DPI implementation) are not sufficient for simulation, hence simulation is tailored toward \emph{Mentor Graphics ModelSim}.
With the exception of \gloss{sbt}, for which a micro-installation guide is provided in the next paragraph, a working installation of the software components is assumed.
Please refer to the corresponding vendor's documentation for installation instructions.
\begin{longtable}[c]{llcc}
\caption{Third-party software components and compatible versions}
\label{tbl:thirdparty}\\
\toprule
\textbf{Software Name} & \textbf{Vendor} & \textbf{Version} & \textbf{Mandatory}\\\midrule
\endhead
\bottomrule
\endlastfoot
gcc/g++ & Free Software Foundation, Inc. & $\geq$ 4.9 & Yes\\\midrule
ModelSim SE & Mentor Graphics Corporation & $\geq$ 10.0c\_1 & No\\\midrule
sbt & Typesafe, Inc. & $\geq$0.13.5 & Yes\\\midrule
Scala & \begin{minipage}{5cm}Programming Methods Laboratory of École Polytechnique Fédérale de Lausanne\end{minipage} & 2.10 & Yes\\\midrule
Vivado Design Suite & Xilinx, Inc. & 2015.2 & Yes\\
\end{longtable}
\subsection*{Installation of sbt}
In case no precompiled package for \gloss{sbt} is provided for your Linux distribution, a very simple manual installation of \gloss{sbt} is possible:
\begin{enumerate}
\item Download a compatible version of \code{sbt-launch.jar} at\\
\url{https://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt/sbt-launch/}.
\item Put \code{sbt-launch.jar} in a directory in the \code{PATH} environment variable, e.g., \code{\textasciitilde/bin}, or adapt your \code{PATH} accordingly.
\item At the same location, create a script \code{sbt}, with the following contents:
\begin{lstlisting}[language=bash]
SBT_OPTS="-Xms512M -Xmx1536M -Xss1M -XX:+CMSClassUnloadingEnabled \
-XX:MaxPermSize=256M"
java $SBT_OPTS -jar `dirname $0`/sbt-launch.jar "$@"
\end{lstlisting}
\end{enumerate}
Check if the installation was successful by running \code{sbt version} on a command line, it should finish without errors.
For more information about \gloss{sbt}, refer to \cite{sbt}.
\section{Paths and other preparations}
Make sure that all software components listed in \tblref{tbl:thirdparty} are accessible from the command line.
If necessary, add their location to the \code{PATH} environment variable or source appropriate scripts supplied by the vendor.
To check this, make sure you can run the following commands from the command line:
\begin{lstlisting}[language=bash, breaklines=true]
~$ echo exit | vivado_hls -i
~$ echo exit | vivado -nojournal -nolog -mode tcl
~$ echo quit | vsim -c
~$ gcc -v
~$ sbt version
\end{lstlisting}
Running the commands should yield output similar to this:
\begin{lstlisting}[language=bash, breaklines=true]
~$ echo exit | vivado_hls -i
================================================================
Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
Version 2015.2
Build 1266856 on Fri Jun 26 16:57:37 PM 2015
Copyright (C) 2015 Xilinx Inc. All rights reserved.
================================================================
@I [LIC-101] Checked out feature [VIVADO_HLS]
@I [HLS-10] Running '/opt/cad/xilinx/vivado/Vivado_HLS/2015.2/bin/unwrapped/lnx64.o/vivado_hls'
for user 'jk' on host 'mountdoom.esa.informatik.tu-darmstadt.de' (Linux_x86_64 version 3.19.5-100.fc20.x86_64) on Mon Nov 02 11:05:24 CET 2015
in directory '/home/jk/rcu/doc'
@E [HLS-70] There is an error calling 'vivado_hls'; try "-help'.
@I [LIC-101] Checked in feature [VIVADO_HLS]
================================================================
Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
Version 2014.3
Build 1034051 on Fri Oct 03 16:32:44 PM 2014
Copyright (C) 2014 Xilinx Inc. All rights reserved.
================================================================
@I [LIC-101] Checked out feature [VIVADO_HLS]
@I [HLS-10] Running '/opt/cad/xilinx/vivado/Vivado_HLS/2014.3/bin/unwrapped/lnx64.o/vivado_hls'
for user 'jk' on host 'mountdoom.esa.informatik.tu-darmstadt.de' (Linux_x86_64 version 3.17.8-200.fc20.x86_64) on Tue Feb 10 17:28:49 CET 2015
in directory '/home/jk'
@E [HLS-70] There is an error calling 'vivado_hls'; try "-help'.
@I [LIC-101] Checked in feature [VIVADO_HLS]
~ $ echo exit | vivado -nojournal -nolog -mode tcl
****** Vivado v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
**** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
exit
INFO: [Common 17-206] Exiting Vivado at Mon Nov 2 11:06:22 2015...
~$ echo quit | vsim -c
Reading /opt/cad/mentor/modelsim/modelsim-10.0c_1/modeltech/tcl/vsim/pref.tcl
# 10.0c_1
#
ModelSim> quit
~$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/local/libexec/gcc/x86_64-unknown-linux-gnu/5.2.0/lto-wrapper
Target: x86_64-unknown-linux-gnu
Configured with: ../5.2.0/configure
Thread model: posix
gcc version 5.2.0 (GCC)
~$ sbt version
[info] Set current project to jk (in build file:/home/jk/)
[info] 0.1-SNAPSHOT
~$
\end{lstlisting}
\input{ig_compile_simlib.tex}
\input{ig_installation.tex}
\begin{center}
\textbf{\huge Revision History}\\[1cm]
\begin{tabular}{C{.15\textwidth}L{.3\textwidth}L{.3\textwidth}R{.15\textwidth}}
\toprule
\textbf{Revision} & \textbf{Editor} & \textbf{Comment} & \textbf{Date}\\\midrule
1.0 & Jens Korinth (TU Darmstadt) & Initial version. & 11.02.2014\\
1.1 & Jens Korinth (TU Darmstadt) & Updated version. & 02.11.2015\\
\bottomrule
\end{tabular}
\end{center}
@misc{threadpool,
institution = {Wikimedia Foundation, Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{Threadpool Pattern}},
url = {http://en.wikipedia.org/wiki/Thread\_pool\_pattern},
urldate = {2015-02-05},
year = {2014}
}
@misc{sbt,
institution = {Typesafe Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{sbt - The interactive build tool}},
url = {http://www.scala-sbt.org/},
urldate = {2015-02-05},
year = {2014}
}
@misc{gcc,
institution = {Free Software Foundation, Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{GCC, the GNU Compiler Collection}},
url = {https://gcc.gnu.org/},
urldate = {2015-02-05},
year = {2014}
}
@misc{modelsim,
institution = {Mentor Graphics Corporation},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{ModelSim - ASIC and FPGA design}},
url = {http://www.mentor.com/products/fpga/simulation/modelsim},
urldate = {2015-02-05},
year = {2014}
}
@misc{kactus2,
institution = {Tampere University of Technology},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{Kactus2}},
url = {http://funbase.cs.tut.fi/\#kactus2},
urldate = {2015-02-05},
year = {2014}
}
@misc{ip-xact,
institution = {accellera Systems Initiative},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{IP-XACT}},
url = {http://www.accellera.org/activities/committees/ip-xact/},
urldate = {2015-02-05},
year = {2014}
}
@misc{vivado-hls,
institution = {Xilinx, Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{Vivado High-Level Synthesis}},
url = {http://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html},
urldate = {2015-02-05},
year = {2014}
}
@misc{ug900-2014.3,
institution = {Xilinx, Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{Vivado Design Suite User Guide - Logic Simulation}},
url = {http://www.xilinx.com/support/documentation/sw\_manuals/xilinx2014\_3/ug900-vivado-logic-simulation.pdf},
urldate = {2015-02-05},
year = {2014}
}
@misc{vivado,
institution = {Xilinx, Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{Vivado Design Suite}},
url = {http://www.xilinx.com/products/design-tools/vivado.html},
urldate = {2015-02-05},
year = {2015}
}
@misc{scala,
institution = {\'{E}cole Polytechnique F\'{e}d\'{e}rale de Lausanne (EPFL)},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{Scala - Object-Oriented Meets Functional}},
url = {http://www.scala-lang.org/},
urldate = {2015-02-05},
year = {2014}
}
@misc{legup,
institution = {University of Toronto},
keywords = {D5.1},
title = {{High-Level Synthesis with LegUp}},
url = {http://legup.eecg.utoronto.ca/},
urldate = {2014-02-05},
year = {2014}
}
@misc{gmake,
institution = {Free Software Foundation, Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{GNU Make}},
url = {http://www.gnu.org/software/make/},
urldate = {2015-02-05},
year = {2014}
}
@misc{ug902,
institution = {Xilinx, Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{Vivado Design Suite User Guide - High-level Synthesis}},
url = {http://www.xilinx.com/support/documentation/sw\_manuals/xilinx2014\_3/ug902-vivado-high-level-synthesis.pdf},
urldate = {2015-02-05},
year = {2014}
}
@misc{ug835,
institution = {Xilinx, Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{Vivado Design Suite User Guide - Tcl Command Reference Guide}},
url = {http://www.xilinx.com/support/documentation/sw\_manuals/xilinx2014\_3/ug835-vivado-tcl-commands.pdf},
urldate = {2014-05-02},
year = {2014}
}
@misc{sv-spec,
institution = {Accellera Organization, Inc.},
keywords = {D5.1},
mendeley-tags = {D5.1},
title = {{SystemVerilog 3.1a Language Reference Manual}},
url = {http://www.eda.org/sv/SystemVerilog\_3.1a.pdf},
urldate = {2014-05-02},
year = {2004}
}
@misc{archlinuxarm,
title = {{archlinux | ARM}},
author = {{ArchLinux Project}},
howpublished = "\url{http://archlinuxarm.org/platforms/armv7/xilinx/zedboard}"
}
PDFLATEX ?= pdflatex
.PHONY: all clean clean-pdf
TEXSRC=$(wildcard *.tex)
TEXPDF=$(patsubst %.tex,%.pdf,$(TEXSRC))
%.pdf: %.tex
$(PDFLATEX) $<
all: $(TEXPDF)
clean-pdf:
rm -f *.pdf *.log *.aux *.fdb_latexmk *.fls
clean: clean-pdf
\documentclass[border=0pt]{standalone}
\usepackage{tikz}
\usetikzlibrary{arrows}
\renewcommand\rmdefault{\sfdefault}
\input{../esacolors}
\begin{document}
\begin{tikzpicture} [
line width=1.5pt,
y=-1cm, x=3cm, rounded corners,
every node/.append style={align=center, font=\bfseries},
process background/.style={top color=esa0, bottom color=esa3, draw=esa5, fill=esa3}
]
\path [process background] (-.1, -1.1) rectangle (1.1, 7.1);
\node [font=\bfseries\large\color{white}] at (0.5, -.5) {User Process};
\begin{scope} [every path/.style={fill=white}]