More refactoring, started work on FifoAxiAdapterSpec

src/main/scala/AxiModuleBuilder.scala

@@ -77,7 +77,8 @@ object AxiModuleBuilder extends ModuleBuilder {
         () => AxiFifoAdapter(fifoDepth = 4)
                             (Axi4.Configuration(addrWidth = AddrWidth(32),
                                                 dataWidth = DataWidth(32),
-                                                idWidth   = IdWidth(1))),
+                                                idWidth   = IdWidth(1)),
+                             logLevel),
         CoreDefinition(
           name = "AxiFifoAdapter",
           vendor = "esa.cs.tu-darmstadt.de",
@@ -94,7 +95,7 @@ object AxiModuleBuilder extends ModuleBuilder {
             gen = UInt(8.W),
             width = 8,
             depth = 3,
-            afa = AxiFifoAdapterConfiguration(fifoDepth = 32, burstSize = Some(16))
+            afa = AxiFifoAdapter.Configuration(fifoDepth = 32, burstSize = Some(16))
           ))
         },
         CoreDefinition(

src/main/scala/axi4/AxiFifoAdapter.scala

 package chisel.axiutils
+import  chisel.axi._
+import  chisel.miscutils.Logging
 import  chisel3._
 import  chisel3.util._
-import  chisel.axi._
 
-/**
- * Configuration parameters for AxiFifoAdapter.
- * @param axi AXI-MM interface parameters.
- * @param fifoDepth Depth of the backing FIFO (each element data width wide).
- * @param burstSize Number of beats per burst (optional).
- * @param size Address wrap-around after size elements (optional).
- **/
-sealed case class AxiFifoAdapterConfiguration(fifoDepth: Int,
-                                              burstSize: Option[Int] = None,
-                                              size: Option[Int] = None)
+object AxiFifoAdapter {
+  /**
+   * Configuration parameters for AxiFifoAdapter.
+   * @param axi AXI-MM interface parameters.
+   * @param fifoDepth Depth of the backing FIFO (each element data width wide).
+   * @param burstSize Number of beats per burst (optional).
+   * @param size Address wrap-around after size elements (optional).
+   **/
+  sealed case class Configuration(fifoDepth: Int,
+                                  burstSize: Option[Int] = None,
+                                  size: Option[Int] = None)
 
-/**
- * I/O bundle for AxiFifoAdapter.
- **/
-class AxiFifoAdapterIO(cfg: AxiFifoAdapterConfiguration)
-                      (implicit axi: Axi4.Configuration) extends Bundle {
-  val maxi = Axi4.Master(axi)
-  val deq  = Decoupled(UInt(axi.dataWidth))
-  val base = Input(UInt(axi.addrWidth))
+  /**
+   * I/O bundle for AxiFifoAdapter.
+   **/
+  class IO(cfg: Configuration)(implicit axi: Axi4.Configuration) extends Bundle {
+    val maxi = Axi4.Master(axi)
+    val deq  = Decoupled(UInt(axi.dataWidth))
+    val base = Input(UInt(axi.addrWidth))
+  }
+
+  /**
+   * Build an AxiFifoAdapter.
+   * @param cfg Configuration.
+   * @return AxiFifoAdapter instance.
+   **/
+  def apply(cfg: Configuration)(implicit axi: Axi4.Configuration, l: Logging.Level): AxiFifoAdapter =
+    new AxiFifoAdapter(cfg)
+
+  /**
+   * Build an AxiFifoAdapter.
+   * @param fifoDepth Depth of the backing FIFO (each element data width wide).
+   * @param burstSize Number of beats per burst (optional).
+   * @param size Address wrap-around after size elements (optional).
+   * @return AxiFifoAdapter instance.
+   **/
+  def apply(fifoDepth: Int,
+            burstSize: Option[Int] = None,
+            size: Option[Int] = None)
+           (implicit axi: Axi4.Configuration, l: Logging.Level): AxiFifoAdapter =
+    new AxiFifoAdapter(Configuration(fifoDepth = fifoDepth, burstSize = burstSize, size = size))
 }
 
 /**
@@ -30,8 +53,9 @@ class AxiFifoAdapterIO(cfg: AxiFifoAdapterConfiguration)
  * interface; the FIFO itself uses handshakes for consumption.
  * @param cfg Configuration parameters.
  **/
-class AxiFifoAdapter(cfg: AxiFifoAdapterConfiguration)
-                    (implicit axi: Axi4.Configuration) extends Module {
+class AxiFifoAdapter(cfg: AxiFifoAdapter.Configuration)
+                    (implicit axi: Axi4.Configuration,
+                     logLevel: Logging.Level) extends Module with Logging{
   val bsz = cfg.burstSize.getOrElse(cfg.fifoDepth)
 
   require (cfg.size.map(s => log2Ceil(s) <= axi.addrWidth).getOrElse(true),
@@ -43,12 +67,12 @@ class AxiFifoAdapter(cfg: AxiFifoAdapterConfiguration)
            "burst size (%d) must be 0 < bsz <= FIFO depth (%d) <= 256"
            .format(bsz, cfg.fifoDepth))
 
-  println ("AxiFifoAdapter: fifoDepth = %d, address bits = %d, data bits = %d, id bits = %d%s%s"
-           .format(cfg.fifoDepth, axi.addrWidth:Int, axi.dataWidth:Int, axi.idWidth:Int,
-                   cfg.burstSize.map(", burst size = %d".format(_)).getOrElse(""),
-                   cfg.size.map(", size = %d".format(_)).getOrElse("")))
+  cinfo ("AxiFifoAdapter: fifoDepth = %d, address bits = %d, data bits = %d, id bits = %d%s%s"
+         .format(cfg.fifoDepth, axi.addrWidth:Int, axi.dataWidth:Int, axi.idWidth:Int,
+                 cfg.burstSize.map(", burst size = %d".format(_)).getOrElse(""),
+                 cfg.size.map(", size = %d".format(_)).getOrElse("")))
 
-  val io = IO(new AxiFifoAdapterIO(cfg))
+  val io = IO(new AxiFifoAdapter.IO(cfg))
 
   val axi_read :: axi_wait :: Nil = Enum(2)
 
@@ -110,26 +134,3 @@ class AxiFifoAdapter(cfg: AxiFifoAdapterConfiguration)
     }
   }
 }
-
-/** AxiFifoAdapter companion object: Factory methods. **/
-object AxiFifoAdapter {
-  /**
-   * Build an AxiFifoAdapter.
-   * @param cfg Configuration.
-   * @return AxiFifoAdapter instance.
-   **/
-  def apply(cfg: AxiFifoAdapterConfiguration)(implicit axi: Axi4.Configuration): AxiFifoAdapter = new AxiFifoAdapter(cfg)
-
-  /**
-   * Build an AxiFifoAdapter.
-   * @param fifoDepth Depth of the backing FIFO (each element data width wide).
-   * @param burstSize Number of beats per burst (optional).
-   * @param size Address wrap-around after size elements (optional).
-   * @return AxiFifoAdapter instance.
-   **/
-  def apply(fifoDepth: Int,
-            burstSize: Option[Int] = None,
-            size: Option[Int] = None)
-           (implicit axi: Axi4.Configuration): AxiFifoAdapter =
-    new AxiFifoAdapter(AxiFifoAdapterConfiguration(fifoDepth = fifoDepth, burstSize = burstSize, size = size))
-}

src/main/scala/axi4/FifoAxiAdapter.scala

 package chisel.axiutils
 import  chisel3._
 import  chisel3.util._
-import  chisel.axi.Axi4._
+import  chisel.axi._
 
-class FifoAxiAdapterIO(fifoDepth: Int)(implicit axi: Configuration) extends Bundle {
-  val maxi  = Master(axi)
-  val enq   = Flipped(Decoupled(UInt(axi.dataWidth)))
-  val base  = Input(UInt(axi.addrWidth))
-  val count = Output(UInt(log2Ceil(fifoDepth).W))
+object FifoAxiAdapter {
+  class IO(fifoDepth: Int)(implicit axi: Axi4.Configuration) extends Bundle {
+    val maxi  = Axi4.Master(axi)
+    val enq   = Flipped(Decoupled(UInt(axi.dataWidth)))
+    val base  = Input(UInt(axi.addrWidth))
+    val count = Output(UInt(log2Ceil(fifoDepth).W))
+  }
 }
 
 class FifoAxiAdapter(fifoDepth: Int,
                      burstSize: Option[Int] = None,
                      size: Option[Int] = None)
-                    (implicit axi: Configuration) extends Module {
+                    (implicit axi: Axi4.Configuration) extends Module {
 
   val bsz = burstSize getOrElse fifoDepth
 
@@ -29,7 +31,7 @@ class FifoAxiAdapter(fifoDepth: Int,
                    burstSize.map(", burst size = %d".format(_)).getOrElse(""),
                    size.map(", size = %d".format(_)).getOrElse("")))
 
-  val io = IO(new FifoAxiAdapterIO(fifoDepth))
+  val io = IO(new FifoAxiAdapter.IO(fifoDepth))
 
   val axi_write :: axi_wait :: Nil = Enum(2)
 
@@ -55,10 +57,10 @@ class FifoAxiAdapter(fifoDepth: Int,
   io.maxi.writeAddr.bits.addr        := maxi_waddr
   io.maxi.writeAddr.bits.burst.size  := (if (axi.dataWidth > 8) log2Ceil(axi.dataWidth / 8) else 0).U
   io.maxi.writeAddr.bits.burst.len   := (bsz - 1).U
-  io.maxi.writeAddr.bits.burst.burst := Burst.Type.incr
+  io.maxi.writeAddr.bits.burst.burst := Axi4.Burst.Type.incr
   io.maxi.writeAddr.bits.id          := 0.U
   io.maxi.writeAddr.bits.lock.lock   := 0.U
-  io.maxi.writeAddr.bits.cache.cache := Cache.Write.WRITE_THROUGH_RW_ALLOCATE
+  io.maxi.writeAddr.bits.cache.cache := Axi4.Cache.Write.WRITE_THROUGH_RW_ALLOCATE
   io.maxi.writeAddr.bits.prot.prot   := 0.U
   io.maxi.writeAddr.bits.qos         := 0.U
   io.maxi.writeData.bits.strb.strb   := ("b" + ("1" * (axi.dataWidth / 8))).U

src/main/scala/axi4/AxiSlidingWindow.scala → src/main/scala/axi4/SlidingWindow.scala

 package chisel.axiutils
-import  chisel.miscutils.DataWidthConverter
+import  chisel.miscutils.{DataWidthConverter, Logging}
 import  chisel.axi._
 import  chisel3._
 import  chisel3.util._
@@ -14,7 +14,7 @@ object SlidingWindow {
   sealed case class Configuration[T <: Data](gen: T,
                                              width: Int,
                                              depth: Int,
-                                             afa: AxiFifoAdapterConfiguration)
+                                             afa: AxiFifoAdapter.Configuration)
 
   /**
    * I/O Bundle for an AxiSlidingWindow:
@@ -30,7 +30,8 @@ object SlidingWindow {
   }
 
   def apply[T <: Data](cfg: SlidingWindow.Configuration[T])
-                      (implicit axi: Axi4.Configuration): SlidingWindow[T] =
+                      (implicit axi: Axi4.Configuration,
+                       logLevel: Logging.Level): SlidingWindow[T] =
     new SlidingWindow(cfg)
 }
 
@@ -44,7 +45,8 @@ object SlidingWindow {
  * @param cfg Configuration parameters.
  **/
 class SlidingWindow[T <: Data](val cfg: SlidingWindow.Configuration[T])
-                              (implicit axi: Axi4.Configuration) extends Module {
+                              (implicit axi: Axi4.Configuration,
+                               logLevel: Logging.Level) extends Module {
   val io = IO(new SlidingWindow.IO(cfg))
 
   /** AXI DMA engine **/

src/test/scala/axi4/AxiMuxSuite.scala

@@ -23,7 +23,7 @@ class AxiMuxReadTestModule(val n: Int)
   val mux = Module(new AxiMux(n))
   private val asmcfg = SlaveModel.Configuration(size = Some(n * 128))
   val saxi = Module(new SlaveModel(asmcfg))
-  private val afacfg = AxiFifoAdapterConfiguration(fifoDepth = 8, burstSize = Some(4))
+  private val afacfg = AxiFifoAdapter.Configuration(fifoDepth = 8, burstSize = Some(4))
   val afa = for (i <- 0 until n) yield Module(new AxiFifoAdapter(afacfg))
   val bases = (0 until n) map (_ * 128 * (axi.dataWidth / 8))
 

src/test/scala/axi4/FifoAxiAdapterSpec.scala

+package chisel.axiutils.axi4
+import  chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
+import  org.scalatest.prop.Checkers
+import  org.scalacheck._, org.scalacheck.Prop._
+
+class FifoAxiAdapterSpec extends ChiselFlatSpec with Checkers {
+  behavior of "FifoAxiAdapter"
+
+  it should "say hello" in {
+    check({ println("hello!"); true })
+  }
+
+  // it should "work with arbitrary configurations"
+}

src/test/scala/axi4/SlidingWindowSuite.scala

@@ -72,9 +72,9 @@ class SlidingWindowSuite extends ChiselFlatSpec {
   implicit val logLevel = Logging.Level.Info
   val chiselArgs = Array("--fint-write-vcd")
   implicit val axi: Axi4.Configuration = Axi4.Configuration(addrWidth = AddrWidth(32), dataWidth = DataWidth(64))
-  implicit val afa: AxiFifoAdapterConfiguration = AxiFifoAdapterConfiguration(fifoDepth = 16)
+  implicit val afa: AxiFifoAdapter.Configuration = AxiFifoAdapter.Configuration(fifoDepth = 16)
 
-  private def slidingWindow(width: Int, depth: Int)(implicit afa: AxiFifoAdapterConfiguration) = {
+  private def slidingWindow(width: Int, depth: Int)(implicit afa: AxiFifoAdapter.Configuration) = {
     val args = chiselArgs ++ Array("--target-dir", "test/slidingWindow/%dx%d".format(width, depth))
     val cfg = SlidingWindow.Configuration(gen = UInt(width.W),
                                           depth = depth,

src/test/scala/axi4/package.scala

+package chisel.axiutils.axi4
+import  chisel.axi._
+import  chisel.miscutils.generators._
+import  org.scalacheck._
+
+package object generators {
+  val axi4CfgGen: Gen[Axi4.Configuration] = for {
+    aw <- bitWidthGen(64)
+    dw <- bitWidthGen(1024)
+  } yield Axi4.Configuration(addrWidth = AddrWidth(aw), dataWidth = DataWidth(dw))
+
+  val fifoDepthGen: Gen[Limited[Int]] = genLimited(1, 16)
+}