Commit 36f55d76 authored by Jaco Hofmann's avatar Jaco Hofmann
Browse files

Use Xilinx IIC controller to program SI5324

parent bcd8f064
Pipeline #641 failed with stage
in 6 minutes and 28 seconds
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// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK `BSV_ARESET_EDGE_META) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module TriState
(
// Outputs
O,
// Inouts
IO,
// Inputs
OE, I
);
parameter width = 1;
input OE;
input [width-1:0] I;
output [width-1:0] O;
inout [width-1:0] IO;
assign IO = (OE) ? I : { width { 1'bz } };
assign O = IO;
endmodule // TriState
......@@ -57,17 +57,17 @@
puts $constraints_file_late {set_false_path -from [get_clocks gt_refclk_clk_p] -to [get_clocks -filter name=~*sfpmac_*gthe2_i/TXOUTCLK]}
puts $constraints_file {# Main I2C Bus - 100KHz - SUME}
puts $constraints_file {set_property IOSTANDARD LVCMOS18 [get_ports SCL_0]}
puts $constraints_file {set_property SLEW SLOW [get_ports SCL_0]}
puts $constraints_file {set_property DRIVE 16 [get_ports SCL_0]}
puts $constraints_file {set_property PULLUP true [get_ports SCL_0]}
puts $constraints_file {set_property PACKAGE_PIN AK24 [get_ports SCL_0]}
puts $constraints_file {set_property IOSTANDARD LVCMOS18 [get_ports SDA_0]}
puts $constraints_file {set_property SLEW SLOW [get_ports SDA_0]}
puts $constraints_file {set_property DRIVE 16 [get_ports SDA_0]}
puts $constraints_file {set_property PULLUP true [get_ports SDA_0]}
puts $constraints_file {set_property PACKAGE_PIN AK25 [get_ports SDA_0]}
puts $constraints_file {set_property IOSTANDARD LVCMOS18 [get_ports IIC_0_scl_io]}
puts $constraints_file {set_property SLEW SLOW [get_ports IIC_0_scl_io]}
puts $constraints_file {set_property DRIVE 16 [get_ports IIC_0_scl_io]}
puts $constraints_file {set_property PULLUP true [get_ports IIC_0_scl_io]}
puts $constraints_file {set_property PACKAGE_PIN AK24 [get_ports IIC_0_scl_io]}
puts $constraints_file {set_property IOSTANDARD LVCMOS18 [get_ports IIC_0_sda_io]}
puts $constraints_file {set_property SLEW SLOW [get_ports IIC_0_sda_io]}
puts $constraints_file {set_property DRIVE 16 [get_ports IIC_0_sda_io]}
puts $constraints_file {set_property PULLUP true [get_ports IIC_0_sda_io]}
puts $constraints_file {set_property PACKAGE_PIN AK25 [get_ports IIC_0_sda_io]}
puts $constraints_file {# i2c_reset[0] - i2c_mux reset - high active}
puts $constraints_file {# i2c_reset[1] - si5324 reset - high active}
......@@ -214,8 +214,15 @@
read_xdc $constraints_fn_late
set_property PROCESSING_ORDER LATE [get_files $constraints_fn_late]
make_bd_pins_external [get_bd_pins $si5324prog/SDA]
make_bd_pins_external [get_bd_pins $si5324prog/SCL]
set iic_controller [tapasco::ip::create_axi_iic "IICController"]
set_property -dict [list CONFIG.C_SCL_INERTIAL_DELAY {5} CONFIG.C_SDA_INERTIAL_DELAY {5} CONFIG.C_GPO_WIDTH {2}] $iic_controller
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC
connect_bd_intf_net [get_bd_intf_pin IIC] [get_bd_intf_pins $iic_controller/IIC]
connect_bd_intf_net [get_bd_intf_pin $si5324prog/M_AXI] [get_bd_intf_pins $iic_controller/S_AXI]
connect_bd_net [get_bd_pins $iic_controller/s_axi_aclk] [get_bd_pins $slow_clk]
connect_bd_net [get_bd_pins $si5324prog/CLK] $slow_clk
......@@ -223,6 +230,7 @@
connect_bd_net [get_bd_pins $rst_gen/slowest_sync_clk] $slow_clk
connect_bd_net $design_clk_aresetn [get_bd_pins $rst_gen/ext_reset_in]
connect_bd_net [get_bd_pins $rst_gen/peripheral_aresetn] [get_bd_pins $si5324prog/RST_N]
connect_bd_net [get_bd_pins $iic_controller/s_axi_aresetn] [get_bd_pins $rst_gen/peripheral_aresetn]
make_bd_pins_external [get_bd_pins $si5324prog/resetSwitch]
make_bd_pins_external [get_bd_pins $si5324prog/resetClock]
......@@ -237,19 +245,9 @@
current_bd_instance
make_bd_pins_external [get_bd_pins memory/mig/mmcm_locked]
make_bd_pins_external [get_bd_pins memory/mig/init_calib_complete]
make_bd_intf_pins_external [get_bd_intf_pins network/IIC]
current_bd_instance $inst
#set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 "net_ila"]
#set_property -dict [list CONFIG.C_DATA_DEPTH {8192} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_EN_STRG_QUAL {1} CONFIG.C_PROBE3_MU_CNT {2} CONFIG.C_PROBE2_MU_CNT {2} CONFIG.C_PROBE1_MU_CNT {2} CONFIG.C_PROBE0_MU_CNT {2} CONFIG.ALL_PROBE_SAME_MU_CNT {2} CONFIG.C_MON_TYPE {NATIVE}] $ila
#connect_bd_net [get_bd_pins $ila/clk] $slow_clk
#connect_bd_net [get_bd_pins $ila/probe0] [get_bd_pins $si5324prog/resetSwitch]
#connect_bd_net [get_bd_pins $ila/probe1] [get_bd_pins $si5324prog/resetClock]
#connect_bd_net [get_bd_pins $ila/probe2] [get_bd_pins $si5324prog/scl_debug]
#connect_bd_net [get_bd_pins $ila/probe3] [get_bd_pins $si5324prog/sda_debug]
#connect_bd_net [get_bd_pins $ila/probe4] [get_bd_pins $si5324prog/ident]
#connect_bd_net [get_bd_pins $ila/probe5] [get_bd_pins $si5324prog/step]
puts "SFP connections completed"
return {}
}
......
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