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Commit 3cdff64a authored by Jens Korinth's avatar Jens Korinth
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WIP: reimagine basic Platform construction 

* need to simplify Platform scripts, move more code into a common base
* will generalize and unify the basic structure of the project
* does not work yet, but looks promising
parent d04440b0
Pipeline #81 passed with stage
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arch/axi4mm/axi4mm.tcl
View file @ 3cdff64a
......@@ -40,7 +40,7 @@ namespace eval arch {
# Returns a list of the bd_cells of slave interfaces of the threadpool.
proc get_slaves {} {
set inst [current_bd_instance]
current_bd_instance "uArch"
current_bd_instance "/uArch"
set r [list [get_bd_intf_pins -of [get_bd_cells "in1"] -filter { MODE == "Slave" }]]
current_bd_instance $inst
return $r
......@@ -53,7 +53,7 @@ namespace eval arch {
}
proc get_processing_elements {} {
return [get_bd_cells "uArch/target*"]
return [get_bd_cells "/uArch/target*"]
}
# Returns a list of interrupt lines from the threadpool.
......@@ -178,7 +178,7 @@ namespace eval arch {
set ic_ports [list]
set mdist [list]
for {set i 0} {$i < [llength $outs] && $i < $no_masters} {incr i} {
lappend ic_ports [create_bd_intf_pin -mode Master -vlnv "xilinx.com:interface:aximm_rtl:1.0" [format "M_AXI_MEM_%02d" $i]]
lappend ic_ports [create_bd_intf_pin -mode Master -vlnv "xilinx.com:interface:aximm_rtl:1.0" [format "M_MEM_%d" $i]]
lappend mdist 0
}
......@@ -224,7 +224,7 @@ namespace eval arch {
puts "Creating interconnects toward peripherals ..."
puts " $ic_s slaves to connect to host"
set out_port [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI]
set out_port [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "S_ARCH"]
connect_bd_intf_net $out_port [get_bd_intf_pins -of_objects $in1 -filter {NAME == "S000_AXI"}]
return $in1
......@@ -347,13 +347,13 @@ namespace eval arch {
# Connect internal clock lines.
proc arch_connect_clocks {} {
set host_aclk [create_bd_pin -type clk -dir I "host_aclk"]
set host_aclk [platform::get_clock_reset_port "o_host_clk"]
connect_bd_net $host_aclk [get_bd_pins -filter { NAME == "s_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
set design_aclk [create_bd_pin -type clk -dir I "design_aclk"]
set design_aclk [platform::get_clock_reset_port "o_design_clk"]
connect_bd_net $design_aclk [get_bd_pins -filter { NAME == "m_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_aclk [get_bd_pins -filter { TYPE == clk && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip_*"}]]
puts " creating clock lines ..."
set memory_aclk [create_bd_pin -type clk -dir I "memory_aclk"]
set memory_aclk [platform::get_clock_reset_port "o_mem_clk"]
if {[llength [get_bd_cells -filter {NAME =~ "out*"}]] > 0} {
connect_bd_net $design_aclk [get_bd_pins -filter { NAME == "s_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "out*"}]]
connect_bd_net $memory_aclk [get_bd_pins -filter { NAME == "m_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "out*"}]]
......@@ -363,21 +363,21 @@ namespace eval arch {
# Connect internal reset lines.
proc arch_connect_resets {} {
# create hierarchical ports for host interconnect and peripheral resets
set host_ic_arstn [create_bd_pin -type rst -dir I "host_interconnect_aresetn"]
set host_p_arstn [create_bd_pin -type rst -dir I "host_peripheral_aresetn"]
set host_ic_arstn [platform::get_clock_reset_port "o_host_interconnect_resetn"]
set host_p_arstn [platform::get_clock_reset_port "o_host_peripheral_resetn"]
connect_bd_net $host_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $host_p_arstn [get_bd_pins -filter { NAME == "s_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
# create hierarchical ports for design interconnect and peripheral resets
set design_ic_arstn [create_bd_pin -type rst -dir I "design_interconnect_aresetn"]
set design_p_arstn [create_bd_pin -type rst -dir I "design_peripheral_aresetn"]
set design_ic_arstn [platform::get_clock_reset_port "o_design_interconnect_resetn"]
set design_p_arstn [platform::get_clock_reset_port "o_design_peripheral_resetn"]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "m_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { NAME == "m_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { TYPE == rst && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip*"}]]
# create hierarchical ports for memory interconnect and peripheral resets
set memory_ic_arstn [create_bd_pin -type rst -dir I "memory_interconnect_aresetn"]
set memory_p_arstn [create_bd_pin -type rst -dir I "memory_peripheral_aresetn"]
set memory_ic_arstn [platform::get_clock_reset_port "o_mem_interconnect_resetn"]
set memory_p_arstn [platform::get_clock_reset_port "o_mem_peripheral_resetn"]
if {[llength [get_bd_cells -filter {NAME =~ "out*"}]] > 0} {
set outs [get_bd_cells -filter {NAME =~ "out*"}]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects $outs]
......@@ -397,7 +397,7 @@ namespace eval arch {
}
# create hierarchical group
set group [create_bd_cell -type hier "uArch"]
set group [platform::create_subsystem "uArch" true false]
set instance [current_bd_instance .]
current_bd_instance $group
......
common/common.tcl
View file @ 3cdff64a
......@@ -1009,7 +1009,7 @@ namespace eval tapasco {
# Generate JSON configuration for the status core.
proc make_status_config_json {} {
set addr [platform::get_address_map]
set addr [platform::get_address_map [platform::get_pe_base_address]]
set slots [list]
set slot_id 0
foreach a $addr {
......
platform/common/platform.tcl
View file @ 3cdff64a
......@@ -21,15 +21,176 @@
# @author J. Korinth, TU Darmstadt (jk@esa.tu-darmstadt.de)
#
namespace eval platform {
namespace export create
namespace export generate
namespace export get_address_map
# Creates the platform infrastructure, consisting of a number of subsystems.
# Subsystems "host", "clocks_and_resets", "memory", "intc" and "tapasco" are
# mandatory, their wiring pre-defined. Custom subsystems can be instantiated
# by implementing a "create_custom_subsystem_<NAME>" proc in platform::, where
# <NAME> is a placeholder for the name of the subsystem.
proc create {} {
set instance [current_bd_instance]
# create mandatory subsystems
set ss_host [create_subsystem "host"]
set ss_cnrs [create_subsystem "clocks_and_resets" false true]
set ss_mem [create_subsystem "memory"]
set ss_intc [create_subsystem "intc"]
set ss_tapasco [create_subsystem "tapasco"]
set sss [list $ss_cnrs $ss_host $ss_intc $ss_mem $ss_tapasco]
foreach ss $sss {
set name [string trim $ss "/"]
set cmd "create_subsystem_$name"
puts "Creating subsystem $name ..."
if {[llength [info commands $cmd]] == 0} {
error "Platform does not implement mandatory command $cmd!"
}
current_bd_instance $ss
eval $cmd
current_bd_instance $instance
}
for {set i 1} {$i < [llength $sss]} {incr i} {
connect_bd_intf_net [get_bd_intf_pins [lindex $sss [expr "$i - 1"]]/M_CLOCKS_RESETS] \
[get_bd_intf_pins [lindex $sss $i]/S_CLOCKS_RESETS]
}
connect_bd_intf_net [get_bd_intf_pins [lindex $sss end]/M_CLOCKS_RESETS] \
[get_bd_intf_pins -of_objects [get_bd_cells "/uArch"] -filter "VLNV == [tapasco::get_vlnv "tapasco_clocks_resets"] && MODE == Slave"]
# create custom subsystems
foreach ss [info commands create_custom_subsystem_*] {
set name [regsub {.*create_custom_subsystem_(.*)} $ss {\1}]
puts "Creating custom subsystem $name ..."
current_bd_instance [create_subsystem $name]
eval $ss
current_bd_instance $instance
}
wire_subsystem_wires
wire_subsystem_intfs
}
# Creates a hierarchical cell with given name and instantiates either a
# ClocksResetsBridgeMaster or ClocksResetsBridgeSlave, depending on whether
# is_reset is true or false, respectively. get_clock_reset_port can be used
# to access the pins in this component.
proc create_subsystem {name {has_slave true} {has_master true}} {
set instance [current_bd_instance]
set cell [create_bd_cell -type hier $name]
set intf_vlnv [tapasco::get_vlnv "tapasco_clocks_resets"]
current_bd_instance $cell
if {$has_master} {
set m_port [create_bd_intf_pin -vlnv $intf_vlnv -mode Master "M_CLOCKS_RESETS"]
set m_cnrs [create_bd_cell -type ip -vlnv [tapasco::get_vlnv "clocks_resets_m"] "m_cnrs"]
connect_bd_intf_net [get_bd_intf_pins -of_objects $m_cnrs -filter "VLNV == $intf_vlnv"] $m_port
}
if {$has_slave} {
set s_port [create_bd_intf_pin -vlnv $intf_vlnv -mode Slave "S_CLOCKS_RESETS"]
set s_cnrs [create_bd_cell -type ip -vlnv [tapasco::get_vlnv "clocks_resets_s"] "s_cnrs"]
connect_bd_intf_net $s_port [get_bd_intf_pins -of_objects $s_cnrs -filter "VLNV == $intf_vlnv"]
}
if {$has_master && $has_slave} {
# directly connect all wires
foreach p [get_bd_pins -of_objects $m_cnrs -filter { NAME =~ i_* }] {
set oname [regsub {i_} [get_property NAME $p] {o_}]
set op [get_bd_pins -of_objects $s_cnrs -filter "NAME == $oname"]
puts " connecting $p to $op ..."
connect_bd_net $p $op
}
}
current_bd_instance $instance
return $cell
}
# Returns pin with given name on the clocks and resets bridge component in
# the current subsystem.
proc get_clock_reset_port {name} {
set cells [get_bd_cells -filter "VLNV == [tapasco::get_vlnv clocks_resets_s] || VLNV == [tapasco::get_vlnv clocks_resets_m]"]
return [get_bd_pins -of_objects $cells -filter "NAME == $name && INTF == false"]
}
proc get_pe_base_address {} {
error "Platform does not implement mandatory proc get_pe_base_address!"
}
proc create_subsystem_tapasco {} {
set port [create_bd_intf_pin -vlnv [tapasco::get_vlnv "aximm_intf"] -mode Slave "S_TAPASCO"]
set tapasco_status [tapasco::createTapascoStatus "tapasco_status"]
connect_bd_intf_net $port [get_bd_intf_pins -of_objects $tapasco_status -filter "VLNV == [tapasco::get_vlnv aximm_intf] && MODE == Slave"]
connect_bd_net [get_clock_reset_port "o_design_clk"] [get_bd_pins -of_objects $tapasco_status -filter {TYPE == clk && DIR == I}]
connect_bd_net [get_clock_reset_port "o_design_peripheral_reset"] [get_bd_pins -of_objects $tapasco_status -filter {TYPE == rst && DIR == I}]
}
proc wire_subsystem_wires {} {
foreach p [get_bd_pins -of_objects [get_bd_cells] -filter {INTF == false && DIR == I}] {
if {[llength [get_bd_nets -of_objects $p]] == 0} {
set name [get_property NAME $p]
set type [get_property TYPE $p]
puts "Looking for matching source for $p ($name) with type $type ..."
set src [get_bd_pins -of_objects [get_bd_cells] -filter "NAME == $name && TYPE == $type && INTF == false && DIR == O"]
if {[llength $src] > 0} {
puts " found pin: $src, connecting $p -> $src"
connect_bd_net $src $p
} else {
puts " found no matching pin for $p"
}
}
}
}
proc wire_subsystem_intfs {} {
foreach p [get_bd_intf_pins -of_objects [get_bd_cells] -filter {MODE == Slave}] {
if {[llength [get_bd_intf_nets -of_objects $p]] == 0} {
set name [regsub {^S_} [get_property NAME $p] {M_}]
set vlnv [get_property VLNV $p]
puts "Looking for matching source for $p ($name) with VLNV $vlnv ..."
set srcs [lsort [get_bd_intf_pins -of_objects [get_bd_cells] -filter "NAME == $name && VLNV == $vlnv && MODE == Master"]]
foreach src $srcs {
if {[llength [get_bd_intf_nets -of_objects $src]] == 0} {
puts " found pin: $src, connecting $p -> $src"
connect_bd_intf_net $src $p
break
} else {
puts " found no matching pin for $p"
}
}
}
}
}
# Returns the address map of the current composition.
# Format: <SLAVE INTF> <BASE ADDR> <RANGE> <KIND>
# Kind is either Mem or Register, depending on the usage.
# Must be implemented by Platforms.
proc get_address_map {} {
error "Platform does not implement get_address_map!"
proc get_address_map {offset} {
set ret [list]
set pes [lsort [arch::get_processing_elements]]
#set offset 0x00300000
foreach pe $pes {
set usrs [lsort [get_bd_addr_segs $pe/* -filter { USAGE != memory }]]
for {set i 0} {$i < [llength $usrs]} {incr i; incr offset 0x10000} {
set seg [lindex $usrs $i]
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
lappend ret "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind register"
}
set usrs [lsort [get_bd_addr_segs $pe/* -filter { USAGE == memory }]]
for {set i 0} {$i < [llength $usrs]} {incr i; incr offset 0x10000} {
set seg [lindex $usrs $i]
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
lappend ret "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind memory"
}
}
return $ret
}
# Checks all current runs at given step for errors, outputs their log files in case.
......
platform/vc709/vc709.tcl
View file @ 3cdff64a
This diff is collapsed.
platform/zynq/zynq.tcl
View file @ 3cdff64a
......@@ -43,27 +43,8 @@ namespace eval platform {
return [list 64 64]
}
proc get_address_map {} {
set ret [list]
set pes [lsort [arch::get_processing_elements]]
set offset 0x43C00000
foreach pe $pes {
set usrs [lsort [get_bd_addr_segs $pe/* -filter { USAGE != memory }]]
for {set i 0} {$i < [llength $usrs]} {incr i; incr offset 0x10000} {
set seg [lindex $usrs $i]
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
lappend ret "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind register"
}
set usrs [lsort [get_bd_addr_segs $pe/* -filter { USAGE == memory }]]
for {set i 0} {$i < [llength $usrs]} {incr i; incr offset 0x10000} {
set seg [lindex $usrs $i]
set intf [get_bd_intf_pins -of_objects $seg]
set range [get_property RANGE $seg]
lappend ret "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind memory"
}
}
return $ret
proc get_pe_base_address {} {
return 0x43C00000
}
# Setup the clock network.
......
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