Commit 410607d7 authored by Jens Korinth's avatar Jens Korinth
Browse files

AXIMasterIF: renameSignals with prefix and suffix

* renameSignals on AXI bundle should support prefix and suffix in order
  to accomodate multiple instance of the interface in one module
parent 962277e9
......@@ -75,49 +75,49 @@ class AXIMasterIF(addrWidthBits: Int, dataWidthBits: Int, idBits: Int) extends B
val readData = Decoupled(new AXIReadData(dataWidthBits, idBits)).flip
// rename signals to be compatible with those in the Xilinx template
def renameSignals() {
def renameSignals(prefix: Option[String], suffix: Option[String]) = {
// write address channel
writeAddr.bits.addr.setName("M_AXI_AWADDR")
writeAddr.bits.prot.setName("M_AXI_AWPROT")
writeAddr.bits.size.setName("M_AXI_AWSIZE")
writeAddr.bits.len.setName("M_AXI_AWLEN")
writeAddr.bits.burst.setName("M_AXI_AWBURST")
writeAddr.bits.lock.setName("M_AXI_AWLOCK")
writeAddr.bits.cache.setName("M_AXI_AWCACHE")
writeAddr.bits.qos.setName("M_AXI_AWQOS")
writeAddr.bits.id.setName("M_AXI_AWID")
writeAddr.valid.setName("M_AXI_AWVALID")
writeAddr.ready.setName("M_AXI_AWREADY")
writeAddr.bits.addr.setName("%sM_AXI_AWADDR%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.bits.prot.setName("%sM_AXI_AWPROT%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.bits.size.setName("%sM_AXI_AWSIZE%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.bits.len.setName("%sM_AXI_AWLEN%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.bits.burst.setName("%sM_AXI_AWBURST%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.bits.lock.setName("%sM_AXI_AWLOCK%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.bits.cache.setName("%sM_AXI_AWCACHE%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.bits.qos.setName("%sM_AXI_AWQOS%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.bits.id.setName("%sM_AXI_AWID%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.valid.setName("%sM_AXI_AWVALID%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeAddr.ready.setName("%sM_AXI_AWREADY%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
// write data channel
writeData.bits.data.setName("M_AXI_WDATA")
writeData.bits.strb.setName("M_AXI_WSTRB")
writeData.bits.last.setName("M_AXI_WLAST")
writeData.valid.setName("M_AXI_WVALID")
writeData.ready.setName("M_AXI_WREADY")
writeData.bits.data.setName("%sM_AXI_WDATA%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeData.bits.strb.setName("%sM_AXI_WSTRB%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeData.bits.last.setName("%sM_AXI_WLAST%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeData.valid.setName("%sM_AXI_WVALID%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeData.ready.setName("%sM_AXI_WREADY%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
// write response channel
writeResp.bits.resp.setName("M_AXI_BRESP")
writeResp.bits.id.setName("M_AXI_BID")
writeResp.valid.setName("M_AXI_BVALID")
writeResp.ready.setName("M_AXI_BREADY")
writeResp.bits.resp.setName("%sM_AXI_BRESP%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeResp.bits.id.setName("%sM_AXI_BID%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeResp.valid.setName("%sM_AXI_BVALID%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
writeResp.ready.setName("%sM_AXI_BREADY%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
// read address channel
readAddr.bits.addr.setName("M_AXI_ARADDR")
readAddr.bits.prot.setName("M_AXI_ARPROT")
readAddr.bits.size.setName("M_AXI_ARSIZE")
readAddr.bits.len.setName("M_AXI_ARLEN")
readAddr.bits.burst.setName("M_AXI_ARBURST")
readAddr.bits.lock.setName("M_AXI_ARLOCK")
readAddr.bits.cache.setName("M_AXI_ARCACHE")
readAddr.bits.qos.setName("M_AXI_ARQOS")
readAddr.bits.id.setName("M_AXI_ARID")
readAddr.valid.setName("M_AXI_ARVALID")
readAddr.ready.setName("M_AXI_ARREADY")
readAddr.bits.addr.setName("%sM_AXI_ARADDR%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.bits.prot.setName("%sM_AXI_ARPROT%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.bits.size.setName("%sM_AXI_ARSIZE%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.bits.len.setName("%sM_AXI_ARLEN%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.bits.burst.setName("%sM_AXI_ARBURST%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.bits.lock.setName("%sM_AXI_ARLOCK%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.bits.cache.setName("%sM_AXI_ARCACHE%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.bits.qos.setName("%sM_AXI_ARQOS%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.bits.id.setName("%sM_AXI_ARID%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.valid.setName("%sM_AXI_ARVALID%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readAddr.ready.setName("%sM_AXI_ARREADY%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
// read data channel
readData.bits.id.setName("M_AXI_RID")
readData.bits.data.setName("M_AXI_RDATA")
readData.bits.resp.setName("M_AXI_RRESP")
readData.bits.last.setName("M_AXI_RLAST")
readData.valid.setName("M_AXI_RVALID")
readData.ready.setName("M_AXI_RREADY")
readData.bits.id.setName("%sM_AXI_RID%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readData.bits.data.setName("%sM_AXI_RDATA%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readData.bits.resp.setName("%sM_AXI_RRESP%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readData.bits.last.setName("%sM_AXI_RLAST%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readData.valid.setName("%sM_AXI_RVALID%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
readData.ready.setName("%sM_AXI_RREADY%s".format(prefix.getOrElse(""), suffix.getOrElse("")))
}
override def clone = { new AXIMasterIF(addrWidthBits, dataWidthBits, idBits).asInstanceOf[this.type] }
......
......@@ -21,7 +21,7 @@ class FifoAxiAdapterTest1(dataWidth : Int, size: Int) extends Module {
dataWidth = dataWidth,
burstSize = Some(16)))
io.maxi.renameSignals()
io.maxi.renameSignals(None, None)
io.base.setName("base")
fad.io.base := io.base
......
......@@ -33,7 +33,7 @@ class AxiSlidingWindowIO[T <: Data](cfg: AxiSlidingWindowConfiguration[T]) exten
data.ready.setName("DATA_READY")
data.valid.setName("DATA_VALID")
for (i <- 0 until cfg.depth) data.bits(i).setName("DATA_%02d".format(i))
maxi.renameSignals()
maxi.renameSignals(None, None)
}
}
......
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